tree 51f5cdcfc6ce98abd5a7cd4214eeff51af9b1ea2
parent ddf7d79bc739c44f7e7cdffc9eb5d94aa213f53e
author Russell King <rmk+kernel@arm.linux.org.uk> 1395243549 +0000
committer Russell King <rmk+kernel@arm.linux.org.uk> 1401407330 +0100

ARM: l2c: add automatic enable of early BRESP

The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted.  Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.

Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>