tree c66ae0aa4a76117608883d28cc8bd4c392e2d1b7
parent df2537f910400cd4f90d2ecb40a0a1a204d8470c
author Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> 1606411108 -0800
committer Daniel Lezcano <daniel.lezcano@linaro.org> 1607599789 +0100

thermal: int340x: processor_thermal: Add RFIM driver

Add support for RFIM (Radio Frequency Interference Mitigation) support
via processor thermal PCI device. This drivers allows adjustment of
FIVR (Fully Integrated Voltage Regulator) and DDR (Double Data Rate)
frequencies to avoid RF interference with WiFi and 5G.

Switching voltage regulators (VR) generate radiated EMI or RFI at the
fundamental frequency and its harmonics. Some harmonics may interfere
with very sensitive wireless receivers such as Wi-Fi and cellular that
are integrated into host systems like notebook PCs.  One of mitigation
methods is requesting SOC integrated VR (IVR) switching frequency to a
small % and shift away the switching noise harmonic interference from
radio channels.  OEM or ODMs can use the driver to control SOC IVR
operation within the range where it does not impact IVR performance.

DRAM devices of DDR IO interface and their power plane can generate EMI
at the data rates. Similar to IVR control mechanism, Intel offers a
mechanism by which DDR data rates can be changed if several conditions
are met: there is strong RFI interference because of DDR; CPU power
management has no other restriction in changing DDR data rates;
PC ODMs enable this feature (real time DDR RFI Mitigation referred to as
DDR-RFIM) for Wi-Fi from BIOS.

This change exports two folders under /sys/bus/pci/devices/0000:00:04.0.
One folder "fivr" contains all attributes exposed for controling FIVR
features. The other folder "dvfs" contains all attributes for DDR
features.

Changes done to implement:
- New module for rfim interfaces
- Two new per processor features for DDR and FIVR
- Enable feature for Tiger Lake (FIVR only) and Alder Lake

The attributes exposed and explanation:

FIVR attributes

vco_ref_code_lo (RW): The VCO reference code is an 11-bit field and
controls the FIVR switching frequency. This is the 3-bit LSB field.

vco_ref_code_hi (RW): The VCO reference code is an 11-bit field and
controls the FIVR switching frequency. This is the 8-bit MSB field.

spread_spectrum_pct (RW): Set the FIVR spread spectrum clocking
percentage

spread_spectrum_clk_enable (RW): Enable/disable of the FIVR spread
spectrum clocking feature

rfi_vco_ref_code (RW): This field is a read only status register which
reflects the current FIVR switching frequency

fivr_fffc_rev (RW): This field indicated the revision of the FIVR HW.

DVFS attributes

rfi_restriction_run_busy (RW): Request the restriction of specific DDR
data rate and set this value 1. Self reset to 0 after operation.

rfi_restriction_err_code (RW): Values:  0 :Request is accepted, 1:Feature
disabled, 2: the request restricts more points than it is allowed

rfi_restriction_data_rate_Delta (RW): Restricted DDR data rate for RFI
protection: Lower Limit

rfi_restriction_data_rate_Base (RW): Restricted DDR data rate for RFI
protection: Upper Limit

ddr_data_rate_point_0 (RO): DDR data rate selection 1st point

ddr_data_rate_point_1 (RO): DDR data rate selection 2nd point

ddr_data_rate_point_2 (RO): DDR data rate selection 3rd point

ddr_data_rate_point_3 (RO): DDR data rate selection 4th point

rfi_disable (RW): Disable DDR rate change feature

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20201126171829.945969-3-srinivas.pandruvada@linux.intel.com