// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2021 StarFive Technology Co., Ltd.
 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
 */

/dts-v1/;
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100.h>

/ {
	compatible = "starfive,jh7100";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		U74_0: cpu@0 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			tlb-split;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <1>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			tlb-split;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&U74_0>;
				};

				core1 {
					cpu = <&U74_1>;
				};
			};
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <15000>;

			thermal-sensors = <&sfctemp>;

			trips {
				cpu-alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu-crit {
					/* milliCelsius */
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	osc_sys: osc-sys {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "osc_sys";
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	osc_aud: osc-aud {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "osc_aud";
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	gmac_rmii_ref: gmac-rmii-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "gmac_rmii_ref";
		/* Should be overridden by the board when needed */
		clock-frequency = <0>;
	};

	gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "gmac_gr_mii_rxclk";
		/* Should be overridden by the board when needed */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		dma-noncoherent;
		ranges;

		clint: clint@2000000 {
			compatible = "starfive,jh7100-clint", "sifive,clint0";
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>;
		};

		ccache: cache-controller@2010000 {
			compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
			reg = <0x0 0x2010000 0x0 0x1000>;
			interrupts = <128>, <130>, <131>, <129>;
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <2048>;
			cache-size = <2097152>;
			cache-unified;
		};

		plic: interrupt-controller@c000000 {
			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
			reg = <0x0 0xc000000 0x0 0x4000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
			riscv,ndev = <133>;
		};

		sdio0: mmc@10000000 {
			compatible = "snps,dw-mshc";
			reg = <0x0 0x10000000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
				 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
			clock-names = "biu", "ciu";
			interrupts = <4>;
			data-addr = <0>;
			fifo-depth = <32>;
			fifo-watermark-aligned;
			status = "disabled";
		};

		sdio1: mmc@10010000 {
			compatible = "snps,dw-mshc";
			reg = <0x0 0x10010000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
				 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
			clock-names = "biu", "ciu";
			interrupts = <5>;
			data-addr = <0>;
			fifo-depth = <32>;
			fifo-watermark-aligned;
			status = "disabled";
		};

		gmac: ethernet@10020000 {
			compatible = "starfive,jh7100-dwmac", "snps,dwmac";
			reg = <0x0 0x10020000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
				 <&clkgen JH7100_CLK_GMAC_AHB>,
				 <&clkgen JH7100_CLK_GMAC_PTP_REF>,
				 <&clkgen JH7100_CLK_GMAC_TX_INV>,
				 <&clkgen JH7100_CLK_GMAC_GTX>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
			resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
			reset-names = "ahb";
			interrupts = <6>, <7>;
			interrupt-names = "macirq", "eth_wake_irq";
			max-frame-size = <9000>;
			snps,multicast-filter-bins = <32>;
			snps,perfect-filter-entries = <128>;
			starfive,syscon = <&sysmain 0x70 0>;
			rx-fifo-depth = <32768>;
			tx-fifo-depth = <16384>;
			snps,axi-config = <&stmmac_axi_setup>;
			snps,fixed-burst;
			snps,force_thresh_dma_mode;
			status = "disabled";

			stmmac_axi_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <16>;
				snps,rd_osr_lmt = <16>;
				snps,blen = <256 128 64 32 0 0 0>;
			};
		};

		clkgen: clock-controller@11800000 {
			compatible = "starfive,jh7100-clkgen";
			reg = <0x0 0x11800000 0x0 0x10000>;
			clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
			clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
			#clock-cells = <1>;
		};

		rstgen: reset-controller@11840000 {
			compatible = "starfive,jh7100-reset";
			reg = <0x0 0x11840000 0x0 0x10000>;
			#reset-cells = <1>;
		};

		sysmain: syscon@11850000 {
			compatible = "starfive,jh7100-sysmain", "syscon";
			reg = <0x0 0x11850000 0x0 0x10000>;
		};

		i2c0: i2c@118b0000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118b0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
				 <&clkgen JH7100_CLK_I2C0_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C0_APB>;
			interrupts = <96>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@118c0000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118c0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
				 <&clkgen JH7100_CLK_I2C1_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C1_APB>;
			interrupts = <97>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gpio: pinctrl@11910000 {
			compatible = "starfive,jh7100-pinctrl";
			reg = <0x0 0x11910000 0x0 0x10000>,
			      <0x0 0x11858000 0x0 0x1000>;
			reg-names = "gpio", "padctl";
			clocks = <&clkgen JH7100_CLK_GPIO_APB>;
			resets = <&rstgen JH7100_RSTN_GPIO_APB>;
			interrupts = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uart2: serial@12430000 {
			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
			reg = <0x0 0x12430000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART2_CORE>,
				 <&clkgen JH7100_CLK_UART2_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART2_APB>;
			interrupts = <72>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart3: serial@12440000 {
			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
			reg = <0x0 0x12440000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART3_CORE>,
				 <&clkgen JH7100_CLK_UART3_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART3_APB>;
			interrupts = <73>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		i2c2: i2c@12450000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12450000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
				 <&clkgen JH7100_CLK_I2C2_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C2_APB>;
			interrupts = <74>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@12460000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12460000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
				 <&clkgen JH7100_CLK_I2C3_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C3_APB>;
			interrupts = <75>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		watchdog@12480000 {
			compatible = "starfive,jh7100-wdt";
			reg = <0x0 0x12480000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
				 <&clkgen JH7100_CLK_WDT_CORE>;
			clock-names = "apb", "core";
			resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
				 <&rstgen JH7100_RSTN_WDT>;
		};

		pwm: pwm@12490000 {
			compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
			reg = <0x0 0x12490000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_PWM_APB>;
			resets = <&rstgen JH7100_RSTN_PWM_APB>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		sfctemp: temperature-sensor@124a0000 {
			compatible = "starfive,jh7100-temp";
			reg = <0x0 0x124a0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
				 <&clkgen JH7100_CLK_TEMP_APB>;
			clock-names = "sense", "bus";
			resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
				 <&rstgen JH7100_RSTN_TEMP_APB>;
			reset-names = "sense", "bus";
			#thermal-sensor-cells = <0>;
		};
	};
};