// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc1 = &sdhc1;
		mmc2 = &sdhc2;
	};

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "sleep_clk";
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				cpu6_map: core2 {
					cpu = <&CPU6>;
				};

				cpu7_map: core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8994", "qcom,scm";
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0x80000000 0 0>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "hvc";
	};

	rpm: remoteproc {
		compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc";

		smd-edge {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			mboxes = <&apcs 0>;
			qcom,smd-edge = <15>;
			qcom,remote-pid = <6>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8994", "qcom,smd-rpm";
				qcom,smd-channels = "rpm_requests";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
					#clock-cells = <1>;
				};

				rpmpd: power-controller {
					compatible = "qcom,msm8994-rpmpd";
					#power-domain-cells = <1>;
					operating-points-v2 = <&rpmpd_opp_table>;

					rpmpd_opp_table: opp-table {
						compatible = "operating-points-v2";

						rpmpd_opp_ret: opp1 {
							opp-level = <1>;
						};
						rpmpd_opp_svs_krait: opp2 {
							opp-level = <2>;
						};
						rpmpd_opp_svs_soc: opp3 {
							opp-level = <3>;
						};
						rpmpd_opp_nom: opp4 {
							opp-level = <4>;
						};
						rpmpd_opp_turbo: opp5 {
							opp-level = <5>;
						};
						rpmpd_opp_super_turbo: opp6 {
							opp-level = <6>;
						};
					};
				};
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dfps_data_mem: dfps-data@3400000 {
			reg = <0 0x03400000 0 0x1000>;
			no-map;
		};

		cont_splash_mem: memory@3401000 {
			reg = <0 0x03401000 0 0x2200000>;
			no-map;
		};

		smem_mem: smem@6a00000 {
			reg = <0 0x06a00000 0 0x200000>;
			no-map;
		};

		mpss_mem: memory@7000000 {
			reg = <0 0x07000000 0 0x5a00000>;
			no-map;
		};

		peripheral_region: memory@ca00000 {
			reg = <0 0x0ca00000 0 0x1f00000>;
			no-map;
		};

		rmtfs_mem: memory@c6400000 {
			compatible = "qcom,rmtfs-mem";
			reg = <0 0xc6400000 0 0x180000>;
			no-map;

			qcom,client-id = <1>;
		};

		mba_mem: memory@c6700000 {
			reg = <0 0xc6700000 0 0x100000>;
			no-map;
		};

		audio_mem: memory@c7000000 {
			reg = <0 0xc7000000 0 0x800000>;
			no-map;
		};

		adsp_mem: memory@c9400000 {
			reg = <0 0xc9400000 0 0x3f00000>;
			no-map;
		};

		res_hyp_mem: reserved@6c00000 {
			reg = <0 0x06c00000 0 0x400000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-lpass {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: mailbox@f900d000 {
			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
			reg = <0xf900d000 0x2000>;
			#mbox-cells = <1>;
		};

		watchdog@f9017000 {
			compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
			reg = <0xf9017000 0x1000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		usb3: usb@f92f8800 {
			compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
			reg = <0xf92f8800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
			clock-names = "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;

			power-domains = <&gcc USB30_GDSC>;
			qcom,select-utmi-as-pipe-clk;

			usb@f9200000 {
				compatible = "snps,dwc3";
				reg = <0xf9200000 0xcc00>;
				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				maximum-speed = "high-speed";
				dr_mode = "peripheral";
			};
		};

		sdhc1: mmc@f9824900 {
			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
			reg-names = "hc", "core";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;

			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

		sdhc2: mmc@f98a4900 {
			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc", "core";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
			pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

			cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
			bus-width = <4>;
			status = "disabled";
		};

		blsp1_dma: dma-controller@f9904000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0xf9904000 0x19000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <24>;
			qcom,num-ees = <4>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "iface";
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart2_default>;
			pinctrl-1 = <&blsp1_uart2_sleep>;
			status = "disabled";
		};

		blsp1_i2c1: i2c@f9923000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9923000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c1_default>;
			pinctrl-1 = <&i2c1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_spi1: spi@f9923000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0xf9923000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_spi1_default>;
			pinctrl-1 = <&blsp1_spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c2: i2c@f9924000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9924000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* I2C3 doesn't exist */

		blsp1_i2c4: i2c@f9926000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9926000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c5: i2c@f9927000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9927000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c5_default>;
			pinctrl-1 = <&i2c5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp1_i2c6: i2c@f9928000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9928000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_dma: dma-controller@f9944000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0xf9944000 0x19000>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <24>;
			qcom,num-ees = <4>;
		};

		blsp2_uart2: serial@f995e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf995e000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "iface";
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
					<&gcc GCC_BLSP2_AHB_CLK>;
			dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_uart2_default>;
			pinctrl-1 = <&blsp2_uart2_sleep>;
			status = "disabled";
		};

		blsp2_i2c1: i2c@f9963000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9963000 0x500>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <400000>;
			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c7_default>;
			pinctrl-1 = <&i2c7_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_spi4: spi@f9966000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0xf9966000 0x500>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_spi10_default>;
			pinctrl-1 = <&blsp2_spi10_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_i2c5: i2c@f9967000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9967000 0x500>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			clock-frequency = <355000>;
			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
			dma-names = "tx", "rx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c11_default>;
			pinctrl-1 = <&i2c11_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8994";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x2000>;

			clock-names = "xo", "sleep";
			clocks = <&xo_board>, <&sleep_clk>;
		};

		rpm_msg_ram: sram@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			reg-names = "core", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		tcsr_mutex: hwlock@fd484000 {
			compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
			reg = <0xfd484000 0x1000>;
			#hwlock-cells = <1>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,msm8994-pinctrl";
			reg = <0xfd510000 0x4000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&tlmm 0 0 146>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			blsp1_uart2_default: blsp1-uart2-default-state {
				pins = "gpio4", "gpio5";
				function = "blsp_uart2";
				drive-strength = <16>;
				bias-disable;
			};

			blsp1_uart2_sleep: blsp1-uart2-sleep-state {
				pins = "gpio4", "gpio5";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-down;
			};

			blsp2_uart2_default: blsp2-uart2-default-state {
				pins = "gpio45", "gpio46", "gpio47", "gpio48";
				function = "blsp_uart8";
				drive-strength = <16>;
				bias-disable;
			};

			blsp2_uart2_sleep: blsp2-uart2-sleep-state {
				pins = "gpio45", "gpio46", "gpio47", "gpio48";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c1_default: i2c1-default-state {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-disable;
			};

			i2c1_sleep: i2c1-sleep-state {
				pins = "gpio2", "gpio3";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c2_default: i2c2-default-state {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-disable;
			};

			i2c2_sleep: i2c2-sleep-state {
				pins = "gpio6", "gpio7";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c4_default: i2c4-default-state {
				pins = "gpio19", "gpio20";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-disable;
			};

			i2c4_sleep: i2c4-sleep-state {
				pins = "gpio19", "gpio20";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-down;
			};

			i2c5_default: i2c5-default-state {
				pins = "gpio23", "gpio24";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-disable;
			};

			i2c5_sleep: i2c5-sleep-state {
				pins = "gpio23", "gpio24";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c6_default: i2c6-default-state {
				pins = "gpio28", "gpio27";
				function = "blsp_i2c6";
				drive-strength = <2>;
				bias-disable;
			};

			i2c6_sleep: i2c6-sleep-state {
				pins = "gpio28", "gpio27";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c7_default: i2c7-default-state {
				pins = "gpio44", "gpio43";
				function = "blsp_i2c7";
				drive-strength = <2>;
				bias-disable;
			};

			i2c7_sleep: i2c7-sleep-state {
				pins = "gpio44", "gpio43";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			blsp2_spi10_default: blsp2-spi10-default-state {
				default-pins {
					pins = "gpio53", "gpio54", "gpio55";
					function = "blsp_spi10";
					drive-strength = <10>;
					bias-pull-down;
				};

				cs-pins {
					pins = "gpio67";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};

			blsp2_spi10_sleep: blsp2-spi10-sleep-state {
				pins = "gpio53", "gpio54", "gpio55";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			i2c11_default: i2c11-default-state {
				pins = "gpio83", "gpio84";
				function = "blsp_i2c11";
				drive-strength = <2>;
				bias-disable;
			};

			i2c11_sleep: i2c11-sleep-state {
				pins = "gpio83", "gpio84";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_spi1_default: blsp1-spi1-default-state {
				default-pins {
					pins = "gpio0", "gpio1", "gpio3";
					function = "blsp_spi1";
					drive-strength = <10>;
					bias-pull-down;
				};

				cs-pins {
					pins = "gpio8";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};

			blsp1_spi1_sleep: blsp1-spi1-sleep-state {
				pins = "gpio0", "gpio1", "gpio3";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			sdc1_clk_on: clk-on-state {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <16>;
			};

			sdc1_clk_off: clk-off-state {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <2>;
			};

			sdc1_cmd_on: cmd-on-state {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <8>;
			};

			sdc1_cmd_off: cmd-off-state {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <2>;
			};

			sdc1_data_on: data-on-state {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <8>;
			};

			sdc1_data_off: data-off-state {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <2>;
			};

			sdc1_rclk_on: rclk-on-state {
				pins = "sdc1_rclk";
				bias-pull-down;
			};

			sdc1_rclk_off: rclk-off-state {
				pins = "sdc1_rclk";
				bias-pull-down;
			};

			sdc2_clk_on: sdc2-clk-on-state {
				pins = "sdc2_clk";
				bias-disable;
				drive-strength = <10>;
			};

			sdc2_clk_off: sdc2-clk-off-state {
				pins = "sdc2_clk";
				bias-disable;
				drive-strength = <2>;
			};

			sdc2_cmd_on: sdc2-cmd-on-state {
				pins = "sdc2_cmd";
				bias-pull-up;
				drive-strength = <10>;
			};

			sdc2_cmd_off: sdc2-cmd-off-state {
				pins = "sdc2_cmd";
				bias-pull-up;
				drive-strength = <2>;
			};

			sdc2_data_on: sdc2-data-on-state {
				pins = "sdc2_data";
				bias-pull-up;
				drive-strength = <10>;
			};

			sdc2_data_off: sdc2-data-off-state {
				pins = "sdc2_data";
				bias-pull-up;
				drive-strength = <2>;
			};
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8994";
			reg = <0xfd8c0000 0x5200>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;

			clock-names = "xo",
				      "gpll0",
				      "mmssnoc_ahb",
				      "oxili_gfx3d_clk_src",
				      "dsi0pll",
				      "dsi0pllbyte",
				      "dsi1pll",
				      "dsi1pllbyte",
				      "hdmipll";
			clocks = <&xo_board>,
				 <&gcc GPLL0_OUT_MMSSCC>,
				 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
				 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>;

			assigned-clocks = <&mmcc MMPLL0_PLL>,
					  <&mmcc MMPLL1_PLL>,
					  <&mmcc MMPLL3_PLL>,
					  <&mmcc MMPLL4_PLL>,
					  <&mmcc MMPLL5_PLL>;
			assigned-clock-rates = <800000000>,
					       <1167000000>,
					       <1020000000>,
					       <960000000>,
					       <600000000>;
		};

		ocmem: sram@fdd00000 {
			compatible = "qcom,msm8974-ocmem";
			reg = <0xfdd00000 0x2000>,
			      <0xfec00000 0x200000>;
			reg-names = "ctrl", "mem";
			ranges = <0 0xfec00000 0x200000>;
			clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
				 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
			clock-names = "core", "iface";

			#address-cells = <1>;
			#size-cells = <1>;

			gmu_sram: gmu-sram@0 {
				reg = <0x0 0x180000>;
			};
		};
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	vph_pwr: vph-pwr-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vph_pwr";

		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;

		regulator-always-on;
	};
};