)]}'
{
  "commit": "4bfe6b6876a036d26a960320f1ab0bbd752c19bf",
  "tree": "a148753cbfea2eee98989d253b9ca572a7873023",
  "parents": [
    "ba86bf8bfc1add5f515db8cf1d6042bb9396a299"
  ],
  "author": {
    "name": "Zhenyu Wang",
    "email": "zhenyuw@linux.intel.com",
    "time": "Mon Nov 02 07:52:29 2009 +0000"
  },
  "committer": {
    "name": "Eric Anholt",
    "email": "eric@anholt.net",
    "time": "Thu Nov 05 14:00:32 2009 -0800"
  },
  "message": "drm/i915: Fix and cleanup DPLL calculation for Ironlake\n\nWhen the ideal error range can\u0027t be reached, this will safely use\na most closed one. Clean up some dumb codes in DPLL function too.\n\nThis fixes DPLL clock issue against one monitor at 1680x1050@60hz.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nSigned-off-by: Eric Anholt \u003ceric@anholt.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3ba6546b7c7f6875938ac8bc9b7345a4ca3ac200",
      "old_mode": 33188,
      "old_path": "drivers/gpu/drm/i915/intel_display.c",
      "new_id": "099f420de57a2350d1da373cd7059b8305776e0a",
      "new_mode": 33188,
      "new_path": "drivers/gpu/drm/i915/intel_display.c"
    }
  ]
}