tree 3f65586a10e872c08a2978c026579ea6fe432c64
parent 2162fed49fa86cb3b5c296565837e674c53cc7ae
author Sandipan Das <sandipan@linux.vnet.ibm.com> 1527145006 +0530
committer Daniel Borkmann <daniel@iogearbox.net> 1527146448 +0200

bpf: powerpc64: pad function address loads with NOPs

For multi-function programs, loading the address of a callee
function to a register requires emitting instructions whose
count varies from one to five depending on the nature of the
address.

Since we come to know of the callee's address only before the
extra pass, the number of instructions required to load this
address may vary from what was previously generated. This can
make the JITed image grow or shrink.

To avoid this, we should generate a constant five-instruction
when loading function addresses by padding the optimized load
sequence with NOPs.

Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>