)]}'
{
  "commit": "4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab",
  "tree": "e3a2e86b00b408c281c6d1304228a5c4c9a6111b",
  "parents": [
    "a197f3c7d48c0c1f45076ea47533a76ba9b1a959"
  ],
  "author": {
    "name": "Andy Shevchenko",
    "email": "andriy.shevchenko@linux.intel.com",
    "time": "Fri Mar 18 14:26:32 2016 +0200"
  },
  "committer": {
    "name": "Vinod Koul",
    "email": "vinod.koul@intel.com",
    "time": "Mon Apr 04 09:41:43 2016 -0700"
  },
  "message": "dmaengine: hsu: correct use of channel status register\n\nThere is a typo in documentation regarding to descriptor empty bit (DESCE)\nwhich is set to 1 when descriptor is empty. Thus, status register at the end of\na transfer usually returns all DESCE bits set and thus it will never be zero.\n\nMoreover, there are 2 bits (CDESC) that encode current descriptor, on which\ninterrupt has been asserted. In case when we have few descriptors programmed we\nmight have non-zero value.\n\nRemove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when\nreading it.\n\nFixes: 2b49e0c56741 (\"dmaengine: append hsu DMA driver\")\nCc: stable@vger.kernel.org\nSigned-off-by: Andy Shevchenko \u003candriy.shevchenko@linux.intel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b3b212146620f7e439cadb5b373ef293d8a5a0d5",
      "old_mode": 33188,
      "old_path": "drivers/dma/hsu/hsu.c",
      "new_id": "ee510515ce187af75d3ba873b65d5de26cc3acb4",
      "new_mode": 33188,
      "new_path": "drivers/dma/hsu/hsu.c"
    },
    {
      "type": "modify",
      "old_id": "578a8ee8cd054429b3e3fd6da2341b49020721cc",
      "old_mode": 33188,
      "old_path": "drivers/dma/hsu/hsu.h",
      "new_id": "6b070c22b1dfc2bca1dc04ca12218de17d1f0d70",
      "new_mode": 33188,
      "new_path": "drivers/dma/hsu/hsu.h"
    }
  ]
}