| commit | 503275bf371fbab01a14f2e9fd1ac7aa20c81645 | [log] [tgz] |
|---|---|---|
| author | Yijing Wang <wangyijing@huawei.com> | Mon Sep 09 21:13:04 2013 +0800 |
| committer | Bjorn Helgaas <bhelgaas@google.com> | Tue Sep 24 12:10:04 2013 -0600 |
| tree | 295daeca82f990fce2400440234526af6b1bb264 | |
| parent | f1c66c4678ad223bda0dcd261e4048f009234f85 [diff] |
tile/PCI: use cached pci_dev->pcie_mpss to simplify code The PCI core caches the "PCIe Max Payload Size Supported" in pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>