| commit | 503fa23614dc95f96af883a8e2e873d5c6cd53d8 | [log] [tgz] |
|---|---|---|
| author | Maciej W. Rozycki <macro@orcam.me.uk> | Sat Sep 17 13:03:09 2022 +0100 |
| committer | Bjorn Helgaas <bhelgaas@google.com> | Fri Nov 04 10:38:11 2022 -0500 |
| tree | db370093acfd139e5bdb9cdaa188bffb936ad8d7 | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 [diff] |
PCI: Access Link 2 registers only for devices with Links PCIe r2.0, sec 7.8 added Link Capabilities/Status/Control 2 registers to the PCIe Capability with Capability Version 2. Previously we assumed these registers were implemented for all PCIe Capabilities of version 2 or greater, but in fact they are only implemented for devices with Links. Update pcie_capability_reg_implemented() to check whether the device has a Link. [bhelgaas: commit log, squash export] Link: https://lore.kernel.org/r/alpine.DEB.2.21.2209100057070.2275@angie.orcam.me.uk Link: https://lore.kernel.org/r/alpine.DEB.2.21.2209100057300.2275@angie.orcam.me.uk Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>