tree 0f2515769d1ceecc8f55380aff228c54929275e1
parent 4b3ea2e04d2b8b37c5bc472f710d706b42e4fa06
author Catalin Marinas <catalin.marinas@arm.com> 1366811222 +0100
committer Catalin Marinas <catalin.marinas@arm.com> 1366908348 +0100

arm64: Execute DSB during thread switching for TLB/cache maintenance

The DSB following TLB or cache maintenance ops must be run on the same
CPU. With kernel preemption enabled or for user-space cache maintenance
this may not be the case. This patch adds an explicit DSB in the
__switch_to() function.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>