# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape PCIe Root Complex(RC) controller

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description:
  This PCIe RC controller is based on the Synopsys DesignWare PCIe IP

  This controller derives its clocks from the Reset Configuration Word (RCW)
  which is used to describe the PLL settings at the time of chip-reset.

  Also as per the available Reference Manuals, there is no specific 'version'
  register available in the Freescale PCIe controller register set,
  which can allow determining the underlying DesignWare PCIe controller version
  information.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,ls1012a-pcie
          - fsl,ls1021a-pcie
          - fsl,ls1028a-pcie
          - fsl,ls1043a-pcie
          - fsl,ls1046a-pcie
          - fsl,ls1088a-pcie
          - fsl,ls2080a-pcie
          - fsl,ls2085a-pcie
          - fsl,ls2088a-pcie
      - items:
          - const: fsl,lx2160ar2-pcie
          - const: fsl,ls2088a-pcie
  reg:
    maxItems: 2

  reg-names:
    items:
      - const: regs
      - const: config

  fsl,pcie-scfg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: A phandle to the SCFG device node. The second entry is the
      physical PCIe controller index starting from '0'. This is used to get
      SCFG PEXN registers.
    items:
      items:
        - description: A phandle to the SCFG device node
        - description: PCIe controller index starting from '0'
    maxItems: 1

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: If the PEX_LUT and PF register block is in big-endian, specify
      this property.

  dma-coherent: true

  msi-parent: true

  iommu-map: true

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    minItems: 1
    maxItems: 2

  num-viewport:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of outbound view ports configured in hardware. It's the same as
      the number of outbound AT windows.
    maximum: 256

required:
  - compatible
  - reg
  - reg-names
  - "#address-cells"
  - "#size-cells"
  - device_type
  - bus-range
  - ranges
  - interrupts
  - interrupt-names
  - "#interrupt-cells"
  - interrupt-map-mask
  - interrupt-map

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

  - if:
      properties:
        compatible:
          enum:
            - fsl,ls1028a-pcie
            - fsl,ls1046a-pcie
            - fsl,ls1043a-pcie
            - fsl,ls1012a-pcie
    then:
      properties:
        interrupts:
          maxItems: 2
        interrupt-names:
          items:
            - const: pme
            - const: aer

  - if:
      properties:
        compatible:
          enum:
            - fsl,ls2080a-pcie
            - fsl,ls2085a-pcie
            - fsl,ls2088a-pcie
    then:
      properties:
        interrupts:
          maxItems: 1
        interrupt-names:
          items:
            - const: intr

  - if:
      properties:
        compatible:
          enum:
            - fsl,ls1088a-pcie
    then:
      properties:
        interrupts:
          maxItems: 1
        interrupt-names:
          items:
            - const: aer

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie@3400000 {
        compatible = "fsl,ls1088a-pcie";
        reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
            <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
        reg-names = "regs", "config";
        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
        interrupt-names = "aer";
        #address-cells = <3>;
        #size-cells = <2>;
        dma-coherent;
        device_type = "pci";
        bus-range = <0x0 0xff>;
        ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
                 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
        msi-parent = <&its>;
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 7>;
        interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
                        <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
                        <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
                        <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
        iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
      };
    };
...