tree e61af1fcb70735394b1269070d5a763c52cf604c
parent 11f8b2d65ca9029591c8df26bb6bd063c312b7fe
author Peter Zijlstra (Intel) <peterz@infradead.org> 1551820997 +0100
committer Thomas Gleixner <tglx@linutronix.de> 1551860741 +0100

x86: Add TSX Force Abort CPUID/MSR

Skylake systems will receive a microcode update to address a TSX
errata. This microcode will (by default) clobber PMC3 when TSX
instructions are (speculatively or not) executed.

It also provides an MSR to cause all TSX transaction to abort and
preserve PMC3.

Add the CPUID enumeration and MSR definition.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>