| /* SPDX-License-Identifier: GPL-2.0+ |
| * Microchip Sparx5 Switch driver |
| * |
| * Copyright (c) 2021 Microchip Technology Inc. |
| */ |
| |
| /* This file is autogenerated by cml-utils 2021-05-06 13:06:37 +0200. |
| * Commit ID: 9ae4ec441e25e4b9003f4e514df5cb12a36b84d3 |
| */ |
| |
| #ifndef _SPARX5_MAIN_REGS_H_ |
| #define _SPARX5_MAIN_REGS_H_ |
| |
| #include <linux/bitfield.h> |
| #include <linux/types.h> |
| #include <linux/bug.h> |
| |
| enum sparx5_target { |
| TARGET_ANA_AC = 1, |
| TARGET_ANA_ACL = 2, |
| TARGET_ANA_AC_POL = 4, |
| TARGET_ANA_CL = 6, |
| TARGET_ANA_L2 = 7, |
| TARGET_ANA_L3 = 8, |
| TARGET_ASM = 9, |
| TARGET_CLKGEN = 11, |
| TARGET_CPU = 12, |
| TARGET_DEV10G = 17, |
| TARGET_DEV25G = 29, |
| TARGET_DEV2G5 = 37, |
| TARGET_DEV5G = 102, |
| TARGET_DSM = 115, |
| TARGET_EACL = 116, |
| TARGET_FDMA = 117, |
| TARGET_GCB = 118, |
| TARGET_HSCH = 119, |
| TARGET_LRN = 122, |
| TARGET_PCEP = 129, |
| TARGET_PCS10G_BR = 132, |
| TARGET_PCS25G_BR = 144, |
| TARGET_PCS5G_BR = 160, |
| TARGET_PORT_CONF = 173, |
| TARGET_QFWD = 175, |
| TARGET_QRES = 176, |
| TARGET_QS = 177, |
| TARGET_QSYS = 178, |
| TARGET_REW = 179, |
| TARGET_VCAP_SUPER = 326, |
| TARGET_VOP = 327, |
| TARGET_XQS = 331, |
| NUM_TARGETS = 332 |
| }; |
| |
| #define __REG(...) __VA_ARGS__ |
| |
| /* ANA_AC:RAM_CTRL:RAM_INIT */ |
| #define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) |
| |
| #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) |
| #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ |
| FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) |
| #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ |
| FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) |
| |
| #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) |
| #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ |
| FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) |
| #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ |
| FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) |
| |
| /* ANA_AC:PS_COMMON:OWN_UPSID */ |
| #define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) |
| |
| #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) |
| #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ |
| FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) |
| #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ |
| FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) |
| |
| /* ANA_AC:SRC:SRC_CFG */ |
| #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) |
| |
| /* ANA_AC:SRC:SRC_CFG1 */ |
| #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) |
| |
| /* ANA_AC:SRC:SRC_CFG2 */ |
| #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) |
| |
| #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) |
| #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ |
| FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) |
| #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ |
| FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) |
| |
| /* ANA_AC:PGID:PGID_CFG */ |
| #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) |
| |
| /* ANA_AC:PGID:PGID_CFG1 */ |
| #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) |
| |
| /* ANA_AC:PGID:PGID_CFG2 */ |
| #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) |
| |
| #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) |
| #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ |
| FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) |
| #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ |
| FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) |
| |
| /* ANA_AC:PGID:PGID_MISC_CFG */ |
| #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) |
| |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ |
| FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ |
| FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) |
| |
| #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) |
| #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) |
| #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) |
| |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) |
| #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) |
| |
| /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ |
| #define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) |
| |
| #define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) |
| #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ |
| FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) |
| #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ |
| FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) |
| |
| /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ |
| #define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) |
| |
| #define ANA_AC_STAT_RESET_RESET BIT(0) |
| #define ANA_AC_STAT_RESET_RESET_SET(x)\ |
| FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) |
| #define ANA_AC_STAT_RESET_RESET_GET(x)\ |
| FIELD_GET(ANA_AC_STAT_RESET_RESET, x) |
| |
| /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ |
| #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4) |
| |
| #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) |
| #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ |
| FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) |
| #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ |
| FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) |
| |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ |
| FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ |
| FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) |
| |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ |
| FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) |
| #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ |
| FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) |
| |
| /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ |
| #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4) |
| |
| /* ANA_ACL:COMMON:OWN_UPSID */ |
| #define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) |
| |
| #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) |
| #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ |
| FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) |
| #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ |
| FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) |
| |
| /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ |
| #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) |
| |
| #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) |
| #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) |
| #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ |
| FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) |
| |
| /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ |
| #define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) |
| |
| #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ |
| FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) |
| |
| #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ |
| FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) |
| |
| #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) |
| |
| #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) |
| #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) |
| |
| /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ |
| #define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) |
| |
| #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) |
| #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) |
| #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ |
| FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) |
| |
| #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) |
| #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) |
| #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ |
| FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) |
| |
| #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) |
| #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) |
| #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) |
| |
| #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) |
| #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ |
| FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) |
| #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ |
| FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) |
| |
| /* ANA_CL:PORT:FILTER_CTRL */ |
| #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) |
| |
| #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) |
| #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) |
| #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) |
| |
| #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) |
| #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) |
| #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) |
| |
| #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) |
| #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ |
| FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) |
| #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ |
| FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) |
| |
| /* ANA_CL:PORT:VLAN_FILTER_CTRL */ |
| #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) |
| #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) |
| #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) |
| #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) |
| |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) |
| #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) |
| |
| /* ANA_CL:PORT:ETAG_FILTER_CTRL */ |
| #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) |
| |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ |
| FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ |
| FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) |
| |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) |
| #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) |
| |
| /* ANA_CL:PORT:VLAN_CTRL */ |
| #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) |
| #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) |
| |
| #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) |
| #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) |
| #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) |
| |
| #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) |
| #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) |
| #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) |
| |
| #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) |
| #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) |
| #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) |
| |
| #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) |
| #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) |
| #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) |
| #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) |
| #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) |
| #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) |
| #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) |
| #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) |
| #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) |
| |
| #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) |
| #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) |
| #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) |
| |
| /* ANA_CL:PORT:VLAN_CTRL_2 */ |
| #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) |
| |
| #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) |
| #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ |
| FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) |
| #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ |
| FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) |
| |
| /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ |
| #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) |
| |
| /* ANA_CL:COMMON:OWN_UPSID */ |
| #define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) |
| |
| #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) |
| #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ |
| FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) |
| #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ |
| FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) |
| |
| /* ANA_L2:COMMON:AUTO_LRN_CFG */ |
| #define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) |
| |
| /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ |
| #define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) |
| |
| /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ |
| #define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) |
| |
| #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) |
| #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ |
| FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) |
| #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ |
| FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) |
| |
| /* ANA_L2:COMMON:OWN_UPSID */ |
| #define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) |
| |
| #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) |
| #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ |
| FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) |
| #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ |
| FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) |
| |
| /* ANA_L3:COMMON:VLAN_CTRL */ |
| #define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) |
| |
| #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) |
| #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) |
| #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) |
| |
| /* ANA_L3:VLAN:VLAN_CFG */ |
| #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) |
| #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) |
| #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) |
| #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) |
| #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) |
| #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) |
| #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) |
| #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) |
| #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) |
| #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) |
| #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) |
| #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) |
| #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) |
| #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) |
| #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) |
| #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) |
| #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) |
| |
| #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) |
| #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) |
| #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) |
| |
| /* ANA_L3:VLAN:VLAN_MASK_CFG */ |
| #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) |
| |
| /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ |
| #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) |
| |
| /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ |
| #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) |
| |
| #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) |
| #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ |
| FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) |
| #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ |
| FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) |
| |
| /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ |
| #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ |
| #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ |
| #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ |
| #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ |
| #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ |
| #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_UC_CNT */ |
| #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_MC_CNT */ |
| #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_BC_CNT */ |
| #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ |
| #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ |
| #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ |
| #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ |
| #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ |
| #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ |
| #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ |
| #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ |
| #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ |
| #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ |
| #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ |
| #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ |
| #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ |
| #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ |
| #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ |
| #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ |
| #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ |
| #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ |
| #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_UC_CNT */ |
| #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_MC_CNT */ |
| #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_BC_CNT */ |
| #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ |
| #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ |
| #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ |
| #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ |
| #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ |
| #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ |
| #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ |
| #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ |
| #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ |
| #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ |
| #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ |
| #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ |
| #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ |
| #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ |
| #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ |
| #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ |
| #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ |
| #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ |
| #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ |
| #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ |
| #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ |
| #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ |
| #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ |
| #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ |
| #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ |
| #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ |
| #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ |
| #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ |
| #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ |
| #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ |
| #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ |
| #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ |
| #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ |
| #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ |
| #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ |
| #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ |
| #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ |
| #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ |
| #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ |
| #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ |
| #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ |
| #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ |
| #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ |
| #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ |
| #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ |
| #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ |
| #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ |
| #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ |
| #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ |
| #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ |
| #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ |
| #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ |
| #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ |
| #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ |
| #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ |
| #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ |
| #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ |
| #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ |
| #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ |
| #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4) |
| |
| /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ |
| #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4) |
| |
| #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) |
| #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ |
| #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4) |
| |
| #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) |
| #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ |
| #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4) |
| |
| #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) |
| #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ |
| #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4) |
| |
| #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) |
| #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ |
| #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4) |
| |
| #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) |
| #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ |
| #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4) |
| |
| #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) |
| #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ |
| #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4) |
| |
| #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) |
| #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ |
| #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4) |
| |
| #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) |
| #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) |
| #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) |
| |
| /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ |
| #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4) |
| |
| /* ASM:CFG:STAT_CFG */ |
| #define ASM_STAT_CFG __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) |
| |
| #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) |
| #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ |
| FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) |
| #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ |
| FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) |
| |
| /* ASM:CFG:PORT_CFG */ |
| #define ASM_PORT_CFG(r) __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) |
| |
| #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) |
| #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) |
| #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) |
| |
| #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) |
| #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) |
| #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) |
| |
| #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) |
| #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) |
| #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) |
| |
| #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) |
| #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) |
| #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) |
| |
| #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) |
| #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) |
| #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) |
| |
| #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) |
| #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) |
| #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) |
| |
| #define ASM_PORT_CFG_PAD_ENA BIT(6) |
| #define ASM_PORT_CFG_PAD_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) |
| #define ASM_PORT_CFG_PAD_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) |
| |
| #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) |
| #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) |
| #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) |
| |
| #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) |
| #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) |
| #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) |
| |
| #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) |
| #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) |
| #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) |
| |
| #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) |
| #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ |
| FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) |
| #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ |
| FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) |
| |
| /* ASM:RAM_CTRL:RAM_INIT */ |
| #define ASM_RAM_INIT __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) |
| |
| #define ASM_RAM_INIT_RAM_INIT BIT(1) |
| #define ASM_RAM_INIT_RAM_INIT_SET(x)\ |
| FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) |
| #define ASM_RAM_INIT_RAM_INIT_GET(x)\ |
| FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) |
| |
| #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) |
| #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ |
| FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) |
| #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ |
| FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) |
| |
| /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) |
| |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ |
| FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) |
| #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ |
| FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) |
| |
| /* CPU:CPU_REGS:PROC_CTRL */ |
| #define CPU_PROC_CTRL __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) |
| |
| #define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) |
| #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) |
| #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) |
| |
| #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) |
| #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) |
| #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) |
| |
| #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) |
| #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) |
| #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) |
| |
| #define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) |
| #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) |
| #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) |
| |
| #define CPU_PROC_CTRL_VINITHI BIT(8) |
| #define CPU_PROC_CTRL_VINITHI_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) |
| #define CPU_PROC_CTRL_VINITHI_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_VINITHI, x) |
| |
| #define CPU_PROC_CTRL_CFGTE BIT(7) |
| #define CPU_PROC_CTRL_CFGTE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) |
| #define CPU_PROC_CTRL_CFGTE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_CFGTE, x) |
| |
| #define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) |
| #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) |
| #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) |
| |
| #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) |
| #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) |
| #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) |
| |
| #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) |
| #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) |
| #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) |
| |
| #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) |
| #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) |
| #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) |
| |
| #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) |
| #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) |
| #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) |
| |
| #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) |
| #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) |
| #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) |
| |
| #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) |
| #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ |
| FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) |
| #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ |
| FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ |
| #define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4) |
| |
| #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) |
| #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) |
| #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) |
| |
| #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) |
| #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) |
| #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ |
| #define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4) |
| |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ |
| FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ |
| FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ |
| #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4) |
| |
| #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) |
| #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) |
| #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ |
| FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ |
| #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4) |
| |
| #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) |
| #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) |
| #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) |
| |
| #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) |
| #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) |
| #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ |
| #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) |
| #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) |
| #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| |
| #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) |
| #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ |
| #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4) |
| |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) |
| |
| #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) |
| |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) |
| |
| #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) |
| |
| #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ |
| FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) |
| #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ |
| FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) |
| |
| /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ |
| #define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4) |
| |
| #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) |
| #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| |
| #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) |
| #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| |
| #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) |
| #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| |
| #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) |
| #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| |
| #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) |
| #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) |
| #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) |
| |
| #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) |
| #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) |
| #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) |
| |
| #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) |
| #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) |
| #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) |
| |
| #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) |
| #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) |
| #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) |
| |
| #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) |
| #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ |
| FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) |
| #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ |
| FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) |
| |
| /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ |
| #define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4) |
| |
| #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) |
| #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ |
| FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) |
| #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ |
| FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ |
| #define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) |
| |
| #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) |
| #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) |
| #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) |
| |
| #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) |
| #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) |
| #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ |
| #define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) |
| |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ |
| FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ |
| FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ |
| #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) |
| #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) |
| #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| |
| #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) |
| #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| |
| /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ |
| #define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) |
| |
| #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) |
| #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| |
| #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) |
| #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| |
| #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) |
| #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| |
| #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) |
| #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| |
| #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) |
| #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) |
| #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) |
| |
| #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) |
| #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) |
| #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) |
| |
| #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) |
| #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) |
| #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) |
| |
| #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) |
| #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) |
| #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) |
| |
| #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) |
| #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ |
| FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) |
| #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ |
| FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) |
| |
| /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ |
| #define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) |
| |
| #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) |
| #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) |
| #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ |
| FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) |
| |
| /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ |
| #define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) |
| |
| #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) |
| #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ |
| FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) |
| #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ |
| FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) |
| |
| #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) |
| #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ |
| FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) |
| #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ |
| FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) |
| |
| #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) |
| #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ |
| FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) |
| #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ |
| FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) |
| |
| /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ |
| #define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4) |
| |
| #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) |
| #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) |
| #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) |
| #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) |
| #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) |
| #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) |
| #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) |
| |
| #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) |
| #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ |
| FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) |
| #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ |
| FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ |
| #define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4) |
| |
| #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) |
| #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) |
| #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) |
| |
| #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) |
| #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) |
| #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ |
| #define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4) |
| |
| #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) |
| #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) |
| #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) |
| |
| #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) |
| #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) |
| #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) |
| |
| #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) |
| #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) |
| #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ |
| #define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4) |
| |
| #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) |
| #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) |
| #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ |
| #define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4) |
| |
| #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) |
| #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) |
| #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) |
| |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) |
| |
| #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) |
| #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) |
| #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) |
| |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) |
| #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ |
| #define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4) |
| |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) |
| |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) |
| #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ |
| #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4) |
| |
| #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) |
| #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) |
| #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ |
| #define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4) |
| |
| #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) |
| #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) |
| #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) |
| |
| #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) |
| #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) |
| #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) |
| |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) |
| |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) |
| #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) |
| |
| /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ |
| #define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4) |
| |
| #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) |
| #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) |
| #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) |
| |
| #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) |
| #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) |
| #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) |
| |
| #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) |
| #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) |
| #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) |
| |
| #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) |
| #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) |
| #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) |
| |
| #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) |
| #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ |
| FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) |
| #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ |
| FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ |
| #define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) |
| #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) |
| #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) |
| |
| #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) |
| #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) |
| #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) |
| |
| #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) |
| #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) |
| #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ |
| #define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) |
| #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) |
| #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) |
| |
| #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) |
| #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) |
| #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) |
| |
| #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) |
| #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) |
| #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ |
| #define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) |
| #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) |
| #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) |
| |
| #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) |
| #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) |
| #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) |
| |
| #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) |
| #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) |
| #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ |
| #define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) |
| #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) |
| #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) |
| |
| #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) |
| #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) |
| #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) |
| |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) |
| |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) |
| #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ |
| #define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) |
| #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) |
| #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) |
| |
| #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) |
| #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) |
| #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) |
| |
| #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) |
| #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) |
| #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ |
| #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) |
| #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) |
| #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) |
| |
| #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) |
| #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) |
| #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) |
| |
| #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) |
| #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) |
| #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) |
| |
| #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) |
| #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) |
| #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ |
| #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) |
| #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) |
| #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) |
| |
| #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) |
| #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) |
| #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) |
| |
| #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) |
| #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) |
| #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) |
| |
| #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) |
| #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) |
| #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) |
| |
| /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ |
| #define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4) |
| |
| #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) |
| #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) |
| #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) |
| |
| #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) |
| #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) |
| #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) |
| |
| /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ |
| #define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4) |
| |
| #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) |
| #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) |
| #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) |
| #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) |
| #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) |
| #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) |
| #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) |
| #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) |
| #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) |
| #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) |
| #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) |
| #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) |
| #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) |
| #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) |
| #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) |
| #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) |
| #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) |
| #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) |
| |
| #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) |
| #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) |
| #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) |
| |
| /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ |
| #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4) |
| |
| #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) |
| #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) |
| #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) |
| #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) |
| #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) |
| #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) |
| #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) |
| #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) |
| #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) |
| #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) |
| #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) |
| #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) |
| #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) |
| |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ |
| FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) |
| #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ |
| FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ |
| #define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4) |
| |
| #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) |
| #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) |
| #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) |
| |
| #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) |
| #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) |
| #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ |
| #define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4) |
| |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ |
| FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) |
| |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ |
| FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) |
| |
| /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ |
| #define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) |
| #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) |
| #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) |
| |
| #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) |
| #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ |
| FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ |
| #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ |
| #define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ |
| #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ |
| #define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ |
| #define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ |
| #define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ |
| #define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ |
| #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ |
| #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ |
| #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ |
| #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ |
| #define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ |
| #define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ |
| #define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ |
| #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ |
| #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ |
| #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ |
| #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ |
| #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ |
| #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ |
| #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ |
| #define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ |
| #define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ |
| #define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ |
| #define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ |
| #define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ |
| #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ |
| #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ |
| #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ |
| #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ |
| #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ |
| #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ |
| #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ |
| #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ |
| #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ |
| #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ |
| #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ |
| #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ |
| #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ |
| #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ |
| #define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ |
| #define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ |
| #define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ |
| #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ |
| #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ |
| #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ |
| #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ |
| t, 13, 60, 0, 1, 312, 184, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ |
| #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ |
| t, 13, 60, 0, 1, 312, 188, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ |
| #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ |
| #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ |
| #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ |
| #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ |
| #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ |
| #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ |
| #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ |
| #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ |
| #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ |
| #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ |
| #define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ |
| #define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ |
| #define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ |
| #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ |
| #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ |
| #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ |
| #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ |
| #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ |
| #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ |
| #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ |
| #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ |
| #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ |
| #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ |
| #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ |
| #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ |
| #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ |
| #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ |
| #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ |
| #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ |
| #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ |
| #define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ |
| #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4) |
| |
| #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) |
| #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ |
| #define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ |
| #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4) |
| |
| #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) |
| #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ |
| #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ |
| #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4) |
| |
| #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) |
| #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ |
| #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ |
| #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4) |
| |
| #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) |
| #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ |
| #define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ |
| #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4) |
| |
| #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) |
| #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ |
| #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ |
| #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4) |
| |
| #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) |
| #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ |
| #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ |
| #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4) |
| |
| #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) |
| #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ |
| #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4) |
| |
| /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ |
| #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4) |
| |
| #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) |
| #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ |
| FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) |
| #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ |
| FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) |
| |
| /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ |
| #define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4) |
| |
| #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) |
| #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) |
| |
| #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) |
| #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) |
| |
| #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) |
| #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) |
| |
| #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) |
| #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) |
| |
| #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) |
| #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) |
| #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) |
| |
| #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) |
| #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) |
| #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) |
| |
| #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) |
| #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) |
| #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) |
| |
| #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) |
| #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) |
| #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) |
| |
| #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) |
| #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ |
| FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) |
| #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ |
| FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) |
| |
| /* DSM:RAM_CTRL:RAM_INIT */ |
| #define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) |
| |
| #define DSM_RAM_INIT_RAM_INIT BIT(1) |
| #define DSM_RAM_INIT_RAM_INIT_SET(x)\ |
| FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) |
| #define DSM_RAM_INIT_RAM_INIT_GET(x)\ |
| FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) |
| |
| #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) |
| #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ |
| FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) |
| #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ |
| FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) |
| |
| /* DSM:CFG:BUF_CFG */ |
| #define DSM_BUF_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) |
| |
| #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) |
| #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ |
| FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) |
| #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ |
| FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) |
| |
| #define DSM_BUF_CFG_AGING_ENA BIT(12) |
| #define DSM_BUF_CFG_AGING_ENA_SET(x)\ |
| FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) |
| #define DSM_BUF_CFG_AGING_ENA_GET(x)\ |
| FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) |
| |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ |
| FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ |
| FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) |
| |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ |
| FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) |
| #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ |
| FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) |
| |
| /* DSM:CFG:DEV_TX_STOP_WM_CFG */ |
| #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) |
| |
| #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) |
| #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ |
| FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) |
| #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ |
|
