| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| #include <dt-bindings/interrupt-controller/mips-gic.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/mt7621-clk.h> |
| #include <dt-bindings/reset/mt7621-reset.h> |
| |
| / { |
| compatible = "mediatek,mt7621-soc"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "mips,mips1004Kc"; |
| reg = <0>; |
| device_type = "cpu"; |
| }; |
| |
| cpu@1 { |
| compatible = "mips,mips1004Kc"; |
| reg = <1>; |
| device_type = "cpu"; |
| }; |
| }; |
| |
| cpuintc: cpuintc { |
| compatible = "mti,cpu-interrupt-controller"; |
| |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| |
| interrupt-controller; |
| }; |
| |
| mmc_fixed_3v3: regulator-3v3 { |
| compatible = "regulator-fixed"; |
| |
| enable-active-high; |
| |
| regulator-always-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "mmc_power"; |
| }; |
| |
| mmc_fixed_1v8_io: regulator-1v8 { |
| compatible = "regulator-fixed"; |
| |
| enable-active-high; |
| |
| regulator-always-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "mmc_io"; |
| }; |
| |
| pinctrl: pinctrl { |
| compatible = "ralink,mt7621-pinctrl"; |
| |
| i2c_pins: i2c0-pins { |
| pinmux { |
| groups = "i2c"; |
| function = "i2c"; |
| }; |
| }; |
| |
| mdio_pins: mdio0-pins { |
| pinmux { |
| groups = "mdio"; |
| function = "mdio"; |
| }; |
| }; |
| |
| nand_pins: nand0-pins { |
| sdhci-pinmux { |
| groups = "sdhci"; |
| function = "nand2"; |
| }; |
| |
| spi-pinmux { |
| groups = "spi"; |
| function = "nand1"; |
| }; |
| }; |
| |
| pcie_pins: pcie0-pins { |
| pinmux { |
| groups = "pcie"; |
| function = "gpio"; |
| }; |
| }; |
| |
| rgmii1_pins: rgmii1-pins { |
| pinmux { |
| groups = "rgmii1"; |
| function = "rgmii1"; |
| }; |
| }; |
| |
| rgmii2_pins: rgmii2-pins { |
| pinmux { |
| groups = "rgmii2"; |
| function = "rgmii2"; |
| }; |
| }; |
| |
| sdhci_pins: sdhci0-pins { |
| pinmux { |
| groups = "sdhci"; |
| function = "sdhci"; |
| }; |
| }; |
| |
| spi_pins: spi0-pins { |
| pinmux { |
| groups = "spi"; |
| function = "spi"; |
| }; |
| }; |
| |
| uart1_pins: uart1-pins { |
| pinmux { |
| groups = "uart1"; |
| function = "uart1"; |
| }; |
| }; |
| |
| uart2_pins: uart2-pins { |
| pinmux { |
| groups = "uart2"; |
| function = "uart2"; |
| }; |
| }; |
| |
| uart3_pins: uart3-pins { |
| pinmux { |
| groups = "uart3"; |
| function = "uart3"; |
| }; |
| }; |
| }; |
| |
| palmbus: palmbus@1e000000 { |
| compatible = "palmbus"; |
| reg = <0x1e000000 0x100000>; |
| ranges = <0x0 0x1e000000 0x0fffff>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| sysc: syscon@0 { |
| compatible = "mediatek,mt7621-sysc", "syscon"; |
| reg = <0x0 0x100>; |
| |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| |
| clock-output-names = "xtal", "cpu", "bus", |
| "50m", "125m", "150m", |
| "250m", "270m"; |
| |
| ralink,memctl = <&memc>; |
| }; |
| |
| wdt: watchdog@100 { |
| compatible = "mediatek,mt7621-wdt"; |
| reg = <0x100 0x100>; |
| mediatek,sysctl = <&sysc>; |
| }; |
| |
| gpio: gpio@600 { |
| compatible = "mediatek,mt7621-gpio"; |
| reg = <0x600 0x100>; |
| |
| #gpio-cells = <2>; |
| #interrupt-cells = <2>; |
| |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 0 95>; |
| |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| i2c: i2c@900 { |
| compatible = "mediatek,mt7621-i2c"; |
| reg = <0x900 0x100>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clocks = <&sysc MT7621_CLK_I2C>; |
| clock-names = "i2c"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins>; |
| |
| resets = <&sysc MT7621_RST_I2C>; |
| reset-names = "i2c"; |
| |
| status = "disabled"; |
| }; |
| |
| memc: memory-controller@5000 { |
| compatible = "mediatek,mt7621-memc", "syscon"; |
| reg = <0x5000 0x1000>; |
| }; |
| |
| serial0: serial@c00 { |
| compatible = "ns16550a"; |
| reg = <0xc00 0x100>; |
| |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| |
| clocks = <&sysc MT7621_CLK_UART1>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; |
| |
| no-loopback-test; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| }; |
| |
| serial1: serial@d00 { |
| compatible = "ns16550a"; |
| reg = <0xd00 0x100>; |
| |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| |
| clocks = <&sysc MT7621_CLK_UART2>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; |
| |
| no-loopback-test; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| |
| status = "disabled"; |
| }; |
| |
| serial2: serial@e00 { |
| compatible = "ns16550a"; |
| reg = <0xe00 0x100>; |
| |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| |
| clocks = <&sysc MT7621_CLK_UART3>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; |
| |
| no-loopback-test; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins>; |
| |
| status = "disabled"; |
| }; |
| |
| spi0: spi@b00 { |
| compatible = "ralink,mt7621-spi"; |
| reg = <0xb00 0x100>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clock-names = "spi"; |
| clocks = <&sysc MT7621_CLK_SPI>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins>; |
| |
| reset-names = "spi"; |
| resets = <&sysc MT7621_RST_SPI>; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| mmc: mmc@1e130000 { |
| compatible = "mediatek,mt7620-mmc"; |
| reg = <0x1e130000 0x4000>; |
| |
| bus-width = <4>; |
| |
| cap-mmc-highspeed; |
| cap-sd-highspeed; |
| |
| clocks = <&sysc MT7621_CLK_SHXC>, |
| <&sysc MT7621_CLK_50M>; |
| clock-names = "source", "hclk"; |
| |
| disable-wp; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; |
| |
| max-frequency = <48000000>; |
| |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&sdhci_pins>; |
| pinctrl-1 = <&sdhci_pins>; |
| |
| vmmc-supply = <&mmc_fixed_3v3>; |
| vqmmc-supply = <&mmc_fixed_1v8_io>; |
| |
| status = "disabled"; |
| }; |
| |
| usb: usb@1e1c0000 { |
| compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci"; |
| reg = <0x1e1c0000 0x1000 |
| 0x1e1d0700 0x0100>; |
| reg-names = "mac", "ippc"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clocks = <&sysc MT7621_CLK_XTAL>; |
| clock-names = "sys_ck"; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gic: interrupt-controller@1fbc0000 { |
| compatible = "mti,gic"; |
| reg = <0x1fbc0000 0x2000>; |
| |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| |
| mti,reserved-cpu-vectors = <7>; |
| |
| timer { |
| compatible = "mti,gic-timer"; |
| clocks = <&sysc MT7621_CLK_CPU>; |
| interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| }; |
| }; |
| |
| cpc: cpc@1fbf0000 { |
| compatible = "mti,mips-cpc"; |
| reg = <0x1fbf0000 0x8000>; |
| }; |
| |
| cdmm: cdmm@1fbf8000 { |
| compatible = "mti,mips-cdmm"; |
| reg = <0x1fbf8000 0x8000>; |
| }; |
| |
| ethernet: ethernet@1e100000 { |
| compatible = "mediatek,mt7621-eth"; |
| reg = <0x1e100000 0x10000>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clock-names = "fe", "ethif"; |
| clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; |
| |
| reset-names = "fe", "eth"; |
| resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; |
| |
| mediatek,ethsys = <&sysc>; |
| |
| mdio: mdio-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| switch0: switch@1f { |
| compatible = "mediatek,mt7621"; |
| reg = <0x1f>; |
| |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reset-names = "mcm"; |
| resets = <&sysc MT7621_RST_MCM>; |
| |
| mediatek,mcm; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| label = "swp0"; |
| status = "disabled"; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| label = "swp1"; |
| status = "disabled"; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| label = "swp2"; |
| status = "disabled"; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| label = "swp3"; |
| status = "disabled"; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| label = "swp4"; |
| status = "disabled"; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| |
| ethernet = <&gmac1>; |
| phy-mode = "rgmii"; |
| |
| fixed-link { |
| full-duplex; |
| pause; |
| speed = <1000>; |
| }; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| |
| ethernet = <&gmac0>; |
| phy-mode = "trgmii"; |
| |
| fixed-link { |
| full-duplex; |
| pause; |
| speed = <1000>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| gmac0: mac@0 { |
| compatible = "mediatek,eth-mac"; |
| reg = <0>; |
| |
| phy-mode = "trgmii"; |
| |
| fixed-link { |
| full-duplex; |
| pause; |
| speed = <1000>; |
| }; |
| }; |
| |
| gmac1: mac@1 { |
| compatible = "mediatek,eth-mac"; |
| reg = <1>; |
| |
| phy-mode = "rgmii"; |
| |
| fixed-link { |
| full-duplex; |
| pause; |
| speed = <1000>; |
| }; |
| }; |
| |
| }; |
| |
| pcie: pcie@1e140000 { |
| compatible = "mediatek,mt7621-pci"; |
| reg = <0x1e140000 0x100>, /* host-pci bridge registers */ |
| <0x1e142000 0x100>, /* pcie port 0 RC control registers */ |
| <0x1e143000 0x100>, /* pcie port 1 RC control registers */ |
| <0x1e144000 0x100>; /* pcie port 2 RC control registers */ |
| ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ |
| <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ |
| |
| #address-cells = <3>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| |
| device_type = "pci"; |
| |
| interrupt-map-mask = <0xf800 0 0 0>; |
| interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, |
| <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, |
| <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie_pins>; |
| |
| reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; |
| |
| status = "disabled"; |
| |
| pcie@0,0 { |
| reg = <0x0000 0 0 0 0>; |
| ranges; |
| |
| #address-cells = <3>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| |
| clocks = <&sysc MT7621_CLK_PCIE0>; |
| |
| device_type = "pci"; |
| |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; |
| |
| phy-names = "pcie-phy0"; |
| phys = <&pcie0_phy 1>; |
| |
| resets = <&sysc MT7621_RST_PCIE0>; |
| }; |
| |
| pcie@1,0 { |
| reg = <0x0800 0 0 0 0>; |
| ranges; |
| |
| #address-cells = <3>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| |
| clocks = <&sysc MT7621_CLK_PCIE1>; |
| |
| device_type = "pci"; |
| |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; |
| |
| phy-names = "pcie-phy1"; |
| phys = <&pcie0_phy 1>; |
| |
| resets = <&sysc MT7621_RST_PCIE1>; |
| }; |
| |
| pcie@2,0 { |
| reg = <0x1000 0 0 0 0>; |
| ranges; |
| |
| #address-cells = <3>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| |
| clocks = <&sysc MT7621_CLK_PCIE2>; |
| |
| device_type = "pci"; |
| |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
| |
| phy-names = "pcie-phy2"; |
| phys = <&pcie2_phy 0>; |
| |
| resets = <&sysc MT7621_RST_PCIE2>; |
| }; |
| }; |
| |
| pcie0_phy: pcie-phy@1e149000 { |
| compatible = "mediatek,mt7621-pci-phy"; |
| reg = <0x1e149000 0x0700>; |
| |
| #phy-cells = <1>; |
| |
| clocks = <&sysc MT7621_CLK_XTAL>; |
| }; |
| |
| pcie2_phy: pcie-phy@1e14a000 { |
| compatible = "mediatek,mt7621-pci-phy"; |
| reg = <0x1e14a000 0x0700>; |
| |
| #phy-cells = <1>; |
| |
| clocks = <&sysc MT7621_CLK_XTAL>; |
| }; |
| }; |
