| commit | 564c836fd945a94b5dd46597d6b7adb464092650 | [log] [tgz] |
|---|---|---|
| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | Mon Sep 14 18:05:00 2020 +0200 |
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | Tue Sep 15 10:40:29 2020 +0200 |
| tree | 1c8500388f9aada05ebd9958f2b26b30c72b132f | |
| parent | baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da [diff] |
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>