clk: tegra: pll: Change misc_reg count from 3 to 6
New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index ced19e7..488ee67 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -156,6 +156,8 @@
u8 override_divp_shift;
};
+#define MAX_PLL_MISC_REG_COUNT 6
+
/**
* struct tegra_clk_pll_params - PLL parameters
*
@@ -225,7 +227,7 @@
u32 iddq_bit_idx;
u32 aux_reg;
u32 dyn_ramp_reg;
- u32 ext_misc_reg[3];
+ u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
u32 pmc_divnm_reg;
u32 pmc_divp_reg;
u32 flags;
