// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

/delete-node/ &enet1_lpcg;
/delete-node/ &fec2;

&conn_subsys {
	conn_enet0_root_clk: clock-conn-enet0-root {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "conn_enet0_root_clk";
	};

	eqos: ethernet@5b050000 {
		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
		reg = <0x5b050000 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "eth_wake_irq", "macirq";
		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
			 <&eqos_lpcg IMX_LPCG_CLK_6>,
			 <&eqos_lpcg IMX_LPCG_CLK_0>,
			 <&eqos_lpcg IMX_LPCG_CLK_5>,
			 <&eqos_lpcg IMX_LPCG_CLK_2>;
		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <125000000>;
		power-domains = <&pd IMX_SC_R_ENET_1>;
		status = "disabled";
	};

	usbotg2: usb@5b0e0000 {
		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
		reg = <0x5b0e0000 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		fsl,usbphy = <&usbphy2>;
		fsl,usbmisc = <&usbmisc2 0>;
		/*
		 * usbotg1 and usbotg2 share one clcok.
		 * scu firmware disables the access to the clock and keeps
		 * it always on in case other core (M4) uses one of these.
		 */
		clocks = <&clk_dummy>;
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>;
		rx-burst-size-dword = <0x10>;
		#stream-id-cells = <1>;
		power-domains = <&pd IMX_SC_R_USB_1>;
		status = "disabled";

		clk_dummy: clock-dummy {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "clk_dummy";
		};
	};

	usbmisc2: usbmisc@5b0e0200 {
		#index-cells = <1>;
		compatible = "fsl,imx7ulp-usbmisc";
		reg = <0x5b0e0200 0x200>;
	};

	usbphy2: usbphy@5b110000 {
		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
		reg = <0x5b110000 0x1000>;
		clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
		status = "disabled";
	};

	eqos_lpcg: clock-controller@5b240000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b240000 0x10000>;
		#clock-cells = <1>;
		clocks = <&conn_enet0_root_clk>,
			 <&conn_axi_clk>,
			 <&conn_axi_clk>,
			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
				<IMX_LPCG_CLK_6>;
		clock-output-names = "eqos_ptp",
				     "eqos_mem_clk",
				     "eqos_aclk",
				     "eqos_clk",
				     "eqos_csr_clk";
		power-domains = <&pd IMX_SC_R_ENET_1>;
	};

	usb2_2_lpcg: clock-controller@5b280000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b280000 0x10000>;
		#clock-cells = <1>;
		clock-indices = <IMX_LPCG_CLK_7>;
		clocks = <&conn_ipg_clk>;
		clock-output-names = "usboh3_2_phy_ipg_clk";
		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
	};

};

&enet0_lpcg {
	clocks = <&conn_enet0_root_clk>,
		 <&conn_enet0_root_clk>,
		 <&conn_axi_clk>,
		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
		 <&conn_ipg_clk>,
		 <&conn_ipg_clk>;
};

&fec1 {
	compatible = "fsl,imx8qm-fec";
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
	assigned-clock-rates = <125000000>;
};

&usdhc1 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
};

&usdhc2 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
};

&usdhc3 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};

&usbotg1 {
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	/*
	 * usbotg1 and usbotg2 share one clock
	 * scfw disable clock access and keep it always on
	 * in case other core (M4) use one of these.
	 */
	clocks = <&clk_dummy>;
};