tree 83e623346682dd5a3072266bbe419bdf00619809
parent e65b30951e50708cb306eb75231329a3a3029a7d
parent d06d60d52ec0b0eef702dd3e7b4699f0b589ad0f
author Linus Torvalds <torvalds@linux-foundation.org> 1605896186 -0800
committer Linus Torvalds <torvalds@linux-foundation.org> 1605896186 -0800
mergetag object d06d60d52ec0b0eef702dd3e7b4699f0b589ad0f
 type commit
 tag mmc-v5.10-rc4
 tagger Ulf Hansson <ulf.hansson@linaro.org> 1605868774 +0100
 
 MMC host:
  - sdhci-of-arasan: Stabilize communication by fixing tap value configs
  - sdhci-pci: Use SDR25 timing for HS mode for BYT-based Intel HWs
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAl+3nr8XHHVsZi5oYW5z
 c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCmbSQ//QkzuRoGDX9OuCorTF5FbesZk
 5dKPjxPcZy+EbMPegEZkH8hIEpHWgiwnUt4UjN7TbxsPsdpEXzws+ChY1mvdID0o
 K1Uj1bl4ngKHDiLgFChwoLvVPpbK9H0SMV4tosymBnhBpsVE4MfYSRd68ZP2EIXh
 9YpP4SJYBfMqhPpvddqA4o4qzYLgAG5NhOTmsp1HvAE2nrDZ5UclrJRVzIu+zd0m
 nGP9Jbh+ygGF3GpYOYgg6KawBe9MnTwThY7yBDt7K5Qad+WXvXQ/wJ23hfNs3+0a
 S17uSF29Ymd8X6Na8mSjNvZIN2bsDjxj/yy1VnQRebQR0jzzbb0ebBSXpjNWJiZ7
 xLj9YJLiNNEu7eFRp4/9zFI5r5y1VxqV8bAuuLIa0HMEdKEq6aia2JxLEznnD1TA
 ZQZoe916UiEnMSVrkdu8rkg4hnzmAngc4DxJMrE4AeRInQevA0dLdwpma8Vn0cIb
 HIEd9U5Oz83emM+ongQTW5EF1NhKuHqtxACmCNIFBMrZ/T9PT3Qgq4yhOSEx/GOg
 +tegTFumlz8LduwQekMdEdUp8BDlVdRlsEvqg1A4CtXmZ2lFG2NCQVjJXNxMCT+E
 Mh6+Pv8XojVPLBhkTh4WmE6MaOEwSdknzR+UJ2tKB5Pa7iyJT1nD4/T4jKp2/HNn
 qgqO2W5LWuOn/oLaalI=
 =kfSz
 -----END PGP SIGNATURE-----

Merge tag 'mmc-v5.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson:
 "A couple of MMC fixes:

   - sdhci-of-arasan: Stabilize communication by fixing tap value configs

   - sdhci-pci: Use SDR25 timing for HS mode for BYT-based Intel HWs"

* tag 'mmc-v5.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-of-arasan: Issue DLL reset explicitly
  mmc: sdhci-of-arasan: Use Mask writes for Tap delays
  mmc: sdhci-of-arasan: Allow configuring zero tap values
  mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers