/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_
#define GAUDI2_BLOCKS_LINUX_DRIVER_H_

#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull
#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull
#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull
#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull
#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull
#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull
#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull
#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull
#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull
#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull
#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull
#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull
#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull
#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull
#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull
#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull
#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull
#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull
#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull
#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull
#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull
#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull
#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull
#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull
#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC0_EML_CS_BASE 0x1FF000ull
#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC1_ROM_TABLE_BASE 0x200000ull
#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC1_EML_SPMU_BASE 0x201000ull
#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC1_EML_ETF_BASE 0x202000ull
#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC1_EML_STM_BASE 0x203000ull
#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC1_EML_CTI_BASE 0x205000ull
#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull
#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull
#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull
#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull
#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull
#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull
#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC1_EML_CFG_BASE 0x240000ull
#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull
#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull
#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull
#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull
#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull
#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull
#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull
#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull
#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull
#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull
#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull
#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull
#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull
#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull
#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull
#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull
#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC1_EML_CS_BASE 0x3FF000ull
#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC1_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC2_ROM_TABLE_BASE 0x400000ull
#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC2_EML_SPMU_BASE 0x401000ull
#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC2_EML_ETF_BASE 0x402000ull
#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC2_EML_STM_BASE 0x403000ull
#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC2_EML_CTI_BASE 0x405000ull
#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull
#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull
#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull
#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull
#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull
#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull
#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC2_EML_CFG_BASE 0x440000ull
#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull
#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull
#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull
#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull
#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull
#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull
#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull
#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull
#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull
#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull
#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull
#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull
#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull
#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull
#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull
#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull
#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC2_EML_CS_BASE 0x5FF000ull
#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC2_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC3_ROM_TABLE_BASE 0x600000ull
#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC3_EML_SPMU_BASE 0x601000ull
#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC3_EML_ETF_BASE 0x602000ull
#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC3_EML_STM_BASE 0x603000ull
#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC3_EML_CTI_BASE 0x605000ull
#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull
#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull
#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull
#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull
#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull
#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull
#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC3_EML_CFG_BASE 0x640000ull
#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull
#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull
#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull
#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull
#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull
#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull
#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull
#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull
#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull
#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull
#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull
#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull
#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull
#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull
#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull
#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull
#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC3_EML_CS_BASE 0x7FF000ull
#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC3_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC4_ROM_TABLE_BASE 0x800000ull
#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC4_EML_SPMU_BASE 0x801000ull
#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC4_EML_ETF_BASE 0x802000ull
#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC4_EML_STM_BASE 0x803000ull
#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC4_EML_CTI_BASE 0x805000ull
#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull
#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull
#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull
#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull
#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull
#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull
#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC4_EML_CFG_BASE 0x840000ull
#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull
#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull
#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull
#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull
#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull
#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull
#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull
#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull
#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull
#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull
#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull
#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull
#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull
#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull
#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull
#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull
#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC4_EML_CS_BASE 0x9FF000ull
#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC4_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull
#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC5_EML_SPMU_BASE 0xA01000ull
#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC5_EML_ETF_BASE 0xA02000ull
#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC5_EML_STM_BASE 0xA03000ull
#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC5_EML_CTI_BASE 0xA05000ull
#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull
#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull
#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull
#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull
#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull
#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull
#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC5_EML_CFG_BASE 0xA40000ull
#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull
#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull
#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull
#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull
#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull
#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull
#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull
#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull
#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull
#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull
#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull
#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull
#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull
#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull
#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull
#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull
#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC5_EML_CS_BASE 0xBFF000ull
#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC5_EML_CS_SECTION 0x1000
#define mmDCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull
#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC6_EML_SPMU_BASE 0xC01000ull
#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC6_EML_ETF_BASE 0xC02000ull
#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC6_EML_STM_BASE 0xC03000ull
#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC6_EML_CTI_BASE 0xC05000ull
#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull
#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull
#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull
#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull
#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull
#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull
#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC6_EML_CFG_BASE 0xC40000ull
#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull
#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull
#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull
#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull
#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull
#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull
#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull
#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull
#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull
#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull
#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull
#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull
#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull
#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull
#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull
#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull
#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE0_TPC6_EML_CS_BASE 0xDFF000ull
#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000
#define DCORE0_TPC6_EML_CS_SECTION 0x201000
#define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull
#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC0_EML_SPMU_BASE 0x1001000ull
#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC0_EML_ETF_BASE 0x1002000ull
#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC0_EML_STM_BASE 0x1003000ull
#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC0_EML_CTI_BASE 0x1005000ull
#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull
#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull
#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull
#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull
#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull
#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull
#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC0_EML_CFG_BASE 0x1040000ull
#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull
#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull
#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull
#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull
#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull
#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull
#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull
#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull
#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull
#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull
#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull
#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull
#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull
#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull
#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull
#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull
#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC0_EML_CS_BASE 0x11FF000ull
#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC0_EML_CS_SECTION 0x1000
#define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull
#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC1_EML_SPMU_BASE 0x1201000ull
#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC1_EML_ETF_BASE 0x1202000ull
#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC1_EML_STM_BASE 0x1203000ull
#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC1_EML_CTI_BASE 0x1205000ull
#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull
#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull
#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull
#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull
#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull
#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull
#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC1_EML_CFG_BASE 0x1240000ull
#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull
#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull
#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull
#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull
#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull
#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull
#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull
#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull
#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull
#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull
#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull
#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull
#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull
#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull
#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull
#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull
#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC1_EML_CS_BASE 0x13FF000ull
#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC1_EML_CS_SECTION 0x1000
#define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull
#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC2_EML_SPMU_BASE 0x1401000ull
#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC2_EML_ETF_BASE 0x1402000ull
#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC2_EML_STM_BASE 0x1403000ull
#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC2_EML_CTI_BASE 0x1405000ull
#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull
#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull
#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull
#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull
#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull
#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull
#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC2_EML_CFG_BASE 0x1440000ull
#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull
#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull
#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull
#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull
#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull
#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull
#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull
#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull
#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull
#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull
#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull
#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull
#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull
#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull
#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull
#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull
#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC2_EML_CS_BASE 0x15FF000ull
#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC2_EML_CS_SECTION 0x1000
#define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull
#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC3_EML_SPMU_BASE 0x1601000ull
#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC3_EML_ETF_BASE 0x1602000ull
#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC3_EML_STM_BASE 0x1603000ull
#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC3_EML_CTI_BASE 0x1605000ull
#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull
#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull
#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull
#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull
#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull
#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull
#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC3_EML_CFG_BASE 0x1640000ull
#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull
#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull
#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull
#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull
#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull
#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull
#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull
#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull
#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull
#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull
#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull
#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull
#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull
#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull
#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull
#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull
#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC3_EML_CS_BASE 0x17FF000ull
#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC3_EML_CS_SECTION 0x1000
#define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull
#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC4_EML_SPMU_BASE 0x1801000ull
#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC4_EML_ETF_BASE 0x1802000ull
#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC4_EML_STM_BASE 0x1803000ull
#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC4_EML_CTI_BASE 0x1805000ull
#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull
#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull
#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull
#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull
#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull
#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull
#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC4_EML_CFG_BASE 0x1840000ull
#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull
#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull
#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull
#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull
#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull
#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull
#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull
#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull
#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull
#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull
#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull
#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull
#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull
#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull
#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull
#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull
#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC4_EML_CS_BASE 0x19FF000ull
#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC4_EML_CS_SECTION 0x1000
#define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull
#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull
#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000
#define mmDCORE1_TPC5_EML_ETF_BASE 0x1A02000ull
#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_ETF_SECTION 0x1000
#define mmDCORE1_TPC5_EML_STM_BASE 0x1A03000ull
#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_STM_SECTION 0x2000
#define mmDCORE1_TPC5_EML_CTI_BASE 0x1A05000ull
#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_CTI_SECTION 0x1000
#define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull
#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000
#define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull
#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull
#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull
#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull
#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull
#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE1_TPC5_EML_CFG_BASE 0x1A40000ull
#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_CFG_SECTION 0xE800
#define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull
#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull
#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull
#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull
#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull
#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull
#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull
#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull
#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull
#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull
#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull
#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull
#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull
#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull
#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull
#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull
#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE1_TPC5_EML_CS_BASE 0x1BFF000ull
#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000
#define DCORE1_TPC5_EML_CS_SECTION 0x401000
#define mmDCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull
#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC0_EML_SPMU_BASE 0x2001000ull
#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC0_EML_ETF_BASE 0x2002000ull
#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC0_EML_STM_BASE 0x2003000ull
#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC0_EML_CTI_BASE 0x2005000ull
#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull
#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull
#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull
#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull
#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull
#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull
#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC0_EML_CFG_BASE 0x2040000ull
#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull
#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull
#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull
#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull
#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull
#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull
#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull
#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull
#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull
#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull
#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull
#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull
#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull
#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull
#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull
#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull
#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC0_EML_CS_BASE 0x21FF000ull
#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC0_EML_CS_SECTION 0x1000
#define mmDCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull
#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC1_EML_SPMU_BASE 0x2201000ull
#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC1_EML_ETF_BASE 0x2202000ull
#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC1_EML_STM_BASE 0x2203000ull
#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC1_EML_CTI_BASE 0x2205000ull
#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull
#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull
#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull
#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull
#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull
#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull
#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC1_EML_CFG_BASE 0x2240000ull
#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull
#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull
#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull
#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull
#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull
#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull
#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull
#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull
#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull
#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull
#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull
#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull
#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull
#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull
#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull
#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull
#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC1_EML_CS_BASE 0x23FF000ull
#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC1_EML_CS_SECTION 0x1000
#define mmDCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull
#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC2_EML_SPMU_BASE 0x2401000ull
#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC2_EML_ETF_BASE 0x2402000ull
#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC2_EML_STM_BASE 0x2403000ull
#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC2_EML_CTI_BASE 0x2405000ull
#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull
#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull
#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull
#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull
#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull
#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull
#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC2_EML_CFG_BASE 0x2440000ull
#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull
#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull
#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull
#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull
#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull
#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull
#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull
#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull
#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull
#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull
#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull
#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull
#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull
#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull
#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull
#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull
#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC2_EML_CS_BASE 0x25FF000ull
#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC2_EML_CS_SECTION 0x1000
#define mmDCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull
#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC3_EML_SPMU_BASE 0x2601000ull
#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC3_EML_ETF_BASE 0x2602000ull
#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC3_EML_STM_BASE 0x2603000ull
#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC3_EML_CTI_BASE 0x2605000ull
#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull
#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull
#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull
#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull
#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull
#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull
#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC3_EML_CFG_BASE 0x2640000ull
#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull
#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull
#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull
#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull
#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull
#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull
#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull
#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull
#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull
#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull
#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull
#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull
#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull
#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull
#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull
#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull
#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC3_EML_CS_BASE 0x27FF000ull
#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC3_EML_CS_SECTION 0x1000
#define mmDCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull
#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC4_EML_SPMU_BASE 0x2801000ull
#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC4_EML_ETF_BASE 0x2802000ull
#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC4_EML_STM_BASE 0x2803000ull
#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC4_EML_CTI_BASE 0x2805000ull
#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull
#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull
#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull
#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull
#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull
#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull
#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC4_EML_CFG_BASE 0x2840000ull
#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull
#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull
#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull
#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull
#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull
#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull
#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull
#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull
#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull
#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull
#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull
#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull
#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull
#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull
#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull
#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull
#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC4_EML_CS_BASE 0x29FF000ull
#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC4_EML_CS_SECTION 0x1000
#define mmDCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull
#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull
#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000
#define mmDCORE2_TPC5_EML_ETF_BASE 0x2A02000ull
#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_ETF_SECTION 0x1000
#define mmDCORE2_TPC5_EML_STM_BASE 0x2A03000ull
#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_STM_SECTION 0x2000
#define mmDCORE2_TPC5_EML_CTI_BASE 0x2A05000ull
#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_CTI_SECTION 0x1000
#define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull
#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000
#define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull
#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull
#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull
#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull
#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull
#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE2_TPC5_EML_CFG_BASE 0x2A40000ull
#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_CFG_SECTION 0xE800
#define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull
#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull
#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull
#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull
#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull
#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull
#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull
#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull
#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull
#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull
#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull
#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull
#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull
#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull
#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull
#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull
#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE2_TPC5_EML_CS_BASE 0x2BFF000ull
#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000
#define DCORE2_TPC5_EML_CS_SECTION 0x401000
#define mmDCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull
#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC0_EML_SPMU_BASE 0x3001000ull
#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC0_EML_ETF_BASE 0x3002000ull
#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC0_EML_STM_BASE 0x3003000ull
#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC0_EML_CTI_BASE 0x3005000ull
#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull
#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull
#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull
#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull
#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull
#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull
#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC0_EML_CFG_BASE 0x3040000ull
#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull
#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull
#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull
#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull
#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull
#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull
#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull
#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull
#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull
#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull
#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull
#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull
#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull
#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull
#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull
#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull
#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC0_EML_CS_BASE 0x31FF000ull
#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC0_EML_CS_SECTION 0x1000
#define mmDCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull
#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC1_EML_SPMU_BASE 0x3201000ull
#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC1_EML_ETF_BASE 0x3202000ull
#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC1_EML_STM_BASE 0x3203000ull
#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC1_EML_CTI_BASE 0x3205000ull
#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull
#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull
#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull
#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull
#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull
#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull
#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC1_EML_CFG_BASE 0x3240000ull
#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull
#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull
#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull
#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull
#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull
#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull
#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull
#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull
#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull
#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull
#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull
#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull
#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull
#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull
#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull
#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull
#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC1_EML_CS_BASE 0x33FF000ull
#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC1_EML_CS_SECTION 0x1000
#define mmDCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull
#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC2_EML_SPMU_BASE 0x3401000ull
#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC2_EML_ETF_BASE 0x3402000ull
#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC2_EML_STM_BASE 0x3403000ull
#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC2_EML_CTI_BASE 0x3405000ull
#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull
#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull
#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull
#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull
#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull
#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull
#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC2_EML_CFG_BASE 0x3440000ull
#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull
#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull
#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull
#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull
#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull
#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull
#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull
#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull
#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull
#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull
#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull
#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull
#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull
#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull
#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull
#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull
#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC2_EML_CS_BASE 0x35FF000ull
#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC2_EML_CS_SECTION 0x1000
#define mmDCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull
#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC3_EML_SPMU_BASE 0x3601000ull
#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC3_EML_ETF_BASE 0x3602000ull
#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC3_EML_STM_BASE 0x3603000ull
#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC3_EML_CTI_BASE 0x3605000ull
#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull
#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull
#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull
#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull
#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull
#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull
#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC3_EML_CFG_BASE 0x3640000ull
#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull
#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull
#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull
#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull
#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull
#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull
#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull
#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull
#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull
#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull
#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull
#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull
#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull
#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull
#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull
#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull
#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC3_EML_CS_BASE 0x37FF000ull
#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC3_EML_CS_SECTION 0x1000
#define mmDCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull
#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC4_EML_SPMU_BASE 0x3801000ull
#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC4_EML_ETF_BASE 0x3802000ull
#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC4_EML_STM_BASE 0x3803000ull
#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC4_EML_CTI_BASE 0x3805000ull
#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull
#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull
#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull
#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull
#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull
#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull
#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC4_EML_CFG_BASE 0x3840000ull
#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull
#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull
#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull
#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull
#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull
#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull
#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull
#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull
#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull
#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull
#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull
#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull
#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull
#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull
#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull
#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull
#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC4_EML_CS_BASE 0x39FF000ull
#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC4_EML_CS_SECTION 0x1000
#define mmDCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull
#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull
#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000
#define mmDCORE3_TPC5_EML_ETF_BASE 0x3A02000ull
#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_ETF_SECTION 0x1000
#define mmDCORE3_TPC5_EML_STM_BASE 0x3A03000ull
#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_STM_SECTION 0x2000
#define mmDCORE3_TPC5_EML_CTI_BASE 0x3A05000ull
#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_CTI_SECTION 0x1000
#define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull
#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000
#define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull
#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull
#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull
#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull
#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull
#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE3_TPC5_EML_CFG_BASE 0x3A40000ull
#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_CFG_SECTION 0xE800
#define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull
#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull
#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull
#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull
#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull
#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull
#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull
#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull
#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800
#define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull
#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull
#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull
#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull
#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull
#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull
#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull
#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull
#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180
#define mmDCORE3_TPC5_EML_CS_BASE 0x3BFF000ull
#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000
#define DCORE3_TPC5_EML_CS_SECTION 0x401000
#define mmDCORE0_TPC0_QM_DCCM_BASE 0x4000000ull
#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull
#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull
#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC0_QM_BASE 0x400A000ull
#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC0_QM_SECTION 0x9000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull
#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull
#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull
#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull
#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC0_QM_CGM_BASE 0x400AD80ull
#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC0_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull
#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_CFG_BASE 0x400B000ull
#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC0_CFG_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull
#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull
#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull
#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull
#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull
#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull
#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull
#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull
#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull
#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull
#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull
#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull
#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull
#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull
#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull
#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull
#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull
#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull
#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull
#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull
#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull
#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull
#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull
#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull
#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC1_QM_DCCM_BASE 0x4010000ull
#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull
#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull
#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC1_QM_BASE 0x401A000ull
#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC1_QM_SECTION 0x9000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull
#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull
#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull
#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull
#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC1_QM_CGM_BASE 0x401AD80ull
#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC1_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull
#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_CFG_BASE 0x401B000ull
#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC1_CFG_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull
#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull
#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull
#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull
#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull
#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull
#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull
#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull
#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull
#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull
#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull
#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull
#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull
#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull
#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull
#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull
#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull
#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull
#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull
#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull
#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull
#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull
#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull
#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull
#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC2_QM_DCCM_BASE 0x4020000ull
#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull
#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull
#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC2_QM_BASE 0x402A000ull
#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC2_QM_SECTION 0x9000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull
#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull
#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull
#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull
#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC2_QM_CGM_BASE 0x402AD80ull
#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC2_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull
#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_CFG_BASE 0x402B000ull
#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC2_CFG_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull
#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull
#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull
#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull
#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull
#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull
#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull
#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull
#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull
#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull
#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull
#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull
#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull
#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull
#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull
#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull
#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull
#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull
#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull
#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull
#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull
#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull
#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull
#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull
#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC3_QM_DCCM_BASE 0x4030000ull
#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull
#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull
#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC3_QM_BASE 0x403A000ull
#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC3_QM_SECTION 0x9000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull
#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull
#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull
#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull
#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC3_QM_CGM_BASE 0x403AD80ull
#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC3_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull
#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_CFG_BASE 0x403B000ull
#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC3_CFG_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull
#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull
#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull
#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull
#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull
#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull
#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull
#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull
#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull
#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull
#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull
#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull
#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull
#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull
#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull
#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull
#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull
#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull
#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull
#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull
#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull
#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull
#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull
#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull
#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC4_QM_DCCM_BASE 0x4040000ull
#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull
#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull
#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC4_QM_BASE 0x404A000ull
#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC4_QM_SECTION 0x9000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull
#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull
#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull
#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull
#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC4_QM_CGM_BASE 0x404AD80ull
#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC4_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull
#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_CFG_BASE 0x404B000ull
#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC4_CFG_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull
#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull
#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull
#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull
#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull
#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull
#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull
#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull
#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull
#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull
#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull
#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull
#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull
#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull
#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull
#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull
#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull
#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull
#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull
#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull
#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull
#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull
#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull
#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull
#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC5_QM_DCCM_BASE 0x4050000ull
#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull
#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull
#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC5_QM_BASE 0x405A000ull
#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC5_QM_SECTION 0x9000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull
#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull
#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull
#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull
#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC5_QM_CGM_BASE 0x405AD80ull
#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC5_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull
#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_CFG_BASE 0x405B000ull
#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC5_CFG_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull
#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull
#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull
#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull
#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull
#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull
#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull
#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull
#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull
#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull
#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull
#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull
#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull
#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull
#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull
#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull
#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull
#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull
#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull
#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull
#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull
#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull
#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull
#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull
#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_TPC6_QM_DCCM_BASE 0x4060000ull
#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000
#define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull
#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull
#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_TPC6_QM_BASE 0x406A000ull
#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000
#define DCORE0_TPC6_QM_SECTION 0x9000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull
#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull
#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull
#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull
#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_TPC6_QM_CGM_BASE 0x406AD80ull
#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_TPC6_QM_CGM_SECTION 0x1000
#define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull
#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_CFG_BASE 0x406B000ull
#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC6_CFG_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull
#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull
#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400
#define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull
#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull
#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull
#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull
#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull
#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull
#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull
#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull
#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull
#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400
#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0
#define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull
#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull
#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull
#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull
#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull
#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull
#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull
#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull
#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull
#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull
#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull
#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull
#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull
#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180
#define mmDCORE0_HMMU0_MMU_BASE 0x4080000ull
#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_MMU_SECTION 0xE800
#define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull
#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU0_STLB_BASE 0x4081000ull
#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_STLB_SECTION 0xE800
#define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull
#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull
#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull
#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull
#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull
#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull
#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull
#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull
#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull
#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull
#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull
#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull
#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull
#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull
#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE0_HMMU1_MMU_BASE 0x4090000ull
#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_MMU_SECTION 0xE800
#define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull
#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU1_STLB_BASE 0x4091000ull
#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_STLB_SECTION 0xE800
#define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull
#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull
#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull
#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull
#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull
#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull
#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull
#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull
#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull
#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull
#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull
#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull
#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull
#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull
#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE0_HMMU2_MMU_BASE 0x40A0000ull
#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_MMU_SECTION 0xE800
#define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull
#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU2_STLB_BASE 0x40A1000ull
#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_STLB_SECTION 0xE800
#define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull
#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull
#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull
#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull
#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull
#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull
#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull
#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull
#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull
#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull
#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull
#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull
#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull
#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull
#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE0_HMMU3_MMU_BASE 0x40B0000ull
#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_MMU_SECTION 0xE800
#define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull
#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU3_STLB_BASE 0x40B1000ull
#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_STLB_SECTION 0xE800
#define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull
#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull
#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull
#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull
#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull
#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull
#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull
#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull
#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull
#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull
#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull
#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull
#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull
#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull
#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull
#define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000
#define mmDCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull
#define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull
#define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull
#define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
#define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000
#define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull
#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
#define mmDCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull
#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_QM_BASE 0x40CA000ull
#define DCORE0_MME_QM_MAX_OFFSET 0x1000
#define DCORE0_MME_QM_SECTION 0x9000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull
#define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull
#define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull
#define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull
#define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_MME_QM_CGM_BASE 0x40CAD80ull
#define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_MME_QM_CGM_SECTION 0x1000
#define mmDCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull
#define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_CTRL_LO_BASE 0x40CB000ull
#define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_LO_SECTION 0x8000
#define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull
#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull
#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull
#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
#define mmDCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull
#define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull
#define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_BASE 0x40CC000ull
#define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_HI_SECTION 0x8000
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull
#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull
#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull
#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull
#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
#define mmDCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull
#define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_EU_BIST_BASE 0x40CD000ull
#define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000
#define DCORE0_MME_EU_BIST_SECTION 0xE800
#define mmDCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull
#define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull
#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull
#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull
#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull
#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull
#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull
#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull
#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull
#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull
#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull
#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull
#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull
#define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
#define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800
#define mmDCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull
#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE0_BASE 0x40D0000ull
#define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_SECTION 0xE800
#define mmDCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull
#define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull
#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull
#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull
#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull
#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull
#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull
#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull
#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull
#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull
#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull
#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull
#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE0_MME_SBTE1_BASE 0x40D8000ull
#define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_SECTION 0xE800
#define mmDCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull
#define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull
#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull
#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull
#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull
#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull
#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull
#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull
#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull
#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull
#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull
#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull
#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE0_MME_SBTE2_BASE 0x40E0000ull
#define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_SECTION 0xE800
#define mmDCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull
#define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull
#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull
#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull
#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull
#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull
#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull
#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull
#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull
#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull
#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull
#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull
#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE0_MME_SBTE3_BASE 0x40E8000ull
#define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_SECTION 0xE800
#define mmDCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull
#define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull
#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull
#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull
#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull
#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull
#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull
#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull
#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull
#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull
#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull
#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull
#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE0_MME_SBTE4_BASE 0x40F0000ull
#define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_SECTION 0xE800
#define mmDCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull
#define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull
#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull
#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull
#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull
#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull
#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull
#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull
#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull
#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull
#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull
#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull
#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE0_MME_ACC_BASE 0x40F8000ull
#define DCORE0_MME_ACC_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_SECTION 0xE800
#define mmDCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull
#define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull
#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull
#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull
#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull
#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull
#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull
#define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull
#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull
#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull
#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull
#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull
#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull
#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull
#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull
#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull
#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull
#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull
#define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull
#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull
#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull
#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull
#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull
#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
#define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull
#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000
#define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull
#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800
#define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull
#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull
#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull
#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull
#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull
#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull
#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull
#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull
#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_HIF0_BASE 0x4120000ull
#define DCORE0_HIF0_MAX_OFFSET 0x1000
#define DCORE0_HIF0_SECTION 0xE800
#define mmDCORE0_HIF0_SPECIAL_BASE 0x4120E80ull
#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HIF0_SPECIAL_SECTION 0x3180
#define mmDCORE0_HIF1_BASE 0x4124000ull
#define DCORE0_HIF1_MAX_OFFSET 0x1000
#define DCORE0_HIF1_SECTION 0xE800
#define mmDCORE0_HIF1_SPECIAL_BASE 0x4124E80ull
#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HIF1_SPECIAL_SECTION 0x3180
#define mmDCORE0_HIF2_BASE 0x4128000ull
#define DCORE0_HIF2_MAX_OFFSET 0x1000
#define DCORE0_HIF2_SECTION 0xE800
#define mmDCORE0_HIF2_SPECIAL_BASE 0x4128E80ull
#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HIF2_SPECIAL_SECTION 0x3180
#define mmDCORE0_HIF3_BASE 0x412C000ull
#define DCORE0_HIF3_MAX_OFFSET 0x1000
#define DCORE0_HIF3_SECTION 0xE800
#define mmDCORE0_HIF3_SPECIAL_BASE 0x412CE80ull
#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HIF3_SPECIAL_SECTION 0x13180
#define mmDCORE0_RTR0_CTRL_BASE 0x4140000ull
#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR0_CTRL_SECTION 0xE800
#define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull
#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR0_H3_BASE 0x4141000ull
#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR0_H3_SECTION 0xE800
#define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull
#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull
#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull
#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull
#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull
#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull
#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull
#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull
#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull
#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull
#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull
#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull
#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull
#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull
#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull
#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR0_BASE 0x4144000ull
#define DCORE0_RTR0_MAX_OFFSET 0x1000
#define DCORE0_RTR0_SECTION 0x3000
#define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull
#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull
#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull
#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull
#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull
#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull
#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull
#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull
#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull
#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull
#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull
#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull
#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull
#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull
#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR0_SPECIAL_BASE 0x4144E80ull
#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull
#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull
#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR1_CTRL_BASE 0x4148000ull
#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR1_CTRL_SECTION 0xE800
#define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull
#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR1_H3_BASE 0x4149000ull
#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR1_H3_SECTION 0xE800
#define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull
#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull
#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull
#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull
#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull
#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull
#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull
#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull
#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull
#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull
#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull
#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull
#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull
#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull
#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull
#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR1_BASE 0x414C000ull
#define DCORE0_RTR1_MAX_OFFSET 0x1000
#define DCORE0_RTR1_SECTION 0x3000
#define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull
#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull
#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull
#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull
#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull
#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull
#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull
#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull
#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull
#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull
#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull
#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull
#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull
#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull
#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR1_SPECIAL_BASE 0x414CE80ull
#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull
#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull
#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR2_CTRL_BASE 0x4150000ull
#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR2_CTRL_SECTION 0xE800
#define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull
#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR2_H3_BASE 0x4151000ull
#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR2_H3_SECTION 0xE800
#define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull
#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull
#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull
#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull
#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull
#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull
#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull
#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull
#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull
#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull
#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull
#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull
#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull
#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull
#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull
#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR2_BASE 0x4154000ull
#define DCORE0_RTR2_MAX_OFFSET 0x1000
#define DCORE0_RTR2_SECTION 0x3000
#define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull
#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull
#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull
#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull
#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull
#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull
#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull
#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull
#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull
#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull
#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull
#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull
#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull
#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull
#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR2_SPECIAL_BASE 0x4154E80ull
#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull
#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull
#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR3_CTRL_BASE 0x4158000ull
#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR3_CTRL_SECTION 0xE800
#define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull
#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR3_H3_BASE 0x4159000ull
#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR3_H3_SECTION 0xE800
#define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull
#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull
#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull
#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull
#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull
#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull
#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull
#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull
#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull
#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull
#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull
#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull
#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull
#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull
#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull
#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR3_BASE 0x415C000ull
#define DCORE0_RTR3_MAX_OFFSET 0x1000
#define DCORE0_RTR3_SECTION 0x3000
#define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull
#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull
#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull
#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull
#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull
#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull
#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull
#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull
#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull
#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull
#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull
#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull
#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull
#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull
#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR3_SPECIAL_BASE 0x415CE80ull
#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull
#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull
#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR4_CTRL_BASE 0x4160000ull
#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR4_CTRL_SECTION 0xE800
#define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull
#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR4_H3_BASE 0x4161000ull
#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR4_H3_SECTION 0xE800
#define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull
#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull
#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull
#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull
#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull
#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull
#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull
#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull
#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull
#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull
#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull
#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull
#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull
#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull
#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull
#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR4_BASE 0x4164000ull
#define DCORE0_RTR4_MAX_OFFSET 0x1000
#define DCORE0_RTR4_SECTION 0x3000
#define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull
#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull
#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull
#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull
#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull
#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull
#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull
#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull
#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull
#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull
#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull
#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull
#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull
#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull
#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR4_SPECIAL_BASE 0x4164E80ull
#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull
#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull
#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR5_CTRL_BASE 0x4168000ull
#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR5_CTRL_SECTION 0xE800
#define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull
#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR5_H3_BASE 0x4169000ull
#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR5_H3_SECTION 0xE800
#define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull
#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull
#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull
#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull
#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull
#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull
#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull
#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull
#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull
#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull
#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull
#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull
#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull
#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull
#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull
#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR5_BASE 0x416C000ull
#define DCORE0_RTR5_MAX_OFFSET 0x1000
#define DCORE0_RTR5_SECTION 0x3000
#define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull
#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull
#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull
#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull
#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull
#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull
#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull
#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull
#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull
#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull
#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull
#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull
#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull
#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull
#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR5_SPECIAL_BASE 0x416CE80ull
#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull
#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull
#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR6_CTRL_BASE 0x4170000ull
#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR6_CTRL_SECTION 0xE800
#define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull
#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR6_H3_BASE 0x4171000ull
#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR6_H3_SECTION 0xE800
#define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull
#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull
#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull
#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull
#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull
#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull
#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull
#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull
#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull
#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull
#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull
#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull
#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull
#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull
#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull
#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR6_BASE 0x4174000ull
#define DCORE0_RTR6_MAX_OFFSET 0x1000
#define DCORE0_RTR6_SECTION 0x3000
#define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull
#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull
#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull
#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull
#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull
#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull
#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull
#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull
#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull
#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull
#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull
#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull
#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull
#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull
#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR6_SPECIAL_BASE 0x4174E80ull
#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull
#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull
#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_RTR7_CTRL_BASE 0x4178000ull
#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000
#define DCORE0_RTR7_CTRL_SECTION 0xE800
#define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull
#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR7_H3_BASE 0x4179000ull
#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000
#define DCORE0_RTR7_H3_SECTION 0xE800
#define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull
#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull
#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull
#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull
#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull
#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull
#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull
#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull
#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull
#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull
#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull
#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull
#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull
#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull
#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull
#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR7_BASE 0x417C000ull
#define DCORE0_RTR7_MAX_OFFSET 0x1000
#define DCORE0_RTR7_SECTION 0x3000
#define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull
#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull
#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull
#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull
#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull
#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull
#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull
#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull
#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull
#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000
#define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull
#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull
#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull
#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull
#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull
#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE0_RTR7_SPECIAL_BASE 0x417CE80ull
#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_SPECIAL_SECTION 0x1800
#define mmDCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull
#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800
#define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull
#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE0_SRAM0_BANK_BASE 0x4180000ull
#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM0_BANK_SECTION 0xE800
#define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull
#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM0_RTR_BASE 0x4181000ull
#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM0_RTR_SECTION 0xE800
#define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull
#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull
#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull
#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull
#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull
#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull
#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull
#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull
#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull
#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull
#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull
#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull
#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull
#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull
#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull
#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull
#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull
#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM1_BANK_BASE 0x4188000ull
#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM1_BANK_SECTION 0xE800
#define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull
#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM1_RTR_BASE 0x4189000ull
#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM1_RTR_SECTION 0xE800
#define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull
#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull
#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull
#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull
#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull
#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull
#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull
#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull
#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull
#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull
#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull
#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull
#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull
#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull
#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull
#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull
#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull
#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM2_BANK_BASE 0x4190000ull
#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM2_BANK_SECTION 0xE800
#define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull
#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM2_RTR_BASE 0x4191000ull
#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM2_RTR_SECTION 0xE800
#define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull
#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull
#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull
#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull
#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull
#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull
#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull
#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull
#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull
#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull
#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull
#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull
#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull
#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull
#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull
#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull
#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull
#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM3_BANK_BASE 0x4198000ull
#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM3_BANK_SECTION 0xE800
#define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull
#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM3_RTR_BASE 0x4199000ull
#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM3_RTR_SECTION 0xE800
#define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull
#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull
#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull
#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull
#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull
#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull
#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull
#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull
#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull
#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull
#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull
#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull
#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull
#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull
#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull
#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull
#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull
#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM4_BANK_BASE 0x41A0000ull
#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM4_BANK_SECTION 0xE800
#define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull
#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM4_RTR_BASE 0x41A1000ull
#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM4_RTR_SECTION 0xE800
#define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull
#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull
#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull
#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull
#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull
#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull
#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull
#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull
#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull
#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull
#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull
#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull
#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull
#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull
#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull
#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull
#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull
#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM5_BANK_BASE 0x41A8000ull
#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM5_BANK_SECTION 0xE800
#define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull
#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM5_RTR_BASE 0x41A9000ull
#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM5_RTR_SECTION 0xE800
#define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull
#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull
#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull
#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull
#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull
#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull
#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull
#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull
#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull
#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull
#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull
#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull
#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull
#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull
#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull
#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull
#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull
#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM6_BANK_BASE 0x41B0000ull
#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM6_BANK_SECTION 0xE800
#define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull
#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM6_RTR_BASE 0x41B1000ull
#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM6_RTR_SECTION 0xE800
#define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull
#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull
#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull
#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull
#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull
#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull
#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull
#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull
#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull
#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull
#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull
#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull
#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull
#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull
#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull
#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull
#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull
#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_SRAM7_BANK_BASE 0x41B8000ull
#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000
#define DCORE0_SRAM7_BANK_SECTION 0xE800
#define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull
#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM7_RTR_BASE 0x41B9000ull
#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000
#define DCORE0_SRAM7_RTR_SECTION 0xE800
#define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull
#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull
#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull
#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull
#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull
#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull
#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull
#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull
#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull
#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull
#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull
#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull
#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull
#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull
#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull
#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull
#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull
#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull
#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull
#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull
#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_EDMA0_QM_BASE 0x41CA000ull
#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_QM_SECTION 0x9000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull
#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull
#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull
#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull
#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull
#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000
#define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull
#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_EDMA0_CORE_BASE 0x41CB000ull
#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CORE_SECTION 0x8000
#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull
#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull
#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00
#define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull
#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull
#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull
#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull
#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull
#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull
#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull
#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull
#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull
#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull
#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull
#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull
#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull
#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull
#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull
#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull
#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE0_EDMA1_QM_BASE 0x41DA000ull
#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_QM_SECTION 0x9000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull
#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull
#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull
#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull
#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull
#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000
#define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull
#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE0_EDMA1_CORE_BASE 0x41DB000ull
#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CORE_SECTION 0x8000
#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull
#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull
#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00
#define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull
#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull
#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull
#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull
#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull
#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull
#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull
#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull
#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull
#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull
#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull
#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull
#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull
#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE0_DEC0_CMD_BASE 0x41E0000ull
#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100
#define DCORE0_DEC0_CMD_SECTION 0x1000
#define mmDCORE0_DEC0_VSI_BASE 0x41E1000ull
#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0
#define DCORE0_DEC0_VSI_SECTION 0x1000
#define mmDCORE0_DEC0_L2C_BASE 0x41E2000ull
#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0
#define DCORE0_DEC0_L2C_SECTION 0x1000
#define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull
#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000
#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull
#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_VDEC0_CTRL_BASE 0x41E4000ull
#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CTRL_SECTION 0xE800
#define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull
#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull
#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull
#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull
#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull
#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull
#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull
#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull
#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull
#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull
#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull
#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull
#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE0_DEC1_CMD_BASE 0x41F0000ull
#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100
#define DCORE0_DEC1_CMD_SECTION 0x1000
#define mmDCORE0_DEC1_VSI_BASE 0x41F1000ull
#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0
#define DCORE0_DEC1_VSI_SECTION 0x1000
#define mmDCORE0_DEC1_L2C_BASE 0x41F2000ull
#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0
#define DCORE0_DEC1_L2C_SECTION 0x1000
#define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull
#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000
#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull
#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_VDEC1_CTRL_BASE 0x41F4000ull
#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CTRL_SECTION 0xE800
#define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull
#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull
#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull
#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull
#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull
#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull
#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull
#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull
#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull
#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull
#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull
#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull
#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE1_TPC0_QM_DCCM_BASE 0x4200000ull
#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull
#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull
#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC0_QM_BASE 0x420A000ull
#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC0_QM_SECTION 0x9000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull
#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull
#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull
#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull
#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC0_QM_CGM_BASE 0x420AD80ull
#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC0_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull
#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_CFG_BASE 0x420B000ull
#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC0_CFG_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull
#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull
#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull
#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull
#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull
#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull
#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull
#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull
#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull
#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull
#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull
#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull
#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull
#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull
#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull
#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull
#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull
#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull
#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull
#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull
#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull
#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull
#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull
#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull
#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_TPC1_QM_DCCM_BASE 0x4210000ull
#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull
#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull
#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC1_QM_BASE 0x421A000ull
#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC1_QM_SECTION 0x9000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull
#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull
#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull
#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull
#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC1_QM_CGM_BASE 0x421AD80ull
#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC1_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull
#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_CFG_BASE 0x421B000ull
#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC1_CFG_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull
#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull
#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull
#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull
#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull
#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull
#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull
#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull
#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull
#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull
#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull
#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull
#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull
#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull
#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull
#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull
#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull
#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull
#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull
#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull
#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull
#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull
#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull
#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull
#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_TPC2_QM_DCCM_BASE 0x4220000ull
#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull
#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull
#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC2_QM_BASE 0x422A000ull
#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC2_QM_SECTION 0x9000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull
#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull
#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull
#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull
#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC2_QM_CGM_BASE 0x422AD80ull
#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC2_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull
#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_CFG_BASE 0x422B000ull
#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC2_CFG_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull
#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull
#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull
#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull
#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull
#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull
#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull
#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull
#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull
#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull
#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull
#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull
#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull
#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull
#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull
#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull
#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull
#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull
#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull
#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull
#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull
#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull
#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull
#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull
#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_TPC3_QM_DCCM_BASE 0x4230000ull
#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull
#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull
#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC3_QM_BASE 0x423A000ull
#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC3_QM_SECTION 0x9000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull
#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull
#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull
#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull
#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC3_QM_CGM_BASE 0x423AD80ull
#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC3_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull
#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_CFG_BASE 0x423B000ull
#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC3_CFG_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull
#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull
#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull
#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull
#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull
#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull
#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull
#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull
#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull
#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull
#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull
#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull
#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull
#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull
#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull
#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull
#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull
#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull
#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull
#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull
#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull
#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull
#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull
#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull
#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_TPC4_QM_DCCM_BASE 0x4240000ull
#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull
#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull
#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC4_QM_BASE 0x424A000ull
#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC4_QM_SECTION 0x9000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull
#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull
#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull
#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull
#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC4_QM_CGM_BASE 0x424AD80ull
#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC4_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull
#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_CFG_BASE 0x424B000ull
#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC4_CFG_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull
#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull
#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull
#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull
#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull
#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull
#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull
#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull
#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull
#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull
#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull
#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull
#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull
#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull
#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull
#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull
#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull
#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull
#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull
#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull
#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull
#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull
#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull
#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull
#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_TPC5_QM_DCCM_BASE 0x4250000ull
#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000
#define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull
#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull
#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_TPC5_QM_BASE 0x425A000ull
#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000
#define DCORE1_TPC5_QM_SECTION 0x9000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull
#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull
#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull
#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull
#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_TPC5_QM_CGM_BASE 0x425AD80ull
#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_TPC5_QM_CGM_SECTION 0x1000
#define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull
#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_CFG_BASE 0x425B000ull
#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000
#define DCORE1_TPC5_CFG_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull
#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull
#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400
#define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull
#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull
#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull
#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull
#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull
#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull
#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull
#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull
#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull
#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400
#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0
#define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull
#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull
#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull
#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull
#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull
#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull
#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull
#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull
#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull
#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull
#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull
#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull
#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull
#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
#define mmDCORE1_HMMU0_MMU_BASE 0x4280000ull
#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_MMU_SECTION 0xE800
#define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull
#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU0_STLB_BASE 0x4281000ull
#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_STLB_SECTION 0xE800
#define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull
#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull
#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull
#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull
#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull
#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull
#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull
#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull
#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull
#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull
#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull
#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull
#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull
#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull
#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE1_HMMU1_MMU_BASE 0x4290000ull
#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_MMU_SECTION 0xE800
#define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull
#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU1_STLB_BASE 0x4291000ull
#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_STLB_SECTION 0xE800
#define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull
#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull
#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull
#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull
#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull
#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull
#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull
#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull
#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull
#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull
#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull
#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull
#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull
#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull
#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE1_HMMU2_MMU_BASE 0x42A0000ull
#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_MMU_SECTION 0xE800
#define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull
#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU2_STLB_BASE 0x42A1000ull
#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_STLB_SECTION 0xE800
#define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull
#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull
#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull
#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull
#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull
#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull
#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull
#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull
#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull
#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull
#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull
#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull
#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull
#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull
#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE1_HMMU3_MMU_BASE 0x42B0000ull
#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_MMU_SECTION 0xE800
#define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull
#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU3_STLB_BASE 0x42B1000ull
#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_STLB_SECTION 0xE800
#define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull
#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull
#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull
#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull
#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull
#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull
#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull
#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull
#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull
#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull
#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull
#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull
#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull
#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull
#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull
#define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000
#define mmDCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull
#define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull
#define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull
#define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
#define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000
#define mmDCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull
#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
#define mmDCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull
#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_QM_BASE 0x42CA000ull
#define DCORE1_MME_QM_MAX_OFFSET 0x1000
#define DCORE1_MME_QM_SECTION 0x9000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull
#define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull
#define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull
#define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull
#define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_MME_QM_CGM_BASE 0x42CAD80ull
#define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_MME_QM_CGM_SECTION 0x1000
#define mmDCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull
#define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_CTRL_LO_BASE 0x42CB000ull
#define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_LO_SECTION 0x8000
#define mmDCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull
#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull
#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
#define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull
#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
#define mmDCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull
#define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull
#define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_BASE 0x42CC000ull
#define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_HI_SECTION 0x8000
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull
#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull
#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull
#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull
#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
#define mmDCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull
#define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_EU_BIST_BASE 0x42CD000ull
#define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000
#define DCORE1_MME_EU_BIST_SECTION 0xE800
#define mmDCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull
#define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull
#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull
#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull
#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull
#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull
#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull
#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull
#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull
#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull
#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull
#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull
#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull
#define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
#define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800
#define mmDCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull
#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE0_BASE 0x42D0000ull
#define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_SECTION 0xE800
#define mmDCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull
#define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull
#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull
#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull
#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull
#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull
#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull
#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull
#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull
#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull
#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull
#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull
#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE1_MME_SBTE1_BASE 0x42D8000ull
#define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_SECTION 0xE800
#define mmDCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull
#define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull
#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull
#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull
#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull
#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull
#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull
#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull
#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull
#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull
#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull
#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull
#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE1_MME_SBTE2_BASE 0x42E0000ull
#define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_SECTION 0xE800
#define mmDCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull
#define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull
#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull
#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull
#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull
#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull
#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull
#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull
#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull
#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull
#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull
#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull
#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE1_MME_SBTE3_BASE 0x42E8000ull
#define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_SECTION 0xE800
#define mmDCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull
#define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull
#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull
#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull
#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull
#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull
#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull
#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull
#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull
#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull
#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull
#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull
#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE1_MME_SBTE4_BASE 0x42F0000ull
#define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_SECTION 0xE800
#define mmDCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull
#define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull
#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull
#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull
#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull
#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull
#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull
#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull
#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull
#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull
#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull
#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull
#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE1_MME_ACC_BASE 0x42F8000ull
#define DCORE1_MME_ACC_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_SECTION 0xE800
#define mmDCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull
#define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull
#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull
#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull
#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull
#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull
#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull
#define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull
#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull
#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull
#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull
#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull
#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull
#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull
#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull
#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull
#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull
#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull
#define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull
#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull
#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull
#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull
#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull
#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
#define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull
#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000
#define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull
#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800
#define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull
#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull
#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull
#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull
#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull
#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull
#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull
#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull
#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_HIF0_BASE 0x4320000ull
#define DCORE1_HIF0_MAX_OFFSET 0x1000
#define DCORE1_HIF0_SECTION 0xE800
#define mmDCORE1_HIF0_SPECIAL_BASE 0x4320E80ull
#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HIF0_SPECIAL_SECTION 0x3180
#define mmDCORE1_HIF1_BASE 0x4324000ull
#define DCORE1_HIF1_MAX_OFFSET 0x1000
#define DCORE1_HIF1_SECTION 0xE800
#define mmDCORE1_HIF1_SPECIAL_BASE 0x4324E80ull
#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HIF1_SPECIAL_SECTION 0x3180
#define mmDCORE1_HIF2_BASE 0x4328000ull
#define DCORE1_HIF2_MAX_OFFSET 0x1000
#define DCORE1_HIF2_SECTION 0xE800
#define mmDCORE1_HIF2_SPECIAL_BASE 0x4328E80ull
#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HIF2_SPECIAL_SECTION 0x3180
#define mmDCORE1_HIF3_BASE 0x432C000ull
#define DCORE1_HIF3_MAX_OFFSET 0x1000
#define DCORE1_HIF3_SECTION 0xE800
#define mmDCORE1_HIF3_SPECIAL_BASE 0x432CE80ull
#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HIF3_SPECIAL_SECTION 0x13180
#define mmDCORE1_RTR0_CTRL_BASE 0x4340000ull
#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR0_CTRL_SECTION 0xE800
#define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull
#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR0_H3_BASE 0x4341000ull
#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR0_H3_SECTION 0xE800
#define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull
#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull
#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull
#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull
#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull
#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull
#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull
#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull
#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull
#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull
#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull
#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull
#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull
#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull
#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull
#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR0_BASE 0x4344000ull
#define DCORE1_RTR0_MAX_OFFSET 0x1000
#define DCORE1_RTR0_SECTION 0x3000
#define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull
#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull
#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull
#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull
#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull
#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull
#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull
#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull
#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull
#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull
#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull
#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull
#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull
#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull
#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR0_SPECIAL_BASE 0x4344E80ull
#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull
#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull
#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR1_CTRL_BASE 0x4348000ull
#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR1_CTRL_SECTION 0xE800
#define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull
#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR1_H3_BASE 0x4349000ull
#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR1_H3_SECTION 0xE800
#define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull
#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull
#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull
#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull
#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull
#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull
#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull
#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull
#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull
#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull
#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull
#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull
#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull
#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull
#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull
#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR1_BASE 0x434C000ull
#define DCORE1_RTR1_MAX_OFFSET 0x1000
#define DCORE1_RTR1_SECTION 0x3000
#define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull
#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull
#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull
#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull
#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull
#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull
#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull
#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull
#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull
#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull
#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull
#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull
#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull
#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull
#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR1_SPECIAL_BASE 0x434CE80ull
#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull
#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull
#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR2_CTRL_BASE 0x4350000ull
#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR2_CTRL_SECTION 0xE800
#define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull
#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR2_H3_BASE 0x4351000ull
#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR2_H3_SECTION 0xE800
#define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull
#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull
#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull
#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull
#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull
#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull
#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull
#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull
#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull
#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull
#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull
#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull
#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull
#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull
#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull
#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR2_BASE 0x4354000ull
#define DCORE1_RTR2_MAX_OFFSET 0x1000
#define DCORE1_RTR2_SECTION 0x3000
#define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull
#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull
#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull
#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull
#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull
#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull
#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull
#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull
#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull
#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull
#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull
#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull
#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull
#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull
#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR2_SPECIAL_BASE 0x4354E80ull
#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull
#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull
#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR3_CTRL_BASE 0x4358000ull
#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR3_CTRL_SECTION 0xE800
#define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull
#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR3_H3_BASE 0x4359000ull
#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR3_H3_SECTION 0xE800
#define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull
#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull
#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull
#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull
#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull
#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull
#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull
#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull
#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull
#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull
#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull
#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull
#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull
#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull
#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull
#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR3_BASE 0x435C000ull
#define DCORE1_RTR3_MAX_OFFSET 0x1000
#define DCORE1_RTR3_SECTION 0x3000
#define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull
#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull
#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull
#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull
#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull
#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull
#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull
#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull
#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull
#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull
#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull
#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull
#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull
#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull
#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR3_SPECIAL_BASE 0x435CE80ull
#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull
#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull
#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR4_CTRL_BASE 0x4360000ull
#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR4_CTRL_SECTION 0xE800
#define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull
#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR4_H3_BASE 0x4361000ull
#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR4_H3_SECTION 0xE800
#define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull
#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull
#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull
#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull
#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull
#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull
#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull
#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull
#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull
#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull
#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull
#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull
#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull
#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull
#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull
#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR4_BASE 0x4364000ull
#define DCORE1_RTR4_MAX_OFFSET 0x1000
#define DCORE1_RTR4_SECTION 0x3000
#define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull
#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull
#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull
#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull
#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull
#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull
#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull
#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull
#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull
#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull
#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull
#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull
#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull
#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull
#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR4_SPECIAL_BASE 0x4364E80ull
#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull
#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull
#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR5_CTRL_BASE 0x4368000ull
#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR5_CTRL_SECTION 0xE800
#define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull
#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR5_H3_BASE 0x4369000ull
#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR5_H3_SECTION 0xE800
#define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull
#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull
#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull
#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull
#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull
#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull
#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull
#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull
#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull
#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull
#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull
#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull
#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull
#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull
#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull
#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR5_BASE 0x436C000ull
#define DCORE1_RTR5_MAX_OFFSET 0x1000
#define DCORE1_RTR5_SECTION 0x3000
#define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull
#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull
#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull
#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull
#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull
#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull
#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull
#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull
#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull
#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull
#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull
#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull
#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull
#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull
#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR5_SPECIAL_BASE 0x436CE80ull
#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull
#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull
#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR6_CTRL_BASE 0x4370000ull
#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR6_CTRL_SECTION 0xE800
#define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull
#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR6_H3_BASE 0x4371000ull
#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR6_H3_SECTION 0xE800
#define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull
#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull
#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull
#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull
#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull
#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull
#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull
#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull
#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull
#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull
#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull
#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull
#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull
#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull
#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull
#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR6_BASE 0x4374000ull
#define DCORE1_RTR6_MAX_OFFSET 0x1000
#define DCORE1_RTR6_SECTION 0x3000
#define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull
#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull
#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull
#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull
#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull
#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull
#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull
#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull
#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull
#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull
#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull
#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull
#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull
#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull
#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR6_SPECIAL_BASE 0x4374E80ull
#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull
#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull
#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_RTR7_CTRL_BASE 0x4378000ull
#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000
#define DCORE1_RTR7_CTRL_SECTION 0xE800
#define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull
#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR7_H3_BASE 0x4379000ull
#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000
#define DCORE1_RTR7_H3_SECTION 0xE800
#define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull
#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull
#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull
#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull
#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull
#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull
#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull
#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull
#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull
#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull
#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull
#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull
#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull
#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull
#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull
#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR7_BASE 0x437C000ull
#define DCORE1_RTR7_MAX_OFFSET 0x1000
#define DCORE1_RTR7_SECTION 0x3000
#define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull
#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull
#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull
#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull
#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull
#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull
#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull
#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull
#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull
#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000
#define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull
#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull
#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull
#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull
#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull
#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE1_RTR7_SPECIAL_BASE 0x437CE80ull
#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_SPECIAL_SECTION 0x1800
#define mmDCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull
#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800
#define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull
#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE1_SRAM0_BANK_BASE 0x4380000ull
#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM0_BANK_SECTION 0xE800
#define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull
#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM0_RTR_BASE 0x4381000ull
#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM0_RTR_SECTION 0xE800
#define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull
#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull
#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull
#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull
#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull
#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull
#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull
#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull
#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull
#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull
#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull
#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull
#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull
#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull
#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull
#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull
#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull
#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM1_BANK_BASE 0x4388000ull
#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM1_BANK_SECTION 0xE800
#define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull
#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM1_RTR_BASE 0x4389000ull
#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM1_RTR_SECTION 0xE800
#define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull
#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull
#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull
#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull
#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull
#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull
#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull
#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull
#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull
#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull
#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull
#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull
#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull
#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull
#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull
#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull
#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull
#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM2_BANK_BASE 0x4390000ull
#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM2_BANK_SECTION 0xE800
#define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull
#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM2_RTR_BASE 0x4391000ull
#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM2_RTR_SECTION 0xE800
#define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull
#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull
#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull
#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull
#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull
#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull
#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull
#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull
#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull
#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull
#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull
#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull
#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull
#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull
#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull
#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull
#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull
#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM3_BANK_BASE 0x4398000ull
#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM3_BANK_SECTION 0xE800
#define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull
#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM3_RTR_BASE 0x4399000ull
#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM3_RTR_SECTION 0xE800
#define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull
#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull
#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull
#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull
#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull
#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull
#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull
#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull
#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull
#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull
#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull
#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull
#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull
#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull
#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull
#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull
#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull
#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM4_BANK_BASE 0x43A0000ull
#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM4_BANK_SECTION 0xE800
#define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull
#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM4_RTR_BASE 0x43A1000ull
#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM4_RTR_SECTION 0xE800
#define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull
#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull
#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull
#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull
#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull
#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull
#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull
#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull
#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull
#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull
#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull
#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull
#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull
#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull
#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull
#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull
#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull
#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM5_BANK_BASE 0x43A8000ull
#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM5_BANK_SECTION 0xE800
#define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull
#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM5_RTR_BASE 0x43A9000ull
#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM5_RTR_SECTION 0xE800
#define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull
#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull
#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull
#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull
#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull
#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull
#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull
#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull
#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull
#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull
#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull
#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull
#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull
#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull
#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull
#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull
#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull
#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM6_BANK_BASE 0x43B0000ull
#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM6_BANK_SECTION 0xE800
#define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull
#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM6_RTR_BASE 0x43B1000ull
#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM6_RTR_SECTION 0xE800
#define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull
#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull
#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull
#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull
#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull
#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull
#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull
#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull
#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull
#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull
#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull
#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull
#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull
#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull
#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull
#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull
#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull
#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_SRAM7_BANK_BASE 0x43B8000ull
#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000
#define DCORE1_SRAM7_BANK_SECTION 0xE800
#define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull
#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM7_RTR_BASE 0x43B9000ull
#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000
#define DCORE1_SRAM7_RTR_SECTION 0xE800
#define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull
#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull
#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull
#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull
#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull
#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull
#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull
#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull
#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull
#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull
#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull
#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull
#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull
#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull
#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull
#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull
#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull
#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull
#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull
#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull
#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_EDMA0_QM_BASE 0x43CA000ull
#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_QM_SECTION 0x9000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull
#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull
#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull
#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull
#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull
#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000
#define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull
#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_EDMA0_CORE_BASE 0x43CB000ull
#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CORE_SECTION 0x8000
#define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull
#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull
#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00
#define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull
#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull
#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull
#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull
#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull
#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull
#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull
#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull
#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull
#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull
#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull
#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull
#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull
#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull
#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull
#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull
#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE1_EDMA1_QM_BASE 0x43DA000ull
#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_QM_SECTION 0x9000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull
#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull
#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull
#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull
#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull
#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000
#define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull
#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE1_EDMA1_CORE_BASE 0x43DB000ull
#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CORE_SECTION 0x8000
#define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull
#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull
#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00
#define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull
#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull
#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull
#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull
#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull
#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull
#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull
#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull
#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull
#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull
#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull
#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull
#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull
#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE1_DEC0_CMD_BASE 0x43E0000ull
#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100
#define DCORE1_DEC0_CMD_SECTION 0x1000
#define mmDCORE1_DEC0_VSI_BASE 0x43E1000ull
#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0
#define DCORE1_DEC0_VSI_SECTION 0x1000
#define mmDCORE1_DEC0_L2C_BASE 0x43E2000ull
#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0
#define DCORE1_DEC0_L2C_SECTION 0x1000
#define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull
#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000
#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull
#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_VDEC0_CTRL_BASE 0x43E4000ull
#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CTRL_SECTION 0xE800
#define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull
#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull
#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull
#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull
#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull
#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull
#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull
#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull
#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull
#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull
#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull
#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull
#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE1_DEC1_CMD_BASE 0x43F0000ull
#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100
#define DCORE1_DEC1_CMD_SECTION 0x1000
#define mmDCORE1_DEC1_VSI_BASE 0x43F1000ull
#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0
#define DCORE1_DEC1_VSI_SECTION 0x1000
#define mmDCORE1_DEC1_L2C_BASE 0x43F2000ull
#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0
#define DCORE1_DEC1_L2C_SECTION 0x1000
#define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull
#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000
#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull
#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_VDEC1_CTRL_BASE 0x43F4000ull
#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CTRL_SECTION 0xE800
#define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull
#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull
#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull
#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull
#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull
#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull
#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull
#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull
#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull
#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull
#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull
#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull
#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE2_TPC0_QM_DCCM_BASE 0x4400000ull
#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull
#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull
#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC0_QM_BASE 0x440A000ull
#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC0_QM_SECTION 0x9000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull
#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull
#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull
#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull
#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC0_QM_CGM_BASE 0x440AD80ull
#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC0_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull
#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_CFG_BASE 0x440B000ull
#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC0_CFG_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull
#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull
#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull
#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull
#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull
#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull
#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull
#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull
#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull
#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull
#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull
#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull
#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull
#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull
#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull
#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull
#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull
#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull
#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull
#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull
#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull
#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull
#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull
#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull
#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_TPC1_QM_DCCM_BASE 0x4410000ull
#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull
#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull
#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC1_QM_BASE 0x441A000ull
#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC1_QM_SECTION 0x9000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull
#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull
#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull
#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull
#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC1_QM_CGM_BASE 0x441AD80ull
#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC1_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull
#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_CFG_BASE 0x441B000ull
#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC1_CFG_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull
#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull
#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull
#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull
#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull
#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull
#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull
#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull
#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull
#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull
#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull
#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull
#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull
#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull
#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull
#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull
#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull
#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull
#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull
#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull
#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull
#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull
#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull
#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull
#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_TPC2_QM_DCCM_BASE 0x4420000ull
#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull
#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull
#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC2_QM_BASE 0x442A000ull
#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC2_QM_SECTION 0x9000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull
#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull
#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull
#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull
#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC2_QM_CGM_BASE 0x442AD80ull
#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC2_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull
#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_CFG_BASE 0x442B000ull
#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC2_CFG_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull
#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull
#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull
#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull
#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull
#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull
#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull
#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull
#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull
#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull
#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull
#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull
#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull
#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull
#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull
#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull
#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull
#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull
#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull
#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull
#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull
#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull
#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull
#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull
#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_TPC3_QM_DCCM_BASE 0x4430000ull
#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull
#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull
#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC3_QM_BASE 0x443A000ull
#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC3_QM_SECTION 0x9000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull
#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull
#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull
#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull
#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC3_QM_CGM_BASE 0x443AD80ull
#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC3_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull
#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_CFG_BASE 0x443B000ull
#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC3_CFG_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull
#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull
#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull
#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull
#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull
#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull
#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull
#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull
#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull
#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull
#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull
#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull
#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull
#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull
#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull
#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull
#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull
#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull
#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull
#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull
#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull
#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull
#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull
#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull
#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_TPC4_QM_DCCM_BASE 0x4440000ull
#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull
#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull
#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC4_QM_BASE 0x444A000ull
#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC4_QM_SECTION 0x9000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull
#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull
#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull
#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull
#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC4_QM_CGM_BASE 0x444AD80ull
#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC4_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull
#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_CFG_BASE 0x444B000ull
#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC4_CFG_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull
#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull
#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull
#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull
#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull
#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull
#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull
#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull
#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull
#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull
#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull
#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull
#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull
#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull
#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull
#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull
#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull
#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull
#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull
#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull
#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull
#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull
#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull
#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull
#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_TPC5_QM_DCCM_BASE 0x4450000ull
#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000
#define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull
#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull
#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_TPC5_QM_BASE 0x445A000ull
#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000
#define DCORE2_TPC5_QM_SECTION 0x9000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull
#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull
#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull
#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull
#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_TPC5_QM_CGM_BASE 0x445AD80ull
#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_TPC5_QM_CGM_SECTION 0x1000
#define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull
#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_CFG_BASE 0x445B000ull
#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000
#define DCORE2_TPC5_CFG_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull
#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull
#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400
#define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull
#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull
#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull
#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull
#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull
#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull
#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull
#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull
#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull
#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400
#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0
#define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull
#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull
#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull
#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull
#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull
#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull
#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull
#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull
#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull
#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull
#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull
#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull
#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull
#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
#define mmDCORE2_HMMU0_MMU_BASE 0x4480000ull
#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_MMU_SECTION 0xE800
#define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull
#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU0_STLB_BASE 0x4481000ull
#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_STLB_SECTION 0xE800
#define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull
#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull
#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull
#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull
#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull
#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull
#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull
#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull
#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull
#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull
#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull
#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull
#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull
#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull
#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE2_HMMU1_MMU_BASE 0x4490000ull
#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_MMU_SECTION 0xE800
#define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull
#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU1_STLB_BASE 0x4491000ull
#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_STLB_SECTION 0xE800
#define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull
#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull
#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull
#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull
#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull
#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull
#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull
#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull
#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull
#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull
#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull
#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull
#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull
#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull
#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE2_HMMU2_MMU_BASE 0x44A0000ull
#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_MMU_SECTION 0xE800
#define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull
#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU2_STLB_BASE 0x44A1000ull
#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_STLB_SECTION 0xE800
#define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull
#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull
#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull
#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull
#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull
#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull
#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull
#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull
#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull
#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull
#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull
#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull
#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull
#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull
#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE2_HMMU3_MMU_BASE 0x44B0000ull
#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_MMU_SECTION 0xE800
#define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull
#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU3_STLB_BASE 0x44B1000ull
#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_STLB_SECTION 0xE800
#define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull
#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull
#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull
#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull
#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull
#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull
#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull
#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull
#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull
#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull
#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull
#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull
#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull
#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull
#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull
#define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000
#define mmDCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull
#define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull
#define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull
#define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
#define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000
#define mmDCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull
#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
#define mmDCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull
#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_QM_BASE 0x44CA000ull
#define DCORE2_MME_QM_MAX_OFFSET 0x1000
#define DCORE2_MME_QM_SECTION 0x9000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull
#define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull
#define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull
#define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull
#define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_MME_QM_CGM_BASE 0x44CAD80ull
#define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_MME_QM_CGM_SECTION 0x1000
#define mmDCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull
#define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_CTRL_LO_BASE 0x44CB000ull
#define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_LO_SECTION 0x8000
#define mmDCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull
#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull
#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
#define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull
#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
#define mmDCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull
#define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull
#define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_BASE 0x44CC000ull
#define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_HI_SECTION 0x8000
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull
#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull
#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull
#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull
#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
#define mmDCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull
#define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_EU_BIST_BASE 0x44CD000ull
#define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000
#define DCORE2_MME_EU_BIST_SECTION 0xE800
#define mmDCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull
#define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull
#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull
#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull
#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull
#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull
#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull
#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull
#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull
#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull
#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull
#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull
#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull
#define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
#define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800
#define mmDCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull
#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE0_BASE 0x44D0000ull
#define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_SECTION 0xE800
#define mmDCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull
#define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull
#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull
#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull
#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull
#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull
#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull
#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull
#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull
#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull
#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull
#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull
#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE2_MME_SBTE1_BASE 0x44D8000ull
#define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_SECTION 0xE800
#define mmDCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull
#define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull
#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull
#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull
#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull
#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull
#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull
#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull
#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull
#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull
#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull
#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull
#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE2_MME_SBTE2_BASE 0x44E0000ull
#define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_SECTION 0xE800
#define mmDCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull
#define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull
#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull
#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull
#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull
#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull
#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull
#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull
#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull
#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull
#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull
#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull
#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE2_MME_SBTE3_BASE 0x44E8000ull
#define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_SECTION 0xE800
#define mmDCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull
#define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull
#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull
#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull
#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull
#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull
#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull
#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull
#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull
#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull
#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull
#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull
#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE2_MME_SBTE4_BASE 0x44F0000ull
#define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_SECTION 0xE800
#define mmDCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull
#define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull
#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull
#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull
#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull
#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull
#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull
#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull
#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull
#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull
#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull
#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull
#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE2_MME_ACC_BASE 0x44F8000ull
#define DCORE2_MME_ACC_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_SECTION 0xE800
#define mmDCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull
#define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull
#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull
#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull
#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull
#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull
#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull
#define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull
#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull
#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull
#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull
#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull
#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull
#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull
#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull
#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull
#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull
#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull
#define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull
#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull
#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull
#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull
#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull
#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
#define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull
#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000
#define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull
#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800
#define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull
#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull
#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull
#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull
#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull
#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull
#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull
#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull
#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_HIF0_BASE 0x4520000ull
#define DCORE2_HIF0_MAX_OFFSET 0x1000
#define DCORE2_HIF0_SECTION 0xE800
#define mmDCORE2_HIF0_SPECIAL_BASE 0x4520E80ull
#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HIF0_SPECIAL_SECTION 0x3180
#define mmDCORE2_HIF1_BASE 0x4524000ull
#define DCORE2_HIF1_MAX_OFFSET 0x1000
#define DCORE2_HIF1_SECTION 0xE800
#define mmDCORE2_HIF1_SPECIAL_BASE 0x4524E80ull
#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HIF1_SPECIAL_SECTION 0x3180
#define mmDCORE2_HIF2_BASE 0x4528000ull
#define DCORE2_HIF2_MAX_OFFSET 0x1000
#define DCORE2_HIF2_SECTION 0xE800
#define mmDCORE2_HIF2_SPECIAL_BASE 0x4528E80ull
#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HIF2_SPECIAL_SECTION 0x3180
#define mmDCORE2_HIF3_BASE 0x452C000ull
#define DCORE2_HIF3_MAX_OFFSET 0x1000
#define DCORE2_HIF3_SECTION 0xE800
#define mmDCORE2_HIF3_SPECIAL_BASE 0x452CE80ull
#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HIF3_SPECIAL_SECTION 0x13180
#define mmDCORE2_RTR0_CTRL_BASE 0x4540000ull
#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR0_CTRL_SECTION 0xE800
#define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull
#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR0_H3_BASE 0x4541000ull
#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR0_H3_SECTION 0xE800
#define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull
#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull
#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull
#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull
#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull
#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull
#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull
#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull
#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull
#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull
#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull
#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull
#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull
#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull
#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull
#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR0_BASE 0x4544000ull
#define DCORE2_RTR0_MAX_OFFSET 0x1000
#define DCORE2_RTR0_SECTION 0x3000
#define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull
#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull
#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull
#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull
#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull
#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull
#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull
#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull
#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull
#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull
#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull
#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull
#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull
#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull
#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR0_SPECIAL_BASE 0x4544E80ull
#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull
#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull
#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR1_CTRL_BASE 0x4548000ull
#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR1_CTRL_SECTION 0xE800
#define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull
#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR1_H3_BASE 0x4549000ull
#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR1_H3_SECTION 0xE800
#define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull
#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull
#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull
#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull
#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull
#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull
#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull
#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull
#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull
#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull
#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull
#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull
#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull
#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull
#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull
#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR1_BASE 0x454C000ull
#define DCORE2_RTR1_MAX_OFFSET 0x1000
#define DCORE2_RTR1_SECTION 0x3000
#define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull
#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull
#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull
#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull
#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull
#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull
#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull
#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull
#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull
#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull
#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull
#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull
#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull
#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull
#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR1_SPECIAL_BASE 0x454CE80ull
#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull
#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull
#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR2_CTRL_BASE 0x4550000ull
#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR2_CTRL_SECTION 0xE800
#define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull
#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR2_H3_BASE 0x4551000ull
#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR2_H3_SECTION 0xE800
#define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull
#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull
#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull
#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull
#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull
#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull
#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull
#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull
#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull
#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull
#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull
#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull
#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull
#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull
#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull
#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR2_BASE 0x4554000ull
#define DCORE2_RTR2_MAX_OFFSET 0x1000
#define DCORE2_RTR2_SECTION 0x3000
#define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull
#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull
#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull
#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull
#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull
#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull
#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull
#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull
#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull
#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull
#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull
#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull
#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull
#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull
#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR2_SPECIAL_BASE 0x4554E80ull
#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull
#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull
#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR3_CTRL_BASE 0x4558000ull
#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR3_CTRL_SECTION 0xE800
#define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull
#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR3_H3_BASE 0x4559000ull
#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR3_H3_SECTION 0xE800
#define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull
#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull
#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull
#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull
#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull
#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull
#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull
#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull
#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull
#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull
#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull
#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull
#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull
#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull
#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull
#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR3_BASE 0x455C000ull
#define DCORE2_RTR3_MAX_OFFSET 0x1000
#define DCORE2_RTR3_SECTION 0x3000
#define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull
#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull
#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull
#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull
#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull
#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull
#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull
#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull
#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull
#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull
#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull
#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull
#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull
#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull
#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR3_SPECIAL_BASE 0x455CE80ull
#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull
#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull
#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR4_CTRL_BASE 0x4560000ull
#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR4_CTRL_SECTION 0xE800
#define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull
#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR4_H3_BASE 0x4561000ull
#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR4_H3_SECTION 0xE800
#define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull
#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull
#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull
#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull
#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull
#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull
#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull
#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull
#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull
#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull
#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull
#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull
#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull
#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull
#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull
#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR4_BASE 0x4564000ull
#define DCORE2_RTR4_MAX_OFFSET 0x1000
#define DCORE2_RTR4_SECTION 0x3000
#define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull
#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull
#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull
#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull
#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull
#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull
#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull
#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull
#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull
#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull
#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull
#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull
#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull
#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull
#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR4_SPECIAL_BASE 0x4564E80ull
#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull
#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull
#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR5_CTRL_BASE 0x4568000ull
#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR5_CTRL_SECTION 0xE800
#define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull
#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR5_H3_BASE 0x4569000ull
#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR5_H3_SECTION 0xE800
#define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull
#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull
#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull
#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull
#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull
#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull
#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull
#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull
#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull
#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull
#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull
#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull
#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull
#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull
#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull
#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR5_BASE 0x456C000ull
#define DCORE2_RTR5_MAX_OFFSET 0x1000
#define DCORE2_RTR5_SECTION 0x3000
#define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull
#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull
#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull
#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull
#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull
#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull
#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull
#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull
#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull
#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull
#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull
#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull
#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull
#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull
#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR5_SPECIAL_BASE 0x456CE80ull
#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull
#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull
#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR6_CTRL_BASE 0x4570000ull
#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR6_CTRL_SECTION 0xE800
#define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull
#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR6_H3_BASE 0x4571000ull
#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR6_H3_SECTION 0xE800
#define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull
#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull
#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull
#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull
#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull
#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull
#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull
#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull
#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull
#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull
#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull
#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull
#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull
#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull
#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull
#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR6_BASE 0x4574000ull
#define DCORE2_RTR6_MAX_OFFSET 0x1000
#define DCORE2_RTR6_SECTION 0x3000
#define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull
#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull
#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull
#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull
#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull
#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull
#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull
#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull
#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull
#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull
#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull
#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull
#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull
#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull
#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR6_SPECIAL_BASE 0x4574E80ull
#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull
#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull
#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_RTR7_CTRL_BASE 0x4578000ull
#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000
#define DCORE2_RTR7_CTRL_SECTION 0xE800
#define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull
#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR7_H3_BASE 0x4579000ull
#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000
#define DCORE2_RTR7_H3_SECTION 0xE800
#define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull
#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull
#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull
#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull
#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull
#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull
#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull
#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull
#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull
#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull
#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull
#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull
#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull
#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull
#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull
#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR7_BASE 0x457C000ull
#define DCORE2_RTR7_MAX_OFFSET 0x1000
#define DCORE2_RTR7_SECTION 0x3000
#define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull
#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull
#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull
#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull
#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull
#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull
#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull
#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull
#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull
#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000
#define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull
#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull
#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull
#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull
#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull
#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE2_RTR7_SPECIAL_BASE 0x457CE80ull
#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_SPECIAL_SECTION 0x1800
#define mmDCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull
#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800
#define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull
#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE2_SRAM0_BANK_BASE 0x4580000ull
#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM0_BANK_SECTION 0xE800
#define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull
#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM0_RTR_BASE 0x4581000ull
#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM0_RTR_SECTION 0xE800
#define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull
#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull
#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull
#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull
#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull
#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull
#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull
#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull
#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull
#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull
#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull
#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull
#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull
#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull
#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull
#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull
#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull
#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM1_BANK_BASE 0x4588000ull
#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM1_BANK_SECTION 0xE800
#define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull
#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM1_RTR_BASE 0x4589000ull
#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM1_RTR_SECTION 0xE800
#define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull
#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull
#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull
#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull
#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull
#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull
#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull
#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull
#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull
#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull
#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull
#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull
#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull
#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull
#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull
#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull
#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull
#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM2_BANK_BASE 0x4590000ull
#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM2_BANK_SECTION 0xE800
#define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull
#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM2_RTR_BASE 0x4591000ull
#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM2_RTR_SECTION 0xE800
#define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull
#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull
#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull
#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull
#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull
#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull
#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull
#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull
#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull
#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull
#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull
#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull
#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull
#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull
#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull
#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull
#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull
#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM3_BANK_BASE 0x4598000ull
#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM3_BANK_SECTION 0xE800
#define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull
#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM3_RTR_BASE 0x4599000ull
#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM3_RTR_SECTION 0xE800
#define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull
#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull
#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull
#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull
#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull
#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull
#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull
#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull
#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull
#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull
#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull
#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull
#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull
#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull
#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull
#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull
#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull
#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM4_BANK_BASE 0x45A0000ull
#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM4_BANK_SECTION 0xE800
#define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull
#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM4_RTR_BASE 0x45A1000ull
#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM4_RTR_SECTION 0xE800
#define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull
#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull
#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull
#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull
#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull
#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull
#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull
#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull
#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull
#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull
#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull
#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull
#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull
#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull
#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull
#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull
#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull
#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM5_BANK_BASE 0x45A8000ull
#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM5_BANK_SECTION 0xE800
#define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull
#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM5_RTR_BASE 0x45A9000ull
#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM5_RTR_SECTION 0xE800
#define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull
#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull
#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull
#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull
#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull
#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull
#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull
#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull
#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull
#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull
#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull
#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull
#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull
#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull
#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull
#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull
#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull
#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM6_BANK_BASE 0x45B0000ull
#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM6_BANK_SECTION 0xE800
#define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull
#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM6_RTR_BASE 0x45B1000ull
#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM6_RTR_SECTION 0xE800
#define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull
#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull
#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull
#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull
#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull
#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull
#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull
#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull
#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull
#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull
#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull
#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull
#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull
#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull
#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull
#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull
#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull
#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_SRAM7_BANK_BASE 0x45B8000ull
#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000
#define DCORE2_SRAM7_BANK_SECTION 0xE800
#define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull
#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM7_RTR_BASE 0x45B9000ull
#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000
#define DCORE2_SRAM7_RTR_SECTION 0xE800
#define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull
#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull
#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull
#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull
#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull
#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull
#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull
#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull
#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull
#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull
#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull
#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull
#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull
#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull
#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull
#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull
#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull
#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull
#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull
#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull
#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_EDMA0_QM_BASE 0x45CA000ull
#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_QM_SECTION 0x9000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull
#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull
#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull
#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull
#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull
#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000
#define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull
#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_EDMA0_CORE_BASE 0x45CB000ull
#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CORE_SECTION 0x8000
#define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull
#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull
#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00
#define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull
#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull
#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull
#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull
#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull
#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull
#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull
#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull
#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull
#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull
#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull
#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull
#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull
#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull
#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull
#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull
#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE2_EDMA1_QM_BASE 0x45DA000ull
#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_QM_SECTION 0x9000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull
#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull
#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull
#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull
#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull
#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000
#define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull
#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE2_EDMA1_CORE_BASE 0x45DB000ull
#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CORE_SECTION 0x8000
#define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull
#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull
#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00
#define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull
#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull
#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull
#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull
#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull
#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull
#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull
#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull
#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull
#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull
#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull
#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull
#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull
#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE2_DEC0_CMD_BASE 0x45E0000ull
#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100
#define DCORE2_DEC0_CMD_SECTION 0x1000
#define mmDCORE2_DEC0_VSI_BASE 0x45E1000ull
#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0
#define DCORE2_DEC0_VSI_SECTION 0x1000
#define mmDCORE2_DEC0_L2C_BASE 0x45E2000ull
#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0
#define DCORE2_DEC0_L2C_SECTION 0x1000
#define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull
#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000
#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull
#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_VDEC0_CTRL_BASE 0x45E4000ull
#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CTRL_SECTION 0xE800
#define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull
#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull
#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull
#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull
#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull
#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull
#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull
#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull
#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull
#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull
#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull
#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull
#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE2_DEC1_CMD_BASE 0x45F0000ull
#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100
#define DCORE2_DEC1_CMD_SECTION 0x1000
#define mmDCORE2_DEC1_VSI_BASE 0x45F1000ull
#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0
#define DCORE2_DEC1_VSI_SECTION 0x1000
#define mmDCORE2_DEC1_L2C_BASE 0x45F2000ull
#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0
#define DCORE2_DEC1_L2C_SECTION 0x1000
#define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull
#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000
#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull
#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_VDEC1_CTRL_BASE 0x45F4000ull
#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CTRL_SECTION 0xE800
#define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull
#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull
#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull
#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull
#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull
#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull
#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull
#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull
#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull
#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull
#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull
#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull
#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE3_TPC0_QM_DCCM_BASE 0x4600000ull
#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull
#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull
#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC0_QM_BASE 0x460A000ull
#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC0_QM_SECTION 0x9000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull
#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull
#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull
#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull
#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC0_QM_CGM_BASE 0x460AD80ull
#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC0_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull
#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_CFG_BASE 0x460B000ull
#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC0_CFG_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull
#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull
#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull
#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull
#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull
#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull
#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull
#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull
#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull
#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull
#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull
#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull
#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull
#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull
#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull
#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull
#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull
#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull
#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull
#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull
#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull
#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull
#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull
#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull
#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_TPC1_QM_DCCM_BASE 0x4610000ull
#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull
#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull
#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC1_QM_BASE 0x461A000ull
#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC1_QM_SECTION 0x9000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull
#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull
#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull
#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull
#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC1_QM_CGM_BASE 0x461AD80ull
#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC1_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull
#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_CFG_BASE 0x461B000ull
#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC1_CFG_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull
#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull
#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull
#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull
#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull
#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull
#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull
#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull
#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull
#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull
#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull
#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull
#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull
#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull
#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull
#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull
#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull
#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull
#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull
#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull
#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull
#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull
#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull
#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull
#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_TPC2_QM_DCCM_BASE 0x4620000ull
#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull
#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull
#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC2_QM_BASE 0x462A000ull
#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC2_QM_SECTION 0x9000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull
#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull
#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull
#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull
#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC2_QM_CGM_BASE 0x462AD80ull
#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC2_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull
#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_CFG_BASE 0x462B000ull
#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC2_CFG_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull
#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull
#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull
#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull
#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull
#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull
#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull
#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull
#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull
#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull
#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull
#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull
#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull
#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull
#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull
#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull
#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull
#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull
#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull
#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull
#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull
#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull
#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull
#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull
#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_TPC3_QM_DCCM_BASE 0x4630000ull
#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull
#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull
#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC3_QM_BASE 0x463A000ull
#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC3_QM_SECTION 0x9000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull
#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull
#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull
#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull
#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC3_QM_CGM_BASE 0x463AD80ull
#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC3_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull
#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_CFG_BASE 0x463B000ull
#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC3_CFG_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull
#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull
#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull
#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull
#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull
#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull
#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull
#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull
#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull
#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull
#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull
#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull
#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull
#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull
#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull
#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull
#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull
#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull
#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull
#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull
#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull
#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull
#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull
#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull
#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_TPC4_QM_DCCM_BASE 0x4640000ull
#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull
#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull
#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC4_QM_BASE 0x464A000ull
#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC4_QM_SECTION 0x9000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull
#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull
#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull
#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull
#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC4_QM_CGM_BASE 0x464AD80ull
#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC4_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull
#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_CFG_BASE 0x464B000ull
#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC4_CFG_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull
#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull
#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull
#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull
#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull
#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull
#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull
#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull
#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull
#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull
#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull
#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull
#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull
#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull
#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull
#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull
#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull
#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull
#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull
#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull
#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull
#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull
#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull
#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull
#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_TPC5_QM_DCCM_BASE 0x4650000ull
#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000
#define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull
#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull
#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_TPC5_QM_BASE 0x465A000ull
#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000
#define DCORE3_TPC5_QM_SECTION 0x9000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull
#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull
#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull
#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull
#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_TPC5_QM_CGM_BASE 0x465AD80ull
#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_TPC5_QM_CGM_SECTION 0x1000
#define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull
#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_CFG_BASE 0x465B000ull
#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000
#define DCORE3_TPC5_CFG_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull
#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull
#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400
#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400
#define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull
#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull
#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull
#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull
#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull
#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull
#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull
#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000
#define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull
#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000
#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000
#define mmDCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull
#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400
#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0
#define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull
#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull
#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull
#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull
#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull
#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull
#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull
#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull
#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull
#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull
#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull
#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull
#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull
#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180
#define mmDCORE3_HMMU0_MMU_BASE 0x4680000ull
#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_MMU_SECTION 0xE800
#define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull
#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU0_STLB_BASE 0x4681000ull
#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_STLB_SECTION 0xE800
#define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull
#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull
#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull
#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull
#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull
#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull
#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull
#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull
#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull
#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull
#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull
#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull
#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull
#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull
#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE3_HMMU1_MMU_BASE 0x4690000ull
#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_MMU_SECTION 0xE800
#define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull
#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU1_STLB_BASE 0x4691000ull
#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_STLB_SECTION 0xE800
#define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull
#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull
#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull
#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull
#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull
#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull
#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull
#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull
#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull
#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull
#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull
#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull
#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull
#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull
#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE3_HMMU2_MMU_BASE 0x46A0000ull
#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_MMU_SECTION 0xE800
#define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull
#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU2_STLB_BASE 0x46A1000ull
#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_STLB_SECTION 0xE800
#define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull
#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull
#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull
#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull
#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull
#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull
#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull
#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull
#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull
#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull
#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull
#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull
#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull
#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull
#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE3_HMMU3_MMU_BASE 0x46B0000ull
#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_MMU_SECTION 0xE800
#define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull
#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU3_STLB_BASE 0x46B1000ull
#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_STLB_SECTION 0xE800
#define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull
#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180
#define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull
#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800
#define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull
#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800
#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull
#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull
#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull
#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull
#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull
#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull
#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull
#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull
#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull
#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull
#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull
#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180
#define mmDCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull
#define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000
#define mmDCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull
#define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull
#define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull
#define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000
#define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000
#define mmDCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull
#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800
#define mmDCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull
#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_QM_BASE 0x46CA000ull
#define DCORE3_MME_QM_MAX_OFFSET 0x1000
#define DCORE3_MME_QM_SECTION 0x9000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull
#define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull
#define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull
#define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull
#define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_MME_QM_CGM_BASE 0x46CAD80ull
#define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_MME_QM_CGM_SECTION 0x1000
#define mmDCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull
#define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_CTRL_LO_BASE 0x46CB000ull
#define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_LO_SECTION 0x8000
#define mmDCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull
#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000
#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull
#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800
#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800
#define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull
#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800
#define mmDCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull
#define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull
#define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_BASE 0x46CC000ull
#define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_HI_SECTION 0x8000
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull
#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull
#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull
#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000
#define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800
#define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull
#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000
#define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000
#define mmDCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull
#define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_EU_BIST_BASE 0x46CD000ull
#define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000
#define DCORE3_MME_EU_BIST_SECTION 0xE800
#define mmDCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull
#define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull
#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull
#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull
#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull
#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull
#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull
#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull
#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull
#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull
#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull
#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull
#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull
#define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000
#define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800
#define mmDCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull
#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE0_BASE 0x46D0000ull
#define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_SECTION 0xE800
#define mmDCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull
#define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull
#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull
#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull
#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull
#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull
#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull
#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull
#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull
#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull
#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull
#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull
#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE3_MME_SBTE1_BASE 0x46D8000ull
#define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_SECTION 0xE800
#define mmDCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull
#define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull
#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull
#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull
#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull
#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull
#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull
#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull
#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull
#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull
#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull
#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull
#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE3_MME_SBTE2_BASE 0x46E0000ull
#define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_SECTION 0xE800
#define mmDCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull
#define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull
#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull
#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull
#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull
#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull
#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull
#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull
#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull
#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull
#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull
#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull
#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE3_MME_SBTE3_BASE 0x46E8000ull
#define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_SECTION 0xE800
#define mmDCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull
#define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull
#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull
#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull
#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull
#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull
#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull
#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull
#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull
#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull
#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull
#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull
#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE3_MME_SBTE4_BASE 0x46F0000ull
#define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_SECTION 0xE800
#define mmDCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull
#define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull
#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull
#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull
#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull
#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull
#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull
#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull
#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull
#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull
#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull
#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull
#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180
#define mmDCORE3_MME_ACC_BASE 0x46F8000ull
#define DCORE3_MME_ACC_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_SECTION 0xE800
#define mmDCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull
#define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull
#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull
#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull
#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull
#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull
#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull
#define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull
#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull
#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull
#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull
#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull
#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull
#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull
#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull
#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull
#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull
#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull
#define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull
#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull
#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull
#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull
#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull
#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180
#define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull
#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00
#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000
#define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull
#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000
#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800
#define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull
#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800
#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull
#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull
#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull
#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull
#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull
#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull
#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull
#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_HIF0_BASE 0x4720000ull
#define DCORE3_HIF0_MAX_OFFSET 0x1000
#define DCORE3_HIF0_SECTION 0xE800
#define mmDCORE3_HIF0_SPECIAL_BASE 0x4720E80ull
#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HIF0_SPECIAL_SECTION 0x3180
#define mmDCORE3_HIF1_BASE 0x4724000ull
#define DCORE3_HIF1_MAX_OFFSET 0x1000
#define DCORE3_HIF1_SECTION 0xE800
#define mmDCORE3_HIF1_SPECIAL_BASE 0x4724E80ull
#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HIF1_SPECIAL_SECTION 0x3180
#define mmDCORE3_HIF2_BASE 0x4728000ull
#define DCORE3_HIF2_MAX_OFFSET 0x1000
#define DCORE3_HIF2_SECTION 0xE800
#define mmDCORE3_HIF2_SPECIAL_BASE 0x4728E80ull
#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HIF2_SPECIAL_SECTION 0x3180
#define mmDCORE3_HIF3_BASE 0x472C000ull
#define DCORE3_HIF3_MAX_OFFSET 0x1000
#define DCORE3_HIF3_SECTION 0xE800
#define mmDCORE3_HIF3_SPECIAL_BASE 0x472CE80ull
#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HIF3_SPECIAL_SECTION 0x13180
#define mmDCORE3_RTR0_CTRL_BASE 0x4740000ull
#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR0_CTRL_SECTION 0xE800
#define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull
#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR0_H3_BASE 0x4741000ull
#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR0_H3_SECTION 0xE800
#define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull
#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull
#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull
#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull
#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull
#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull
#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull
#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull
#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull
#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull
#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull
#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull
#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull
#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull
#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull
#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR0_BASE 0x4744000ull
#define DCORE3_RTR0_MAX_OFFSET 0x1000
#define DCORE3_RTR0_SECTION 0x3000
#define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull
#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull
#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull
#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull
#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull
#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull
#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull
#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull
#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull
#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull
#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull
#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull
#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull
#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull
#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR0_SPECIAL_BASE 0x4744E80ull
#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull
#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull
#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR1_CTRL_BASE 0x4748000ull
#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR1_CTRL_SECTION 0xE800
#define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull
#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR1_H3_BASE 0x4749000ull
#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR1_H3_SECTION 0xE800
#define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull
#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull
#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull
#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull
#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull
#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull
#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull
#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull
#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull
#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull
#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull
#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull
#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull
#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull
#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull
#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR1_BASE 0x474C000ull
#define DCORE3_RTR1_MAX_OFFSET 0x1000
#define DCORE3_RTR1_SECTION 0x3000
#define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull
#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull
#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull
#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull
#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull
#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull
#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull
#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull
#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull
#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull
#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull
#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull
#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull
#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull
#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR1_SPECIAL_BASE 0x474CE80ull
#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull
#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull
#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR2_CTRL_BASE 0x4750000ull
#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR2_CTRL_SECTION 0xE800
#define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull
#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR2_H3_BASE 0x4751000ull
#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR2_H3_SECTION 0xE800
#define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull
#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull
#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull
#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull
#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull
#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull
#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull
#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull
#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull
#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull
#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull
#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull
#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull
#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull
#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull
#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR2_BASE 0x4754000ull
#define DCORE3_RTR2_MAX_OFFSET 0x1000
#define DCORE3_RTR2_SECTION 0x3000
#define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull
#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull
#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull
#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull
#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull
#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull
#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull
#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull
#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull
#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull
#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull
#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull
#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull
#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull
#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR2_SPECIAL_BASE 0x4754E80ull
#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull
#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull
#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR3_CTRL_BASE 0x4758000ull
#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR3_CTRL_SECTION 0xE800
#define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull
#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR3_H3_BASE 0x4759000ull
#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR3_H3_SECTION 0xE800
#define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull
#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull
#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull
#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull
#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull
#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull
#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull
#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull
#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull
#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull
#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull
#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull
#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull
#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull
#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull
#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR3_BASE 0x475C000ull
#define DCORE3_RTR3_MAX_OFFSET 0x1000
#define DCORE3_RTR3_SECTION 0x3000
#define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull
#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull
#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull
#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull
#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull
#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull
#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull
#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull
#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull
#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull
#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull
#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull
#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull
#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull
#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR3_SPECIAL_BASE 0x475CE80ull
#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull
#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull
#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR4_CTRL_BASE 0x4760000ull
#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR4_CTRL_SECTION 0xE800
#define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull
#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR4_H3_BASE 0x4761000ull
#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR4_H3_SECTION 0xE800
#define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull
#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull
#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull
#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull
#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull
#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull
#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull
#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull
#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull
#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull
#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull
#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull
#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull
#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull
#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull
#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR4_BASE 0x4764000ull
#define DCORE3_RTR4_MAX_OFFSET 0x1000
#define DCORE3_RTR4_SECTION 0x3000
#define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull
#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull
#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull
#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull
#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull
#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull
#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull
#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull
#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull
#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull
#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull
#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull
#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull
#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull
#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR4_SPECIAL_BASE 0x4764E80ull
#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull
#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull
#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR5_CTRL_BASE 0x4768000ull
#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR5_CTRL_SECTION 0xE800
#define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull
#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR5_H3_BASE 0x4769000ull
#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR5_H3_SECTION 0xE800
#define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull
#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull
#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull
#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull
#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull
#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull
#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull
#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull
#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull
#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull
#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull
#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull
#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull
#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull
#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull
#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR5_BASE 0x476C000ull
#define DCORE3_RTR5_MAX_OFFSET 0x1000
#define DCORE3_RTR5_SECTION 0x3000
#define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull
#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull
#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull
#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull
#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull
#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull
#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull
#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull
#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull
#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull
#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull
#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull
#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull
#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull
#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR5_SPECIAL_BASE 0x476CE80ull
#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull
#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull
#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR6_CTRL_BASE 0x4770000ull
#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR6_CTRL_SECTION 0xE800
#define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull
#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR6_H3_BASE 0x4771000ull
#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR6_H3_SECTION 0xE800
#define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull
#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull
#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull
#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull
#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull
#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull
#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull
#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull
#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull
#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull
#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull
#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull
#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull
#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull
#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull
#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR6_BASE 0x4774000ull
#define DCORE3_RTR6_MAX_OFFSET 0x1000
#define DCORE3_RTR6_SECTION 0x3000
#define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull
#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull
#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull
#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull
#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull
#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull
#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull
#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull
#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull
#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull
#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull
#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull
#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull
#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull
#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR6_SPECIAL_BASE 0x4774E80ull
#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull
#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull
#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_RTR7_CTRL_BASE 0x4778000ull
#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000
#define DCORE3_RTR7_CTRL_SECTION 0xE800
#define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull
#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR7_H3_BASE 0x4779000ull
#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000
#define DCORE3_RTR7_H3_SECTION 0xE800
#define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull
#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull
#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull
#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull
#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull
#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull
#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull
#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull
#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull
#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull
#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull
#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull
#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull
#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000
#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000
#define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull
#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600
#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800
#define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull
#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR7_BASE 0x477C000ull
#define DCORE3_RTR7_MAX_OFFSET 0x1000
#define DCORE3_RTR7_SECTION 0x3000
#define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull
#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull
#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull
#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull
#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull
#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull
#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull
#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull
#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull
#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000
#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000
#define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull
#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000
#define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull
#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000
#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000
#define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull
#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull
#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000
#define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull
#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000
#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800
#define mmDCORE3_RTR7_SPECIAL_BASE 0x477CE80ull
#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_SPECIAL_SECTION 0x1800
#define mmDCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull
#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000
#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800
#define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull
#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180
#define mmDCORE3_SRAM0_BANK_BASE 0x4780000ull
#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM0_BANK_SECTION 0xE800
#define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull
#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM0_RTR_BASE 0x4781000ull
#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM0_RTR_SECTION 0xE800
#define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull
#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull
#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull
#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull
#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull
#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull
#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull
#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull
#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull
#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull
#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull
#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull
#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull
#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull
#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull
#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull
#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull
#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM1_BANK_BASE 0x4788000ull
#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM1_BANK_SECTION 0xE800
#define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull
#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM1_RTR_BASE 0x4789000ull
#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM1_RTR_SECTION 0xE800
#define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull
#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull
#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull
#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull
#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull
#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull
#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull
#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull
#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull
#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull
#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull
#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull
#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull
#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull
#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull
#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull
#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull
#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM2_BANK_BASE 0x4790000ull
#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM2_BANK_SECTION 0xE800
#define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull
#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM2_RTR_BASE 0x4791000ull
#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM2_RTR_SECTION 0xE800
#define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull
#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull
#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull
#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull
#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull
#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull
#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull
#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull
#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull
#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull
#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull
#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull
#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull
#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull
#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull
#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull
#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull
#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM3_BANK_BASE 0x4798000ull
#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM3_BANK_SECTION 0xE800
#define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull
#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM3_RTR_BASE 0x4799000ull
#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM3_RTR_SECTION 0xE800
#define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull
#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull
#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull
#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull
#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull
#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull
#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull
#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull
#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull
#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull
#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull
#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull
#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull
#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull
#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull
#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull
#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull
#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM4_BANK_BASE 0x47A0000ull
#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM4_BANK_SECTION 0xE800
#define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull
#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM4_RTR_BASE 0x47A1000ull
#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM4_RTR_SECTION 0xE800
#define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull
#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull
#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull
#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull
#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull
#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull
#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull
#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull
#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull
#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull
#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull
#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull
#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull
#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull
#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull
#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull
#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull
#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM5_BANK_BASE 0x47A8000ull
#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM5_BANK_SECTION 0xE800
#define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull
#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM5_RTR_BASE 0x47A9000ull
#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM5_RTR_SECTION 0xE800
#define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull
#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull
#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull
#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull
#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull
#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull
#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull
#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull
#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull
#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull
#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull
#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull
#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull
#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull
#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull
#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull
#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull
#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM6_BANK_BASE 0x47B0000ull
#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM6_BANK_SECTION 0xE800
#define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull
#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM6_RTR_BASE 0x47B1000ull
#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM6_RTR_SECTION 0xE800
#define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull
#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull
#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull
#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull
#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull
#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull
#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull
#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull
#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull
#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull
#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull
#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull
#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull
#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull
#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull
#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull
#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull
#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_SRAM7_BANK_BASE 0x47B8000ull
#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000
#define DCORE3_SRAM7_BANK_SECTION 0xE800
#define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull
#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM7_RTR_BASE 0x47B9000ull
#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000
#define DCORE3_SRAM7_RTR_SECTION 0xE800
#define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull
#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800
#define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull
#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull
#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull
#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull
#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull
#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull
#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull
#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800
#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000
#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull
#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull
#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull
#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull
#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull
#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull
#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull
#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000
#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull
#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000
#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000
#define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull
#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180
#define mmDCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull
#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull
#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull
#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_EDMA0_QM_BASE 0x47CA000ull
#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_QM_SECTION 0x9000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull
#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull
#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull
#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull
#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull
#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000
#define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull
#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_EDMA0_CORE_BASE 0x47CB000ull
#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CORE_SECTION 0x8000
#define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull
#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull
#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00
#define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull
#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull
#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull
#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull
#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull
#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull
#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull
#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull
#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull
#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull
#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull
#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull
#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull
#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull
#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000
#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull
#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800
#define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull
#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmDCORE3_EDMA1_QM_BASE 0x47DA000ull
#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_QM_SECTION 0x9000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47DA940ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47DA948ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47DA950ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47DA958ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47DA960ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47DA968ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47DA970ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47DA978ull
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmDCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x47DAB00ull
#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x47DAB80ull
#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_DBG_HBW_BASE 0x47DAC00ull
#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000
#define mmDCORE3_EDMA1_QM_DBG_LBW_BASE 0x47DAC80ull
#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000
#define mmDCORE3_EDMA1_QM_CGM_BASE 0x47DAD80ull
#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000
#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000
#define mmDCORE3_EDMA1_QM_SPECIAL_BASE 0x47DAE80ull
#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800
#define mmDCORE3_EDMA1_CORE_BASE 0x47DB000ull
#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CORE_SECTION 0x8000
#define mmDCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x47DB800ull
#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000
#define mmDCORE3_EDMA1_CORE_CTX_BASE 0x47DB860ull
#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000
#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00
#define mmDCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x47DBE00ull
#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000
#define mmDCORE3_EDMA1_CORE_SPECIAL_BASE 0x47DBE80ull
#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800
#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x47DC000ull
#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x47DC200ull
#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x47DC400ull
#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x47DC600ull
#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x47DC800ull
#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x47DCA80ull
#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x47DCB00ull
#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x47DCB80ull
#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x47DCC00ull
#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x47DCD80ull
#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x47DCE80ull
#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmDCORE3_DEC0_CMD_BASE 0x47E0000ull
#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100
#define DCORE3_DEC0_CMD_SECTION 0x1000
#define mmDCORE3_DEC0_VSI_BASE 0x47E1000ull
#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0
#define DCORE3_DEC0_VSI_SECTION 0x1000
#define mmDCORE3_DEC0_L2C_BASE 0x47E2000ull
#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0
#define DCORE3_DEC0_L2C_SECTION 0x1000
#define mmDCORE3_VDEC0_BRDG_CTRL_BASE 0x47E3000ull
#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000
#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47E3800ull
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47E3900ull
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47E3A00ull
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47E3B00ull
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x47E3C00ull
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x47E3E80ull
#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_VDEC0_CTRL_BASE 0x47E4000ull
#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CTRL_SECTION 0xE800
#define mmDCORE3_VDEC0_CTRL_SPECIAL_BASE 0x47E4E80ull
#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x47E5000ull
#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x47E5200ull
#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x47E5400ull
#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x47E5600ull
#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x47E5800ull
#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x47E5A80ull
#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x47E5B00ull
#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x47E5B80ull
#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x47E5C00ull
#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x47E5D80ull
#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x47E5E80ull
#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmDCORE3_DEC1_CMD_BASE 0x47F0000ull
#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100
#define DCORE3_DEC1_CMD_SECTION 0x1000
#define mmDCORE3_DEC1_VSI_BASE 0x47F1000ull
#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0
#define DCORE3_DEC1_VSI_SECTION 0x1000
#define mmDCORE3_DEC1_L2C_BASE 0x47F2000ull
#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0
#define DCORE3_DEC1_L2C_SECTION 0x1000
#define mmDCORE3_VDEC1_BRDG_CTRL_BASE 0x47F3000ull
#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000
#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x47F3800ull
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x47F3900ull
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x47F3A00ull
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x47F3B00ull
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x47F3C00ull
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmDCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x47F3E80ull
#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_VDEC1_CTRL_BASE 0x47F4000ull
#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CTRL_SECTION 0xE800
#define mmDCORE3_VDEC1_CTRL_SPECIAL_BASE 0x47F4E80ull
#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800
#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x47F5000ull
#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x47F5200ull
#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x47F5400ull
#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x47F5600ull
#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmDCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x47F5800ull
#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmDCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x47F5A80ull
#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmDCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x47F5B00ull
#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmDCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x47F5B80ull
#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmDCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x47F5C00ull
#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmDCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x47F5D80ull
#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmDCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x47F5E80ull
#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmGIC_BASE 0x4800000ull
#define GIC_MAX_OFFSET 0x10000
#define GIC_SECTION 0x401000
#define mmPCIE_WRAP_BASE 0x4C01000ull
#define PCIE_WRAP_MAX_OFFSET 0x1000
#define PCIE_WRAP_SECTION 0xE800
#define mmPCIE_WRAP_SPECIAL_BASE 0x4C01E80ull
#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_WRAP_SPECIAL_SECTION 0x1800
#define mmPCIE_DBI_BASE 0x4C02000ull
#define PCIE_DBI_MAX_OFFSET 0xC040
#define PCIE_DBI_SECTION 0x2000
#define mmPCIE_CORE_BASE 0x4C04000ull
#define PCIE_CORE_MAX_OFFSET 0x1000
#define PCIE_CORE_SECTION 0xE800
#define mmPCIE_CORE_SPECIAL_BASE 0x4C04E80ull
#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_CORE_SPECIAL_SECTION 0x2180
#define mmPCIE_AUX_BASE 0x4C07000ull
#define PCIE_AUX_MAX_OFFSET 0x1000
#define PCIE_AUX_SECTION 0xE800
#define mmPCIE_AUX_SPECIAL_BASE 0x4C07E80ull
#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_AUX_SPECIAL_SECTION 0x8180
#define mmPCIE_PHY_BASE 0x4C10000ull
#define PCIE_PHY_MAX_OFFSET 0x1000
#define PCIE_PHY_SECTION 0xE800
#define mmPCIE_PHY_SPECIAL_BASE 0x4C10E80ull
#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_PHY_SPECIAL_SECTION 0x2180
#define mmPCIE_MSI_BASE 0x4C13000ull
#define PCIE_MSI_MAX_OFFSET 0x8000
#define PCIE_MSI_SECTION 0x1000
#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C14000ull
#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C14200ull
#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C14400ull
#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C14600ull
#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x4C14800ull
#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x4C14A80ull
#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x4C14B00ull
#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x4C14B80ull
#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x4C14C00ull
#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x4C14D80ull
#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x4C14E80ull
#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C15000ull
#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C15200ull
#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C15400ull
#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C15600ull
#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x4C15800ull
#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x4C15A80ull
#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x4C15B00ull
#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x4C15B80ull
#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x4C15C00ull
#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x4C15D80ull
#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x4C15E80ull
#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x4C16000ull
#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x4C16200ull
#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x4C16400ull
#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x4C16600ull
#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x4C16800ull
#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x4C16A80ull
#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x4C16B00ull
#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x4C16B80ull
#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x4C16C00ull
#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x4C16D80ull
#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x4C16E80ull
#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPCIE_MSIX_BASE 0x4C17000ull
#define PCIE_MSIX_MAX_OFFSET 0x4000
#define PCIE_MSIX_SECTION 0x29000
#define mmPSOC_I2C_M0_BASE 0x4C40000ull
#define PSOC_I2C_M0_MAX_OFFSET 0x1000
#define PSOC_I2C_M0_SECTION 0x1000
#define mmPSOC_I2C_M1_BASE 0x4C41000ull
#define PSOC_I2C_M1_MAX_OFFSET 0x1000
#define PSOC_I2C_M1_SECTION 0x1000
#define mmPSOC_I2C_S_BASE 0x4C42000ull
#define PSOC_I2C_S_MAX_OFFSET 0x1000
#define PSOC_I2C_S_SECTION 0x1000
#define mmPSOC_SPI_BASE 0x4C43000ull
#define PSOC_SPI_MAX_OFFSET 0x1000
#define PSOC_SPI_SECTION 0x1000
#define mmPSOC_QSPI_BASE 0x4C44000ull
#define PSOC_QSPI_MAX_OFFSET 0x1000
#define PSOC_QSPI_SECTION 0x1000
#define mmPSOC_UART_0_BASE 0x4C45000ull
#define PSOC_UART_0_MAX_OFFSET 0x1000
#define PSOC_UART_0_SECTION 0x1000
#define mmPSOC_UART_1_BASE 0x4C46000ull
#define PSOC_UART_1_MAX_OFFSET 0x1000
#define PSOC_UART_1_SECTION 0x1000
#define mmPSOC_TIMER_BASE 0x4C47000ull
#define PSOC_TIMER_MAX_OFFSET 0x1000
#define PSOC_TIMER_SECTION 0x1000
#define mmPSOC_WDOG_BASE 0x4C48000ull
#define PSOC_WDOG_MAX_OFFSET 0x1000
#define PSOC_WDOG_SECTION 0x1000
#define mmPSOC_TIMESTAMP_BASE 0x4C49000ull
#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000
#define PSOC_TIMESTAMP_SECTION 0x1000
#define mmPSOC_EFUSE_BASE 0x4C4A000ull
#define PSOC_EFUSE_MAX_OFFSET 0x1000
#define PSOC_EFUSE_SECTION 0xE800
#define mmPSOC_EFUSE_SPECIAL_BASE 0x4C4AE80ull
#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_EFUSE_SPECIAL_SECTION 0x1800
#define mmPSOC_GLOBAL_CONF_BASE 0x4C4B000ull
#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000
#define PSOC_GLOBAL_CONF_SECTION 0xE800
#define mmPSOC_GLOBAL_CONF_SPECIAL_BASE 0x4C4BE80ull
#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800
#define mmPSOC_GPIO0_BASE 0x4C4C000ull
#define PSOC_GPIO0_MAX_OFFSET 0x1000
#define PSOC_GPIO0_SECTION 0x1000
#define mmPSOC_GPIO1_BASE 0x4C4D000ull
#define PSOC_GPIO1_MAX_OFFSET 0x1000
#define PSOC_GPIO1_SECTION 0x1000
#define mmPSOC_BTL_BASE 0x4C4E000ull
#define PSOC_BTL_MAX_OFFSET 0x1000
#define PSOC_BTL_SECTION 0xE800
#define mmPSOC_BTL_SPECIAL_BASE 0x4C4EE80ull
#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_BTL_SPECIAL_SECTION 0x1800
#define mmPSOC_CS_TRACE_BASE 0x4C4F000ull
#define PSOC_CS_TRACE_MAX_OFFSET 0x1000
#define PSOC_CS_TRACE_SECTION 0xE800
#define mmPSOC_CS_TRACE_SPECIAL_BASE 0x4C4FE80ull
#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800
#define mmPSOC_GPIO2_BASE 0x4C50000ull
#define PSOC_GPIO2_MAX_OFFSET 0x1000
#define PSOC_GPIO2_SECTION 0x1000
#define mmPSOC_GPIO3_BASE 0x4C51000ull
#define PSOC_GPIO3_MAX_OFFSET 0x1000
#define PSOC_GPIO3_SECTION 0x2000
#define mmPSOC_DFT_EFUSE_BASE 0x4C53000ull
#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000
#define PSOC_DFT_EFUSE_SECTION 0xE800
#define mmPSOC_DFT_EFUSE_SPECIAL_BASE 0x4C53E80ull
#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800
#define mmPSOC_RPM_0_BASE 0x4C54000ull
#define PSOC_RPM_0_MAX_OFFSET 0x1000
#define PSOC_RPM_0_SECTION 0xE800
#define mmPSOC_RPM_0_SPECIAL_BASE 0x4C54E80ull
#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_RPM_0_SPECIAL_SECTION 0x1800
#define mmPSOC_RPM_1_BASE 0x4C55000ull
#define PSOC_RPM_1_MAX_OFFSET 0x1000
#define PSOC_RPM_1_SECTION 0xE800
#define mmPSOC_RPM_1_SPECIAL_BASE 0x4C55E80ull
#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_RPM_1_SPECIAL_SECTION 0x1800
#define mmPSOC_GPIO4_BASE 0x4C56000ull
#define PSOC_GPIO4_MAX_OFFSET 0x1000
#define PSOC_GPIO4_SECTION 0x1000
#define mmPSOC_GPIO5_BASE 0x4C57000ull
#define PSOC_GPIO5_MAX_OFFSET 0x1000
#define PSOC_GPIO5_SECTION 0x1000
#define mmPSOC_PID_BASE 0x4C58000ull
#define PSOC_PID_MAX_OFFSET 0x1000
#define PSOC_PID_SECTION 0xE800
#define mmPSOC_PID_SPECIAL_BASE 0x4C58E80ull
#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_PID_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC0_CFG_BASE 0x4C59000ull
#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000
#define PSOC_ARC0_CFG_SECTION 0xE800
#define mmPSOC_ARC0_CFG_SPECIAL_BASE 0x4C59E80ull
#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5A000ull
#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5A200ull
#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5A400ull
#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5A600ull
#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x4C5A800ull
#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPSOC_ARC0_MSTR_IF_AXUSER_BASE 0x4C5AA80ull
#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x4C5AB00ull
#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x4C5AB80ull
#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x4C5AC00ull
#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x4C5AD80ull
#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x4C5AE80ull
#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC0_AUX_BASE 0x4C5B000ull
#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000
#define PSOC_ARC0_AUX_SECTION 0xE800
#define mmPSOC_ARC0_AUX_SPECIAL_BASE 0x4C5BE80ull
#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC1_CFG_BASE 0x4C5C000ull
#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000
#define PSOC_ARC1_CFG_SECTION 0xE800
#define mmPSOC_ARC1_CFG_SPECIAL_BASE 0x4C5CE80ull
#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C5D000ull
#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C5D200ull
#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C5D400ull
#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C5D600ull
#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x4C5D800ull
#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPSOC_ARC1_MSTR_IF_AXUSER_BASE 0x4C5DA80ull
#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x4C5DB00ull
#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x4C5DB80ull
#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x4C5DC00ull
#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x4C5DD80ull
#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x4C5DE80ull
#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPSOC_ARC1_AUX_BASE 0x4C5E000ull
#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000
#define PSOC_ARC1_AUX_SECTION 0xE800
#define mmPSOC_ARC1_AUX_SPECIAL_BASE 0x4C5EE80ull
#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180
#define mmPSOC_SECURITY_BASE 0x4C60000ull
#define PSOC_SECURITY_MAX_OFFSET 0x1000
#define PSOC_SECURITY_SECTION 0xE800
#define mmPSOC_SECURITY_SPECIAL_BASE 0x4C60E80ull
#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_SECURITY_SPECIAL_SECTION 0x1800
#define mmJT_MSTR_IF_RR_SHRD_HBW_BASE 0x4C61000ull
#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmJT_MSTR_IF_RR_PRVT_HBW_BASE 0x4C61200ull
#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmJT_MSTR_IF_RR_SHRD_LBW_BASE 0x4C61400ull
#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmJT_MSTR_IF_RR_PRVT_LBW_BASE 0x4C61600ull
#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmJT_MSTR_IF_E2E_CRDT_BASE 0x4C61800ull
#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmJT_MSTR_IF_AXUSER_BASE 0x4C61A80ull
#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define JT_MSTR_IF_AXUSER_SECTION 0x8000
#define mmJT_MSTR_IF_DBG_HBW_BASE 0x4C61B00ull
#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmJT_MSTR_IF_DBG_LBW_BASE 0x4C61B80ull
#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmJT_MSTR_IF_CORE_HBW_BASE 0x4C61C00ull
#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmJT_MSTR_IF_CORE_LBW_BASE 0x4C61D80ull
#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmJT_MSTR_IF_SPECIAL_BASE 0x4C61E80ull
#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define JT_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSMI_MSTR_IF_RR_SHRD_HBW_BASE 0x4C62000ull
#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSMI_MSTR_IF_RR_PRVT_HBW_BASE 0x4C62200ull
#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSMI_MSTR_IF_RR_SHRD_LBW_BASE 0x4C62400ull
#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSMI_MSTR_IF_RR_PRVT_LBW_BASE 0x4C62600ull
#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSMI_MSTR_IF_E2E_CRDT_BASE 0x4C62800ull
#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSMI_MSTR_IF_AXUSER_BASE 0x4C62A80ull
#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SMI_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSMI_MSTR_IF_DBG_HBW_BASE 0x4C62B00ull
#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSMI_MSTR_IF_DBG_LBW_BASE 0x4C62B80ull
#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSMI_MSTR_IF_CORE_HBW_BASE 0x4C62C00ull
#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSMI_MSTR_IF_CORE_LBW_BASE 0x4C62D80ull
#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSMI_MSTR_IF_SPECIAL_BASE 0x4C62E80ull
#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x4C63000ull
#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmI2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x4C63200ull
#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmI2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x4C63400ull
#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmI2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x4C63600ull
#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmI2C_S_MSTR_IF_E2E_CRDT_BASE 0x4C63800ull
#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmI2C_S_MSTR_IF_AXUSER_BASE 0x4C63A80ull
#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000
#define mmI2C_S_MSTR_IF_DBG_HBW_BASE 0x4C63B00ull
#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmI2C_S_MSTR_IF_DBG_LBW_BASE 0x4C63B80ull
#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmI2C_S_MSTR_IF_CORE_HBW_BASE 0x4C63C00ull
#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmI2C_S_MSTR_IF_CORE_LBW_BASE 0x4C63D80ull
#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmI2C_S_MSTR_IF_SPECIAL_BASE 0x4C63E80ull
#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPSOC_SVID0_BASE 0x4C64000ull
#define PSOC_SVID0_MAX_OFFSET 0x1000
#define PSOC_SVID0_SECTION 0xE800
#define mmPSOC_SVID0_SPECIAL_BASE 0x4C64E80ull
#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_SVID0_SPECIAL_SECTION 0x1800
#define mmPSOC_SVID1_BASE 0x4C65000ull
#define PSOC_SVID1_MAX_OFFSET 0x1000
#define PSOC_SVID1_SECTION 0xE800
#define mmPSOC_SVID1_SPECIAL_BASE 0x4C65E80ull
#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_SVID1_SPECIAL_SECTION 0x1800
#define mmPSOC_SVID2_BASE 0x4C66000ull
#define PSOC_SVID2_MAX_OFFSET 0x1000
#define PSOC_SVID2_SECTION 0xE800
#define mmPSOC_SVID2_SPECIAL_BASE 0x4C66E80ull
#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_SVID2_SPECIAL_SECTION 0x5180
#define mmPSOC_MME_PLL_CTRL_BASE 0x4C6C000ull
#define PSOC_MME_PLL_CTRL_MAX_OFFSET 0x3540
#define PSOC_MME_PLL_CTRL_SECTION 0x3600
#define mmPSOC_MME_PLL_ASIF_SLV_BASE 0x4C6C360ull
#define PSOC_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define PSOC_MME_PLL_ASIF_SLV_SECTION 0xA000
#define mmPSOC_MME_PLL_DIV_0_RLX_BASE 0x4C6C400ull
#define PSOC_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define PSOC_MME_PLL_DIV_0_RLX_SECTION 0x4000
#define mmPSOC_MME_PLL_DIV_1_RLX_BASE 0x4C6C800ull
#define PSOC_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define PSOC_MME_PLL_DIV_1_RLX_SECTION 0x2000
#define mmPSOC_MME_PLL_DIV_2_RLX_BASE 0x4C6CA00ull
#define PSOC_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define PSOC_MME_PLL_DIV_2_RLX_SECTION 0x2000
#define mmPSOC_MME_PLL_DIV_3_RLX_BASE 0x4C6CC00ull
#define PSOC_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define PSOC_MME_PLL_DIV_3_RLX_SECTION 0x2800
#define mmPSOC_MME_PLL_SPECIAL_BASE 0x4C6CE80ull
#define PSOC_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_MME_PLL_SPECIAL_SECTION 0x1800
#define mmPSOC_CPU_PLL_CTRL_BASE 0x4C6D000ull
#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540
#define PSOC_CPU_PLL_CTRL_SECTION 0x3600
#define mmPSOC_CPU_PLL_ASIF_SLV_BASE 0x4C6D360ull
#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000
#define mmPSOC_CPU_PLL_DIV_0_RLX_BASE 0x4C6D400ull
#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000
#define mmPSOC_CPU_PLL_DIV_1_RLX_BASE 0x4C6D800ull
#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000
#define mmPSOC_CPU_PLL_DIV_2_RLX_BASE 0x4C6DA00ull
#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000
#define mmPSOC_CPU_PLL_DIV_3_RLX_BASE 0x4C6DC00ull
#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800
#define mmPSOC_CPU_PLL_SPECIAL_BASE 0x4C6DE80ull
#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800
#define mmPSOC_VID_PLL_CTRL_BASE 0x4C6E000ull
#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540
#define PSOC_VID_PLL_CTRL_SECTION 0x3600
#define mmPSOC_VID_PLL_ASIF_SLV_BASE 0x4C6E360ull
#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000
#define mmPSOC_VID_PLL_DIV_0_RLX_BASE 0x4C6E400ull
#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000
#define mmPSOC_VID_PLL_DIV_1_RLX_BASE 0x4C6E800ull
#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000
#define mmPSOC_VID_PLL_DIV_2_RLX_BASE 0x4C6EA00ull
#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000
#define mmPSOC_VID_PLL_DIV_3_RLX_BASE 0x4C6EC00ull
#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800
#define mmPSOC_VID_PLL_SPECIAL_BASE 0x4C6EE80ull
#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180
#define mmPSOC_RESET_CONF_BASE 0x4C74000ull
#define PSOC_RESET_CONF_MAX_OFFSET 0x1000
#define PSOC_RESET_CONF_SECTION 0xE800
#define mmPSOC_RESET_CONF_SPECIAL_BASE 0x4C74E80ull
#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800
#define mmPSOC_DFT_APB_BASE 0x4C75000ull
#define PSOC_DFT_APB_MAX_OFFSET 0x8000
#define PSOC_DFT_APB_SECTION 0x1000
#define mmPSOC_AVS0_BASE 0x4C76000ull
#define PSOC_AVS0_MAX_OFFSET 0x1000
#define PSOC_AVS0_SECTION 0xE800
#define mmPSOC_AVS0_SPECIAL_BASE 0x4C76E80ull
#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_AVS0_SPECIAL_SECTION 0x1800
#define mmPSOC_AVS1_BASE 0x4C77000ull
#define PSOC_AVS1_MAX_OFFSET 0x1000
#define PSOC_AVS1_SECTION 0xE800
#define mmPSOC_AVS1_SPECIAL_BASE 0x4C77E80ull
#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_AVS1_SPECIAL_SECTION 0x1800
#define mmPSOC_AVS2_BASE 0x4C78000ull
#define PSOC_AVS2_MAX_OFFSET 0x1000
#define PSOC_AVS2_SECTION 0xE800
#define mmPSOC_AVS2_SPECIAL_BASE 0x4C78E80ull
#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_AVS2_SPECIAL_SECTION 0x1800
#define mmPSOC_PWM0_BASE 0x4C79000ull
#define PSOC_PWM0_MAX_OFFSET 0x1000
#define PSOC_PWM0_SECTION 0xE800
#define mmPSOC_PWM0_SPECIAL_BASE 0x4C79E80ull
#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_PWM0_SPECIAL_SECTION 0x1800
#define mmPSOC_PWM1_BASE 0x4C7A000ull
#define PSOC_PWM1_MAX_OFFSET 0x1000
#define PSOC_PWM1_SECTION 0xE800
#define mmPSOC_PWM1_SPECIAL_BASE 0x4C7AE80ull
#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_PWM1_SPECIAL_SECTION 0x1800
#define mmSVID0_AC_BASE 0x4C7B000ull
#define SVID0_AC_MAX_OFFSET 0x1000
#define SVID0_AC_SECTION 0xE800
#define mmSVID0_AC_SPECIAL_BASE 0x4C7BE80ull
#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800
#define SVID0_AC_SPECIAL_SECTION 0x1800
#define mmSVID1_AC_BASE 0x4C7C000ull
#define SVID1_AC_MAX_OFFSET 0x1000
#define SVID1_AC_SECTION 0xE800
#define mmSVID1_AC_SPECIAL_BASE 0x4C7CE80ull
#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800
#define SVID1_AC_SPECIAL_SECTION 0x1800
#define mmSVID2_AC_BASE 0x4C7D000ull
#define SVID2_AC_MAX_OFFSET 0x1000
#define SVID2_AC_SECTION 0xE800
#define mmSVID2_AC_SPECIAL_BASE 0x4C7DE80ull
#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800
#define SVID2_AC_SPECIAL_SECTION 0x1180
#define mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x4C7F000ull
#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x4C7F200ull
#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x4C7F400ull
#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x4C7F600ull
#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPSOC_MSTR_IF_E2E_CRDT_BASE 0x4C7F800ull
#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPSOC_MSTR_IF_AXUSER_BASE 0x4C7FA80ull
#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPSOC_MSTR_IF_DBG_HBW_BASE 0x4C7FB00ull
#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPSOC_MSTR_IF_DBG_LBW_BASE 0x4C7FB80ull
#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPSOC_MSTR_IF_CORE_HBW_BASE 0x4C7FC00ull
#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPSOC_MSTR_IF_CORE_LBW_BASE 0x4C7FD80ull
#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPSOC_MSTR_IF_SPECIAL_BASE 0x4C7FE80ull
#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPDMA0_QM_ARC_DCCM_BASE 0x4C80000ull
#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define PDMA0_QM_ARC_DCCM_SECTION 0x8000
#define mmPDMA0_QM_ARC_AUX_BASE 0x4C88000ull
#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define PDMA0_QM_ARC_AUX_SECTION 0xE800
#define mmPDMA0_QM_ARC_AUX_SPECIAL_BASE 0x4C88E80ull
#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmPDMA0_QM_BASE 0x4C8A000ull
#define PDMA0_QM_MAX_OFFSET 0x1000
#define PDMA0_QM_SECTION 0x9000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C8A900ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C8A908ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C8A910ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C8A918ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C8A920ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C8A928ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C8A930ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C8A938ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C8A940ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C8A948ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C8A950ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C8A958ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C8A960ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C8A968ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C8A970ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C8A978ull
#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmPDMA0_QM_AXUSER_SECURED_BASE 0x4C8AB00ull
#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmPDMA0_QM_AXUSER_NONSECURED_BASE 0x4C8AB80ull
#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmPDMA0_QM_DBG_HBW_BASE 0x4C8AC00ull
#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define PDMA0_QM_DBG_HBW_SECTION 0x8000
#define mmPDMA0_QM_DBG_LBW_BASE 0x4C8AC80ull
#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define PDMA0_QM_DBG_LBW_SECTION 0x1000
#define mmPDMA0_QM_CGM_BASE 0x4C8AD80ull
#define PDMA0_QM_CGM_MAX_OFFSET 0xC000
#define PDMA0_QM_CGM_SECTION 0x1000
#define mmPDMA0_QM_SPECIAL_BASE 0x4C8AE80ull
#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800
#define PDMA0_QM_SPECIAL_SECTION 0x1800
#define mmPDMA0_CORE_BASE 0x4C8B000ull
#define PDMA0_CORE_MAX_OFFSET 0x1000
#define PDMA0_CORE_SECTION 0x8000
#define mmPDMA0_CORE_CTX_AXUSER_BASE 0x4C8B800ull
#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000
#define mmPDMA0_CORE_CTX_BASE 0x4C8B860ull
#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000
#define PDMA0_CORE_CTX_SECTION 0x5A00
#define mmPDMA0_CORE_KDMA_CGM_BASE 0x4C8BE00ull
#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000
#define mmPDMA0_CORE_SPECIAL_BASE 0x4C8BE80ull
#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PDMA0_CORE_SPECIAL_SECTION 0x1800
#define mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x4C8C000ull
#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x4C8C200ull
#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x4C8C400ull
#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x4C8C600ull
#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPDMA0_MSTR_IF_E2E_CRDT_BASE 0x4C8C800ull
#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPDMA0_MSTR_IF_AXUSER_BASE 0x4C8CA80ull
#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPDMA0_MSTR_IF_DBG_HBW_BASE 0x4C8CB00ull
#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPDMA0_MSTR_IF_DBG_LBW_BASE 0x4C8CB80ull
#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPDMA0_MSTR_IF_CORE_HBW_BASE 0x4C8CC00ull
#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPDMA0_MSTR_IF_CORE_LBW_BASE 0x4C8CD80ull
#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPDMA0_MSTR_IF_SPECIAL_BASE 0x4C8CE80ull
#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmPDMA1_QM_ARC_DCCM_BASE 0x4C90000ull
#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define PDMA1_QM_ARC_DCCM_SECTION 0x8000
#define mmPDMA1_QM_ARC_AUX_BASE 0x4C98000ull
#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define PDMA1_QM_ARC_AUX_SECTION 0xE800
#define mmPDMA1_QM_ARC_AUX_SPECIAL_BASE 0x4C98E80ull
#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmPDMA1_QM_BASE 0x4C9A000ull
#define PDMA1_QM_MAX_OFFSET 0x1000
#define PDMA1_QM_SECTION 0x9000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C9A900ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C9A908ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C9A910ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C9A918ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C9A920ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C9A928ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C9A930ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C9A938ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C9A940ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C9A948ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C9A950ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C9A958ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C9A960ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C9A968ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C9A970ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C9A978ull
#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmPDMA1_QM_AXUSER_SECURED_BASE 0x4C9AB00ull
#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmPDMA1_QM_AXUSER_NONSECURED_BASE 0x4C9AB80ull
#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmPDMA1_QM_DBG_HBW_BASE 0x4C9AC00ull
#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define PDMA1_QM_DBG_HBW_SECTION 0x8000
#define mmPDMA1_QM_DBG_LBW_BASE 0x4C9AC80ull
#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define PDMA1_QM_DBG_LBW_SECTION 0x1000
#define mmPDMA1_QM_CGM_BASE 0x4C9AD80ull
#define PDMA1_QM_CGM_MAX_OFFSET 0xC000
#define PDMA1_QM_CGM_SECTION 0x1000
#define mmPDMA1_QM_SPECIAL_BASE 0x4C9AE80ull
#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800
#define PDMA1_QM_SPECIAL_SECTION 0x1800
#define mmPDMA1_CORE_BASE 0x4C9B000ull
#define PDMA1_CORE_MAX_OFFSET 0x1000
#define PDMA1_CORE_SECTION 0x8000
#define mmPDMA1_CORE_CTX_AXUSER_BASE 0x4C9B800ull
#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000
#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000
#define mmPDMA1_CORE_CTX_BASE 0x4C9B860ull
#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000
#define PDMA1_CORE_CTX_SECTION 0x5A00
#define mmPDMA1_CORE_KDMA_CGM_BASE 0x4C9BE00ull
#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000
#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000
#define mmPDMA1_CORE_SPECIAL_BASE 0x4C9BE80ull
#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PDMA1_CORE_SPECIAL_SECTION 0x1800
#define mmPDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x4C9C000ull
#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x4C9C200ull
#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x4C9C400ull
#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x4C9C600ull
#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPDMA1_MSTR_IF_E2E_CRDT_BASE 0x4C9C800ull
#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPDMA1_MSTR_IF_AXUSER_BASE 0x4C9CA80ull
#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPDMA1_MSTR_IF_DBG_HBW_BASE 0x4C9CB00ull
#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPDMA1_MSTR_IF_DBG_LBW_BASE 0x4C9CB80ull
#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPDMA1_MSTR_IF_CORE_HBW_BASE 0x4C9CC00ull
#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPDMA1_MSTR_IF_CORE_LBW_BASE 0x4C9CD80ull
#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPDMA1_MSTR_IF_SPECIAL_BASE 0x4C9CE80ull
#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180
#define mmCPU_CA53_CFG_BASE 0x4CC0000ull
#define CPU_CA53_CFG_MAX_OFFSET 0x1000
#define CPU_CA53_CFG_SECTION 0xE800
#define mmCPU_CA53_CFG_SPECIAL_BASE 0x4CC0E80ull
#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800
#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800
#define mmCPU_IF_BASE 0x4CC1000ull
#define CPU_IF_MAX_OFFSET 0x1000
#define CPU_IF_SECTION 0xE800
#define mmCPU_IF_SPECIAL_BASE 0x4CC1E80ull
#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800
#define CPU_IF_SPECIAL_SECTION 0x1800
#define mmCPU_TIMESTAMP_BASE 0x4CC2000ull
#define CPU_TIMESTAMP_MAX_OFFSET 0x1000
#define CPU_TIMESTAMP_SECTION 0x1000
#define mmCPU_MSTR_IF_RR_SHRD_HBW_BASE 0x4CC3000ull
#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmCPU_MSTR_IF_RR_PRVT_HBW_BASE 0x4CC3200ull
#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmCPU_MSTR_IF_RR_SHRD_LBW_BASE 0x4CC3400ull
#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmCPU_MSTR_IF_RR_PRVT_LBW_BASE 0x4CC3600ull
#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmCPU_MSTR_IF_E2E_CRDT_BASE 0x4CC3800ull
#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmCPU_MSTR_IF_AXUSER_BASE 0x4CC3A80ull
#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define CPU_MSTR_IF_AXUSER_SECTION 0x8000
#define mmCPU_MSTR_IF_DBG_HBW_BASE 0x4CC3B00ull
#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmCPU_MSTR_IF_DBG_LBW_BASE 0x4CC3B80ull
#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmCPU_MSTR_IF_CORE_HBW_BASE 0x4CC3C00ull
#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmCPU_MSTR_IF_CORE_LBW_BASE 0x4CC3D80ull
#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmCPU_MSTR_IF_SPECIAL_BASE 0x4CC3E80ull
#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180
#define mmPMMU_HBW_MMU_BASE 0x4D00000ull
#define PMMU_HBW_MMU_MAX_OFFSET 0x1000
#define PMMU_HBW_MMU_SECTION 0xE800
#define mmPMMU_HBW_MMU_SPECIAL_BASE 0x4D00E80ull
#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800
#define mmPMMU_HBW_STLB_BASE 0x4D01000ull
#define PMMU_HBW_STLB_MAX_OFFSET 0x1000
#define PMMU_HBW_STLB_SECTION 0xE800
#define mmPMMU_HBW_STLB_SPECIAL_BASE 0x4D01E80ull
#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800
#define mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x4D02000ull
#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x4D02200ull
#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x4D02400ull
#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x4D02600ull
#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x4D02800ull
#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPMMU_HBW_MSTR_IF_AXUSER_BASE 0x4D02A80ull
#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x4D02B00ull
#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x4D02B80ull
#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x4D02C00ull
#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x4D02D80ull
#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPMMU_HBW_MSTR_IF_SPECIAL_BASE 0x4D02E80ull
#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmPMMU_PIF_BASE 0x4D03000ull
#define PMMU_PIF_MAX_OFFSET 0x1000
#define PMMU_PIF_SECTION 0xE800
#define mmPMMU_PIF_SPECIAL_BASE 0x4D03E80ull
#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_PIF_SPECIAL_SECTION 0x1800
#define mmPMMU_MME_PLL_CTRL_BASE 0x4D04000ull
#define PMMU_MME_PLL_CTRL_MAX_OFFSET 0x3540
#define PMMU_MME_PLL_CTRL_SECTION 0x3600
#define mmPMMU_MME_PLL_ASIF_SLV_BASE 0x4D04360ull
#define PMMU_MME_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define PMMU_MME_PLL_ASIF_SLV_SECTION 0xA000
#define mmPMMU_MME_PLL_DIV_0_RLX_BASE 0x4D04400ull
#define PMMU_MME_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define PMMU_MME_PLL_DIV_0_RLX_SECTION 0x4000
#define mmPMMU_MME_PLL_DIV_1_RLX_BASE 0x4D04800ull
#define PMMU_MME_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define PMMU_MME_PLL_DIV_1_RLX_SECTION 0x2000
#define mmPMMU_MME_PLL_DIV_2_RLX_BASE 0x4D04A00ull
#define PMMU_MME_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define PMMU_MME_PLL_DIV_2_RLX_SECTION 0x2000
#define mmPMMU_MME_PLL_DIV_3_RLX_BASE 0x4D04C00ull
#define PMMU_MME_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define PMMU_MME_PLL_DIV_3_RLX_SECTION 0x2800
#define mmPMMU_MME_PLL_SPECIAL_BASE 0x4D04E80ull
#define PMMU_MME_PLL_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_MME_PLL_SPECIAL_SECTION 0x1800
#define mmPMMU_VID_PLL_CTRL_BASE 0x4D05000ull
#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540
#define PMMU_VID_PLL_CTRL_SECTION 0x3600
#define mmPMMU_VID_PLL_ASIF_SLV_BASE 0x4D05360ull
#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000
#define mmPMMU_VID_PLL_DIV_0_RLX_BASE 0x4D05400ull
#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000
#define mmPMMU_VID_PLL_DIV_1_RLX_BASE 0x4D05800ull
#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000
#define mmPMMU_VID_PLL_DIV_2_RLX_BASE 0x4D05A00ull
#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000
#define mmPMMU_VID_PLL_DIV_3_RLX_BASE 0x4D05C00ull
#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800
#define mmPMMU_VID_PLL_SPECIAL_BASE 0x4D05E80ull
#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800
#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180
#define mmXBAR_MID_0_BASE 0x4D40000ull
#define XBAR_MID_0_MAX_OFFSET 0x1000
#define XBAR_MID_0_SECTION 0xE800
#define mmXBAR_MID_0_SPECIAL_BASE 0x4D40E80ull
#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_MID_0_SPECIAL_SECTION 0x1800
#define mmDCORE0_XBAR_DMA_PLL_CTRL_BASE 0x4D41000ull
#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D41360ull
#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D41400ull
#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D41800ull
#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D41A00ull
#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D41C00ull
#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x4D41E80ull
#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE0_XBAR_MMU_PLL_CTRL_BASE 0x4D42000ull
#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D42360ull
#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D42400ull
#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D42800ull
#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D42A00ull
#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D42C00ull
#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x4D42E80ull
#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE0_XBAR_IF_PLL_CTRL_BASE 0x4D43000ull
#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D43360ull
#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D43400ull
#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D43800ull
#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D43A00ull
#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D43C00ull
#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x4D43E80ull
#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE0_XBAR_MESH_PLL_CTRL_BASE 0x4D44000ull
#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D44360ull
#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D44400ull
#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D44800ull
#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D44A00ull
#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D44C00ull
#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x4D44E80ull
#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180
#define mmXBAR_EDGE_0_BASE 0x4D48000ull
#define XBAR_EDGE_0_MAX_OFFSET 0x1000
#define XBAR_EDGE_0_SECTION 0xE800
#define mmXBAR_EDGE_0_SPECIAL_BASE 0x4D48E80ull
#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180
#define mmXBAR_MID_1_BASE 0x4D50000ull
#define XBAR_MID_1_MAX_OFFSET 0x1000
#define XBAR_MID_1_SECTION 0xE800
#define mmXBAR_MID_1_SPECIAL_BASE 0x4D50E80ull
#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_MID_1_SPECIAL_SECTION 0x1800
#define mmDCORE1_XBAR_DMA_PLL_CTRL_BASE 0x4D51000ull
#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D51360ull
#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D51400ull
#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D51800ull
#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D51A00ull
#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D51C00ull
#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x4D51E80ull
#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_XBAR_MMU_PLL_CTRL_BASE 0x4D52000ull
#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D52360ull
#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D52400ull
#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D52800ull
#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D52A00ull
#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D52C00ull
#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x4D52E80ull
#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_XBAR_IF_PLL_CTRL_BASE 0x4D53000ull
#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D53360ull
#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D53400ull
#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D53800ull
#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D53A00ull
#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D53C00ull
#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x4D53E80ull
#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_XBAR_MESH_PLL_CTRL_BASE 0x4D54000ull
#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x4D54360ull
#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x4D54400ull
#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x4D54800ull
#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x4D54A00ull
#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x4D54C00ull
#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x4D54E80ull
#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_XBAR_HBM_PLL_CTRL_BASE 0x4D55000ull
#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D55360ull
#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D55400ull
#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D55800ull
#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D55A00ull
#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D55C00ull
#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x4D55E80ull
#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
#define mmXBAR_EDGE_1_BASE 0x4D58000ull
#define XBAR_EDGE_1_MAX_OFFSET 0x1000
#define XBAR_EDGE_1_SECTION 0xE800
#define mmXBAR_EDGE_1_SPECIAL_BASE 0x4D58E80ull
#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180
#define mmXBAR_MID_2_BASE 0x4D60000ull
#define XBAR_MID_2_MAX_OFFSET 0x1000
#define XBAR_MID_2_SECTION 0xE800
#define mmXBAR_MID_2_SPECIAL_BASE 0x4D60E80ull
#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_MID_2_SPECIAL_SECTION 0x1800
#define mmDCORE2_XBAR_DMA_PLL_CTRL_BASE 0x4D61000ull
#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D61360ull
#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D61400ull
#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D61800ull
#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D61A00ull
#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D61C00ull
#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x4D61E80ull
#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE2_XBAR_MMU_PLL_CTRL_BASE 0x4D62000ull
#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D62360ull
#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D62400ull
#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D62800ull
#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D62A00ull
#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D62C00ull
#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x4D62E80ull
#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE2_XBAR_IF_PLL_CTRL_BASE 0x4D63000ull
#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D63360ull
#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D63400ull
#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D63800ull
#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D63A00ull
#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D63C00ull
#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x4D63E80ull
#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE2_XBAR_BANK_PLL_CTRL_BASE 0x4D64000ull
#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D64360ull
#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D64400ull
#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D64800ull
#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D64A00ull
#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D64C00ull
#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x4D64E80ull
#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE2_XBAR_HBM_PLL_CTRL_BASE 0x4D65000ull
#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x4D65360ull
#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x4D65400ull
#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x4D65800ull
#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x4D65A00ull
#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x4D65C00ull
#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x4D65E80ull
#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180
#define mmXBAR_EDGE_2_BASE 0x4D68000ull
#define XBAR_EDGE_2_MAX_OFFSET 0x1000
#define XBAR_EDGE_2_SECTION 0xE800
#define mmXBAR_EDGE_2_SPECIAL_BASE 0x4D68E80ull
#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180
#define mmXBAR_MID_3_BASE 0x4D70000ull
#define XBAR_MID_3_MAX_OFFSET 0x1000
#define XBAR_MID_3_SECTION 0xE800
#define mmXBAR_MID_3_SPECIAL_BASE 0x4D70E80ull
#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_MID_3_SPECIAL_SECTION 0x1800
#define mmDCORE3_XBAR_DMA_PLL_CTRL_BASE 0x4D71000ull
#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x4D71360ull
#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x4D71400ull
#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x4D71800ull
#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x4D71A00ull
#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x4D71C00ull
#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x4D71E80ull
#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE3_XBAR_MMU_PLL_CTRL_BASE 0x4D72000ull
#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x4D72360ull
#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x4D72400ull
#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x4D72800ull
#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x4D72A00ull
#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x4D72C00ull
#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x4D72E80ull
#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE3_XBAR_IF_PLL_CTRL_BASE 0x4D73000ull
#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x4D73360ull
#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x4D73400ull
#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x4D73800ull
#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x4D73A00ull
#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x4D73C00ull
#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x4D73E80ull
#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 0x4D74000ull
#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x4D74360ull
#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x4D74400ull
#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x4D74800ull
#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x4D74A00ull
#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x4D74C00ull
#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x4D74E80ull
#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180
#define mmXBAR_EDGE_3_BASE 0x4D78000ull
#define XBAR_EDGE_3_MAX_OFFSET 0x1000
#define XBAR_EDGE_3_SECTION 0xE800
#define mmXBAR_EDGE_3_SPECIAL_BASE 0x4D78E80ull
#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800
#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180
#define mmPCIE_PMA_0_BASE 0x4D80000ull
#define PCIE_PMA_0_MAX_OFFSET 0x40000
#define PCIE_PMA_0_SECTION 0x40000
#define mmPCIE_PMA_1_BASE 0x4DC0000ull
#define PCIE_PMA_1_MAX_OFFSET 0x40000
#define PCIE_PMA_1_SECTION 0x40000
#define mmROT0_QM_ARC_DCCM_BASE 0x4E00000ull
#define ROT0_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define ROT0_QM_ARC_DCCM_SECTION 0x8000
#define mmROT0_QM_ARC_AUX_BASE 0x4E08000ull
#define ROT0_QM_ARC_AUX_MAX_OFFSET 0x1000
#define ROT0_QM_ARC_AUX_SECTION 0xE800
#define mmROT0_QM_ARC_AUX_SPECIAL_BASE 0x4E08E80ull
#define ROT0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ROT0_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmROT0_QM_BASE 0x4E0A000ull
#define ROT0_QM_MAX_OFFSET 0x1000
#define ROT0_QM_SECTION 0x9000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E0A900ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E0A908ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E0A910ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E0A918ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E0A920ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E0A928ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E0A930ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E0A938ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E0A940ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E0A948ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E0A950ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E0A958ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E0A960ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E0A968ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E0A970ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E0A978ull
#define ROT0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define ROT0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmROT0_QM_AXUSER_SECURED_BASE 0x4E0AB00ull
#define ROT0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define ROT0_QM_AXUSER_SECURED_SECTION 0x8000
#define mmROT0_QM_AXUSER_NONSECURED_BASE 0x4E0AB80ull
#define ROT0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define ROT0_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmROT0_QM_DBG_HBW_BASE 0x4E0AC00ull
#define ROT0_QM_DBG_HBW_MAX_OFFSET 0x5800
#define ROT0_QM_DBG_HBW_SECTION 0x8000
#define mmROT0_QM_DBG_LBW_BASE 0x4E0AC80ull
#define ROT0_QM_DBG_LBW_MAX_OFFSET 0x5800
#define ROT0_QM_DBG_LBW_SECTION 0x1000
#define mmROT0_QM_CGM_BASE 0x4E0AD80ull
#define ROT0_QM_CGM_MAX_OFFSET 0xC000
#define ROT0_QM_CGM_SECTION 0x1000
#define mmROT0_QM_SPECIAL_BASE 0x4E0AE80ull
#define ROT0_QM_SPECIAL_MAX_OFFSET 0x1800
#define ROT0_QM_SPECIAL_SECTION 0x1800
#define mmROT0_BASE 0x4E0B000ull
#define ROT0_MAX_OFFSET 0x1000
#define ROT0_SECTION 0x1000
#define mmROT0_DESC_BASE 0x4E0B100ull
#define ROT0_DESC_MAX_OFFSET 0x1080
#define ROT0_DESC_SECTION 0xD800
#define mmROT0_SPECIAL_BASE 0x4E0BE80ull
#define ROT0_SPECIAL_MAX_OFFSET 0x1800
#define ROT0_SPECIAL_SECTION 0x1800
#define mmROT0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E0C000ull
#define ROT0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define ROT0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmROT0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E0C200ull
#define ROT0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define ROT0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmROT0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E0C400ull
#define ROT0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define ROT0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmROT0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E0C600ull
#define ROT0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define ROT0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmROT0_MSTR_IF_E2E_CRDT_BASE 0x4E0C800ull
#define ROT0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define ROT0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmROT0_MSTR_IF_AXUSER_BASE 0x4E0CA80ull
#define ROT0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define ROT0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmROT0_MSTR_IF_DBG_HBW_BASE 0x4E0CB00ull
#define ROT0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define ROT0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmROT0_MSTR_IF_DBG_LBW_BASE 0x4E0CB80ull
#define ROT0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define ROT0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmROT0_MSTR_IF_CORE_HBW_BASE 0x4E0CC00ull
#define ROT0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define ROT0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmROT0_MSTR_IF_CORE_LBW_BASE 0x4E0CD80ull
#define ROT0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define ROT0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmROT0_MSTR_IF_SPECIAL_BASE 0x4E0CE80ull
#define ROT0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define ROT0_MSTR_IF_SPECIAL_SECTION 0x3180
#define mmROT1_QM_ARC_DCCM_BASE 0x4E10000ull
#define ROT1_QM_ARC_DCCM_MAX_OFFSET 0x4000
#define ROT1_QM_ARC_DCCM_SECTION 0x8000
#define mmROT1_QM_ARC_AUX_BASE 0x4E18000ull
#define ROT1_QM_ARC_AUX_MAX_OFFSET 0x1000
#define ROT1_QM_ARC_AUX_SECTION 0xE800
#define mmROT1_QM_ARC_AUX_SPECIAL_BASE 0x4E18E80ull
#define ROT1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ROT1_QM_ARC_AUX_SPECIAL_SECTION 0x1180
#define mmROT1_QM_BASE 0x4E1A000ull
#define ROT1_QM_MAX_OFFSET 0x1000
#define ROT1_QM_SECTION 0x9000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4E1A900ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4E1A908ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4E1A910ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4E1A918ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4E1A920ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4E1A928ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4E1A930ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4E1A938ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4E1A940ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4E1A948ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4E1A950ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4E1A958ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4E1A960ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4E1A968ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4E1A970ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmROT1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4E1A978ull
#define ROT1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define ROT1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmROT1_QM_AXUSER_SECURED_BASE 0x4E1AB00ull
#define ROT1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000
#define ROT1_QM_AXUSER_SECURED_SECTION 0x8000
#define mmROT1_QM_AXUSER_NONSECURED_BASE 0x4E1AB80ull
#define ROT1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define ROT1_QM_AXUSER_NONSECURED_SECTION 0x8000
#define mmROT1_QM_DBG_HBW_BASE 0x4E1AC00ull
#define ROT1_QM_DBG_HBW_MAX_OFFSET 0x5800
#define ROT1_QM_DBG_HBW_SECTION 0x8000
#define mmROT1_QM_DBG_LBW_BASE 0x4E1AC80ull
#define ROT1_QM_DBG_LBW_MAX_OFFSET 0x5800
#define ROT1_QM_DBG_LBW_SECTION 0x1000
#define mmROT1_QM_CGM_BASE 0x4E1AD80ull
#define ROT1_QM_CGM_MAX_OFFSET 0xC000
#define ROT1_QM_CGM_SECTION 0x1000
#define mmROT1_QM_SPECIAL_BASE 0x4E1AE80ull
#define ROT1_QM_SPECIAL_MAX_OFFSET 0x1800
#define ROT1_QM_SPECIAL_SECTION 0x1800
#define mmROT1_BASE 0x4E1B000ull
#define ROT1_MAX_OFFSET 0x1000
#define ROT1_SECTION 0x1000
#define mmROT1_DESC_BASE 0x4E1B100ull
#define ROT1_DESC_MAX_OFFSET 0x1080
#define ROT1_DESC_SECTION 0xD800
#define mmROT1_SPECIAL_BASE 0x4E1BE80ull
#define ROT1_SPECIAL_MAX_OFFSET 0x1800
#define ROT1_SPECIAL_SECTION 0x1800
#define mmROT1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E1C000ull
#define ROT1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define ROT1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmROT1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E1C200ull
#define ROT1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define ROT1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmROT1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E1C400ull
#define ROT1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define ROT1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmROT1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E1C600ull
#define ROT1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define ROT1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmROT1_MSTR_IF_E2E_CRDT_BASE 0x4E1C800ull
#define ROT1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define ROT1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmROT1_MSTR_IF_AXUSER_BASE 0x4E1CA80ull
#define ROT1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define ROT1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmROT1_MSTR_IF_DBG_HBW_BASE 0x4E1CB00ull
#define ROT1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define ROT1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmROT1_MSTR_IF_DBG_LBW_BASE 0x4E1CB80ull
#define ROT1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define ROT1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmROT1_MSTR_IF_CORE_HBW_BASE 0x4E1CC00ull
#define ROT1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define ROT1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmROT1_MSTR_IF_CORE_LBW_BASE 0x4E1CD80ull
#define ROT1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define ROT1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmROT1_MSTR_IF_SPECIAL_BASE 0x4E1CE80ull
#define ROT1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define ROT1_MSTR_IF_SPECIAL_SECTION 0x23180
#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E40000ull
#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E40E80ull
#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF0_RTR_H3_BASE 0x4E41000ull
#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
#define mmSFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E41E80ull
#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E42000ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E42200ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E42400ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E42600ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E42800ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E42A80ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E42B00ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E42B80ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E42C00ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E42D80ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E42E80ull
#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E43000ull
#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E43400ull
#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E43E80ull
#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E44000ull
#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E44E80ull
#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF1_RTR_H3_BASE 0x4E45000ull
#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
#define mmSFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E45E80ull
#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E46000ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E46200ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E46400ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E46600ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E46800ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E46A80ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E46B00ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E46B80ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E46C00ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E46D80ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E46E80ull
#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E47000ull
#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E47400ull
#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E47E80ull
#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x4E48000ull
#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
#define mmSFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E48E80ull
#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT0_LBW_RTR_IF_RTR_H3_BASE 0x4E49000ull
#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800
#define mmSFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E49E80ull
#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E4A000ull
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E4A200ull
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E4A400ull
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E4A600ull
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E4A800ull
#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E4AA80ull
#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E4AB00ull
#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E4AB80ull
#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E4AC00ull
#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E4AD80ull
#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E4AE80ull
#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E4B000ull
#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E4B400ull
#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E4BE80ull
#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT0_BASE 0x4E4C000ull
#define SFT0_MAX_OFFSET 0x1000
#define SFT0_SECTION 0xE800
#define mmSFT0_SPECIAL_BASE 0x4E4CE80ull
#define SFT0_SPECIAL_MAX_OFFSET 0x1800
#define SFT0_SPECIAL_SECTION 0x3180
#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E50000ull
#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E50E80ull
#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF0_RTR_H3_BASE 0x4E51000ull
#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
#define mmSFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E51E80ull
#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E52000ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E52200ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E52400ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E52600ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E52800ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E52A80ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E52B00ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E52B80ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E52C00ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E52D80ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E52E80ull
#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E53000ull
#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E53400ull
#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E53E80ull
#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E54000ull
#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E54E80ull
#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF1_RTR_H3_BASE 0x4E55000ull
#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
#define mmSFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E55E80ull
#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E56000ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E56200ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E56400ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E56600ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E56800ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E56A80ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E56B00ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E56B80ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E56C00ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E56D80ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E56E80ull
#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E57000ull
#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E57400ull
#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E57E80ull
#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x4E58000ull
#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
#define mmSFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E58E80ull
#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT1_LBW_RTR_IF_RTR_H3_BASE 0x4E59000ull
#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800
#define mmSFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E59E80ull
#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E5A000ull
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E5A200ull
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E5A400ull
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E5A600ull
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E5A800ull
#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E5AA80ull
#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E5AB00ull
#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E5AB80ull
#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E5AC00ull
#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E5AD80ull
#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E5AE80ull
#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E5B000ull
#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E5B400ull
#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E5BE80ull
#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT1_BASE 0x4E5C000ull
#define SFT1_MAX_OFFSET 0x1000
#define SFT1_SECTION 0xE800
#define mmSFT1_SPECIAL_BASE 0x4E5CE80ull
#define SFT1_SPECIAL_MAX_OFFSET 0x1800
#define SFT1_SPECIAL_SECTION 0x3180
#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E60000ull
#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E60E80ull
#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF0_RTR_H3_BASE 0x4E61000ull
#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
#define mmSFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E61E80ull
#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E62000ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E62200ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E62400ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E62600ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E62800ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E62A80ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E62B00ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E62B80ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E62C00ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E62D80ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E62E80ull
#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E63000ull
#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E63400ull
#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E63E80ull
#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E64000ull
#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E64E80ull
#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF1_RTR_H3_BASE 0x4E65000ull
#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
#define mmSFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E65E80ull
#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E66000ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E66200ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E66400ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E66600ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E66800ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E66A80ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E66B00ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E66B80ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E66C00ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E66D80ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E66E80ull
#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E67000ull
#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E67400ull
#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E67E80ull
#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x4E68000ull
#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
#define mmSFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E68E80ull
#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT2_LBW_RTR_IF_RTR_H3_BASE 0x4E69000ull
#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800
#define mmSFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E69E80ull
#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E6A000ull
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E6A200ull
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E6A400ull
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E6A600ull
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E6A800ull
#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E6AA80ull
#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E6AB00ull
#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E6AB80ull
#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E6AC00ull
#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E6AD80ull
#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E6AE80ull
#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E6B000ull
#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E6B400ull
#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E6BE80ull
#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT2_BASE 0x4E6C000ull
#define SFT2_MAX_OFFSET 0x1000
#define SFT2_SECTION 0xE800
#define mmSFT2_SPECIAL_BASE 0x4E6CE80ull
#define SFT2_SPECIAL_MAX_OFFSET 0x1800
#define SFT2_SPECIAL_SECTION 0x3180
#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x4E70000ull
#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800
#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x4E70E80ull
#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF0_RTR_H3_BASE 0x4E71000ull
#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000
#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800
#define mmSFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x4E71E80ull
#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x4E72000ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x4E72200ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x4E72400ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x4E72600ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x4E72800ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x4E72A80ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x4E72B00ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x4E72B80ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x4E72C00ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x4E72D80ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x4E72E80ull
#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x4E73000ull
#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x4E73400ull
#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x4E73E80ull
#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x4E74000ull
#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800
#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x4E74E80ull
#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF1_RTR_H3_BASE 0x4E75000ull
#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000
#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800
#define mmSFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x4E75E80ull
#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x4E76000ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x4E76200ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x4E76400ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x4E76600ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x4E76800ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x4E76A80ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x4E76B00ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x4E76B80ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x4E76C00ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x4E76D80ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x4E76E80ull
#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x4E77000ull
#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x4E77400ull
#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x4E77E80ull
#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x4E78000ull
#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000
#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800
#define mmSFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x4E78E80ull
#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800
#define mmSFT3_LBW_RTR_IF_RTR_H3_BASE 0x4E79000ull
#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000
#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800
#define mmSFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x4E79E80ull
#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800
#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x4E7A000ull
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x4E7A200ull
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x4E7A400ull
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x4E7A600ull
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x4E7A800ull
#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmSFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x4E7AA80ull
#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x4E7AB00ull
#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x4E7AB80ull
#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x4E7AC00ull
#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x4E7AD80ull
#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmSFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x4E7AE80ull
#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmSFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x4E7B000ull
#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000
#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000
#define mmSFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x4E7B400ull
#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600
#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800
#define mmSFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x4E7BE80ull
#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800
#define mmSFT3_BASE 0x4E7C000ull
#define SFT3_MAX_OFFSET 0x1000
#define SFT3_SECTION 0xE800
#define mmSFT3_SPECIAL_BASE 0x4E7CE80ull
#define SFT3_SPECIAL_MAX_OFFSET 0x1800
#define SFT3_SPECIAL_SECTION 0x4180
#define mmARC_FARM_FARM_BASE 0x4E81000ull
#define ARC_FARM_FARM_MAX_OFFSET 0x1000
#define ARC_FARM_FARM_SECTION 0xE800
#define mmARC_FARM_FARM_SPECIAL_BASE 0x4E81E80ull
#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800
#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x4E82000ull
#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x4E82200ull
#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x4E82400ull
#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x4E82600ull
#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x4E82800ull
#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x4E82A80ull
#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000
#define mmARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x4E82B00ull
#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x4E82B80ull
#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x4E82C00ull
#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x4E82D80ull
#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x4E82E80ull
#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180
#define mmARC_FARM_ARC0_AUX_BASE 0x4E88000ull
#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000
#define ARC_FARM_ARC0_AUX_SECTION 0xE800
#define mmARC_FARM_ARC0_AUX_SPECIAL_BASE 0x4E88E80ull
#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC0_DUP_ENG_BASE 0x4E89000ull
#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000
#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x4E89900ull
#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800
#define mmARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x4E89E80ull
#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180
#define mmARC_FARM_KDMA_BASE 0x4E8B000ull
#define ARC_FARM_KDMA_MAX_OFFSET 0x1000
#define ARC_FARM_KDMA_SECTION 0x8000
#define mmARC_FARM_KDMA_CTX_AXUSER_BASE 0x4E8B800ull
#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000
#define mmARC_FARM_KDMA_CTX_BASE 0x4E8B860ull
#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000
#define ARC_FARM_KDMA_CTX_SECTION 0x5A00
#define mmARC_FARM_KDMA_KDMA_CGM_BASE 0x4E8BE00ull
#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000
#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000
#define mmARC_FARM_KDMA_SPECIAL_BASE 0x4E8BE80ull
#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800
#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x4E8C000ull
#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x4E8C200ull
#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x4E8C400ull
#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x4E8C600ull
#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x4E8C800ull
#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x4E8CA80ull
#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000
#define mmARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x4E8CB00ull
#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x4E8CB80ull
#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x4E8CC00ull
#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x4E8CD80ull
#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x4E8CE80ull
#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180
#define mmARC_FARM_ARC0_ACP_ENG_BASE 0x4E8F000ull
#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800
#define mmARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x4E8FE80ull
#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC0_DCCM0_BASE 0x4E90000ull
#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000
#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000
#define mmARC_FARM_ARC0_DCCM1_BASE 0x4E98000ull
#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000
#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000
#define mmARC_FARM_ARC1_AUX_BASE 0x4EA8000ull
#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000
#define ARC_FARM_ARC1_AUX_SECTION 0xE800
#define mmARC_FARM_ARC1_AUX_SPECIAL_BASE 0x4EA8E80ull
#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC1_DUP_ENG_BASE 0x4EA9000ull
#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000
#define mmARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x4EA9900ull
#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800
#define mmARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x4EA9E80ull
#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180
#define mmARC_FARM_ARC1_ACP_ENG_BASE 0x4EAF000ull
#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800
#define mmARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x4EAFE80ull
#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC1_DCCM0_BASE 0x4EB0000ull
#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000
#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000
#define mmARC_FARM_ARC1_DCCM1_BASE 0x4EB8000ull
#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000
#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000
#define mmARC_FARM_ARC2_AUX_BASE 0x4EC8000ull
#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000
#define ARC_FARM_ARC2_AUX_SECTION 0xE800
#define mmARC_FARM_ARC2_AUX_SPECIAL_BASE 0x4EC8E80ull
#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC2_DUP_ENG_BASE 0x4EC9000ull
#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000
#define mmARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x4EC9900ull
#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800
#define mmARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x4EC9E80ull
#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180
#define mmARC_FARM_ARC2_ACP_ENG_BASE 0x4ECF000ull
#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800
#define mmARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x4ECFE80ull
#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC2_DCCM0_BASE 0x4ED0000ull
#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000
#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000
#define mmARC_FARM_ARC2_DCCM1_BASE 0x4ED8000ull
#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000
#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000
#define mmARC_FARM_ARC3_AUX_BASE 0x4EE8000ull
#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000
#define ARC_FARM_ARC3_AUX_SECTION 0xE800
#define mmARC_FARM_ARC3_AUX_SPECIAL_BASE 0x4EE8E80ull
#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC3_DUP_ENG_BASE 0x4EE9000ull
#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000
#define mmARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x4EE9900ull
#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000
#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800
#define mmARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x4EE9E80ull
#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180
#define mmARC_FARM_ARC3_ACP_ENG_BASE 0x4EEF000ull
#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000
#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800
#define mmARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x4EEFE80ull
#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800
#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800
#define mmARC_FARM_ARC3_DCCM0_BASE 0x4EF0000ull
#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000
#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000
#define mmARC_FARM_ARC3_DCCM1_BASE 0x4EF8000ull
#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000
#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000
#define mmPCIE_DEC0_CMD_BASE 0x4F00000ull
#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100
#define PCIE_DEC0_CMD_SECTION 0x1000
#define mmPCIE_DEC0_VSI_BASE 0x4F01000ull
#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0
#define PCIE_DEC0_VSI_SECTION 0x1000
#define mmPCIE_DEC0_L2C_BASE 0x4F02000ull
#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0
#define PCIE_DEC0_L2C_SECTION 0x1000
#define mmPCIE_VDEC0_BRDG_CTRL_BASE 0x4F03000ull
#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000
#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F03800ull
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F03900ull
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F03A00ull
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F03B00ull
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x4F03C00ull
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmPCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x4F03E80ull
#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmPCIE_VDEC0_CTRL_BASE 0x4F04000ull
#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CTRL_SECTION 0xE800
#define mmPCIE_VDEC0_CTRL_SPECIAL_BASE 0x4F04E80ull
#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800
#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x4F05000ull
#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x4F05200ull
#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x4F05400ull
#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x4F05600ull
#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x4F05800ull
#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x4F05A80ull
#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x4F05B00ull
#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x4F05B80ull
#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x4F05C00ull
#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x4F05D80ull
#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x4F05E80ull
#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180
#define mmPCIE_DEC1_CMD_BASE 0x4F10000ull
#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100
#define PCIE_DEC1_CMD_SECTION 0x1000
#define mmPCIE_DEC1_VSI_BASE 0x4F11000ull
#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0
#define PCIE_DEC1_VSI_SECTION 0x1000
#define mmPCIE_DEC1_L2C_BASE 0x4F12000ull
#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0
#define PCIE_DEC1_L2C_SECTION 0x1000
#define mmPCIE_VDEC1_BRDG_CTRL_BASE 0x4F13000ull
#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000
#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000
#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x4F13800ull
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000
#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x4F13900ull
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000
#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x4F13A00ull
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000
#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x4F13B00ull
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000
#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x4F13C00ull
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000
#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800
#define mmPCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x4F13E80ull
#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800
#define mmPCIE_VDEC1_CTRL_BASE 0x4F14000ull
#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CTRL_SECTION 0xE800
#define mmPCIE_VDEC1_CTRL_SPECIAL_BASE 0x4F14E80ull
#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800
#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x4F15000ull
#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x4F15200ull
#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x4F15400ull
#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x4F15600ull
#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmPCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x4F15800ull
#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmPCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x4F15A80ull
#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmPCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x4F15B00ull
#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmPCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x4F15B80ull
#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmPCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x4F15C00ull
#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmPCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x4F15D80ull
#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmPCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x4F15E80ull
#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180
#define mmDCORE0_XFT_BASE 0x4F40000ull
#define DCORE0_XFT_MAX_OFFSET 0x1000
#define DCORE0_XFT_SECTION 0xE800
#define mmDCORE0_XFT_SPECIAL_BASE 0x4F40E80ull
#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_XFT_SPECIAL_SECTION 0x1800
#define mmDCORE0_HBM_PLL_CTRL_BASE 0x4F41000ull
#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_HBM_PLL_ASIF_SLV_BASE 0x4F41360ull
#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_HBM_PLL_DIV_0_RLX_BASE 0x4F41400ull
#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_HBM_PLL_DIV_1_RLX_BASE 0x4F41800ull
#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_HBM_PLL_DIV_2_RLX_BASE 0x4F41A00ull
#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_HBM_PLL_DIV_3_RLX_BASE 0x4F41C00ull
#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_HBM_PLL_SPECIAL_BASE 0x4F41E80ull
#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC_PLL_CTRL_BASE 0x4F42000ull
#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_TPC_PLL_ASIF_SLV_BASE 0x4F42360ull
#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_TPC_PLL_DIV_0_RLX_BASE 0x4F42400ull
#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_TPC_PLL_DIV_1_RLX_BASE 0x4F42800ull
#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_TPC_PLL_DIV_2_RLX_BASE 0x4F42A00ull
#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_TPC_PLL_DIV_3_RLX_BASE 0x4F42C00ull
#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_TPC_PLL_SPECIAL_BASE 0x4F42E80ull
#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE0_PCI_PLL_CTRL_BASE 0x4F43000ull
#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600
#define mmDCORE0_PCI_PLL_ASIF_SLV_BASE 0x4F43360ull
#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE0_PCI_PLL_DIV_0_RLX_BASE 0x4F43400ull
#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE0_PCI_PLL_DIV_1_RLX_BASE 0x4F43800ull
#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE0_PCI_PLL_DIV_2_RLX_BASE 0x4F43A00ull
#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE0_PCI_PLL_DIV_3_RLX_BASE 0x4F43C00ull
#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE0_PCI_PLL_SPECIAL_BASE 0x4F43E80ull
#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180
#define mmDCORE0_TSTDVS_BASE 0x4F45000ull
#define DCORE0_TSTDVS_MAX_OFFSET 0x7800
#define DCORE0_TSTDVS_SECTION 0x1000
#define mmDCORE0_TS_WRAP_BASE 0x4F46000ull
#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380
#define DCORE0_TS_WRAP_SECTION 0x2000
#define mmDCORE0_TS_WRAP_ASIF_SLV_BASE 0x4F46200ull
#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00
#define mmDCORE1_XFT_BASE 0x4F50000ull
#define DCORE1_XFT_MAX_OFFSET 0x1000
#define DCORE1_XFT_SECTION 0xE800
#define mmDCORE1_XFT_SPECIAL_BASE 0x4F50E80ull
#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_XFT_SPECIAL_SECTION 0x1800
#define mmDCORE1_HBM_PLL_CTRL_BASE 0x4F51000ull
#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_HBM_PLL_ASIF_SLV_BASE 0x4F51360ull
#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_HBM_PLL_DIV_0_RLX_BASE 0x4F51400ull
#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_HBM_PLL_DIV_1_RLX_BASE 0x4F51800ull
#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_HBM_PLL_DIV_2_RLX_BASE 0x4F51A00ull
#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_HBM_PLL_DIV_3_RLX_BASE 0x4F51C00ull
#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_HBM_PLL_SPECIAL_BASE 0x4F51E80ull
#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_TPC_PLL_CTRL_BASE 0x4F52000ull
#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_TPC_PLL_ASIF_SLV_BASE 0x4F52360ull
#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_TPC_PLL_DIV_0_RLX_BASE 0x4F52400ull
#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_TPC_PLL_DIV_1_RLX_BASE 0x4F52800ull
#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_TPC_PLL_DIV_2_RLX_BASE 0x4F52A00ull
#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_TPC_PLL_DIV_3_RLX_BASE 0x4F52C00ull
#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_TPC_PLL_SPECIAL_BASE 0x4F52E80ull
#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE1_NIC_PLL_CTRL_BASE 0x4F53000ull
#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600
#define mmDCORE1_NIC_PLL_ASIF_SLV_BASE 0x4F53360ull
#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE1_NIC_PLL_DIV_0_RLX_BASE 0x4F53400ull
#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE1_NIC_PLL_DIV_1_RLX_BASE 0x4F53800ull
#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE1_NIC_PLL_DIV_2_RLX_BASE 0x4F53A00ull
#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE1_NIC_PLL_DIV_3_RLX_BASE 0x4F53C00ull
#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE1_NIC_PLL_SPECIAL_BASE 0x4F53E80ull
#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180
#define mmDCORE1_TSTDVS_BASE 0x4F55000ull
#define DCORE1_TSTDVS_MAX_OFFSET 0x7800
#define DCORE1_TSTDVS_SECTION 0x1000
#define mmDCORE1_TS_WRAP_BASE 0x4F56000ull
#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380
#define DCORE1_TS_WRAP_SECTION 0x2000
#define mmDCORE1_TS_WRAP_ASIF_SLV_BASE 0x4F56200ull
#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00
#define mmDCORE2_XFT_BASE 0x4F60000ull
#define DCORE2_XFT_MAX_OFFSET 0x1000
#define DCORE2_XFT_SECTION 0xE800
#define mmDCORE2_XFT_SPECIAL_BASE 0x4F60E80ull
#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_XFT_SPECIAL_SECTION 0x1800
#define mmDCORE2_HBM_PLL_CTRL_BASE 0x4F61000ull
#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_HBM_PLL_ASIF_SLV_BASE 0x4F61360ull
#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_HBM_PLL_DIV_0_RLX_BASE 0x4F61400ull
#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_HBM_PLL_DIV_1_RLX_BASE 0x4F61800ull
#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_HBM_PLL_DIV_2_RLX_BASE 0x4F61A00ull
#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_HBM_PLL_DIV_3_RLX_BASE 0x4F61C00ull
#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_HBM_PLL_SPECIAL_BASE 0x4F61E80ull
#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE2_TPC_PLL_CTRL_BASE 0x4F62000ull
#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600
#define mmDCORE2_TPC_PLL_ASIF_SLV_BASE 0x4F62360ull
#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE2_TPC_PLL_DIV_0_RLX_BASE 0x4F62400ull
#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE2_TPC_PLL_DIV_1_RLX_BASE 0x4F62800ull
#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE2_TPC_PLL_DIV_2_RLX_BASE 0x4F62A00ull
#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE2_TPC_PLL_DIV_3_RLX_BASE 0x4F62C00ull
#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE2_TPC_PLL_SPECIAL_BASE 0x4F62E80ull
#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180
#define mmDCORE2_TSTDVS_BASE 0x4F65000ull
#define DCORE2_TSTDVS_MAX_OFFSET 0x7800
#define DCORE2_TSTDVS_SECTION 0x1000
#define mmDCORE2_TS_WRAP_BASE 0x4F66000ull
#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380
#define DCORE2_TS_WRAP_SECTION 0x2000
#define mmDCORE2_TS_WRAP_ASIF_SLV_BASE 0x4F66200ull
#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00
#define mmDCORE3_XFT_BASE 0x4F70000ull
#define DCORE3_XFT_MAX_OFFSET 0x1000
#define DCORE3_XFT_SECTION 0xE800
#define mmDCORE3_XFT_SPECIAL_BASE 0x4F70E80ull
#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_XFT_SPECIAL_SECTION 0x1800
#define mmDCORE3_HBM_PLL_CTRL_BASE 0x4F71000ull
#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_HBM_PLL_ASIF_SLV_BASE 0x4F71360ull
#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_HBM_PLL_DIV_0_RLX_BASE 0x4F71400ull
#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_HBM_PLL_DIV_1_RLX_BASE 0x4F71800ull
#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_HBM_PLL_DIV_2_RLX_BASE 0x4F71A00ull
#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_HBM_PLL_DIV_3_RLX_BASE 0x4F71C00ull
#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_HBM_PLL_SPECIAL_BASE 0x4F71E80ull
#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE3_TPC_PLL_CTRL_BASE 0x4F72000ull
#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_TPC_PLL_ASIF_SLV_BASE 0x4F72360ull
#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_TPC_PLL_DIV_0_RLX_BASE 0x4F72400ull
#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_TPC_PLL_DIV_1_RLX_BASE 0x4F72800ull
#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_TPC_PLL_DIV_2_RLX_BASE 0x4F72A00ull
#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_TPC_PLL_DIV_3_RLX_BASE 0x4F72C00ull
#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_TPC_PLL_SPECIAL_BASE 0x4F72E80ull
#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800
#define mmDCORE3_NIC_PLL_CTRL_BASE 0x4F73000ull
#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540
#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600
#define mmDCORE3_NIC_PLL_ASIF_SLV_BASE 0x4F73360ull
#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000
#define mmDCORE3_NIC_PLL_DIV_0_RLX_BASE 0x4F73400ull
#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800
#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000
#define mmDCORE3_NIC_PLL_DIV_1_RLX_BASE 0x4F73800ull
#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000
#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000
#define mmDCORE3_NIC_PLL_DIV_2_RLX_BASE 0x4F73A00ull
#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000
#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000
#define mmDCORE3_NIC_PLL_DIV_3_RLX_BASE 0x4F73C00ull
#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000
#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800
#define mmDCORE3_NIC_PLL_SPECIAL_BASE 0x4F73E80ull
#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800
#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180
#define mmDCORE3_TSTDVS_BASE 0x4F75000ull
#define DCORE3_TSTDVS_MAX_OFFSET 0x7800
#define DCORE3_TSTDVS_SECTION 0x1000
#define mmDCORE3_TS_WRAP_BASE 0x4F76000ull
#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380
#define DCORE3_TS_WRAP_SECTION 0x2000
#define mmDCORE3_TS_WRAP_ASIF_SLV_BASE 0x4F76200ull
#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800
#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00
#define mmPCIE_PMA_2_BASE 0x4F80000ull
#define PCIE_PMA_2_MAX_OFFSET 0x40000
#define PCIE_PMA_2_SECTION 0x40000
#define mmPCIE_PMA_3_BASE 0x4FC0000ull
#define PCIE_PMA_3_MAX_OFFSET 0x40000
#define PCIE_PMA_3_SECTION 0x40000
#define mmHBM0_MC0_BASE 0x5000000ull
#define HBM0_MC0_MAX_OFFSET 0x1000
#define HBM0_MC0_SECTION 0xE800
#define mmHBM0_MC0_SPECIAL_BASE 0x5000E80ull
#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST0_BASE 0x5001000ull
#define HBM0_MC0BIST0_MAX_OFFSET 0x1000
#define HBM0_MC0BIST0_SECTION 0xE800
#define mmHBM0_MC0BIST0_SPECIAL_BASE 0x5001E80ull
#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST1_BASE 0x5002000ull
#define HBM0_MC0BIST1_MAX_OFFSET 0x1000
#define HBM0_MC0BIST1_SECTION 0xE800
#define mmHBM0_MC0BIST1_SPECIAL_BASE 0x5002E80ull
#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST2_BASE 0x5003000ull
#define HBM0_MC0BIST2_MAX_OFFSET 0x1000
#define HBM0_MC0BIST2_SECTION 0xE800
#define mmHBM0_MC0BIST2_SPECIAL_BASE 0x5003E80ull
#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST3_BASE 0x5004000ull
#define HBM0_MC0BIST3_MAX_OFFSET 0x1000
#define HBM0_MC0BIST3_SECTION 0xE800
#define mmHBM0_MC0BIST3_SPECIAL_BASE 0x5004E80ull
#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST4_BASE 0x5005000ull
#define HBM0_MC0BIST4_MAX_OFFSET 0x1000
#define HBM0_MC0BIST4_SECTION 0xE800
#define mmHBM0_MC0BIST4_SPECIAL_BASE 0x5005E80ull
#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST5_BASE 0x5006000ull
#define HBM0_MC0BIST5_MAX_OFFSET 0x1000
#define HBM0_MC0BIST5_SECTION 0xE800
#define mmHBM0_MC0BIST5_SPECIAL_BASE 0x5006E80ull
#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST6_BASE 0x5007000ull
#define HBM0_MC0BIST6_MAX_OFFSET 0x1000
#define HBM0_MC0BIST6_SECTION 0xE800
#define mmHBM0_MC0BIST6_SPECIAL_BASE 0x5007E80ull
#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST7_BASE 0x5008000ull
#define HBM0_MC0BIST7_MAX_OFFSET 0x1000
#define HBM0_MC0BIST7_SECTION 0xE800
#define mmHBM0_MC0BIST7_SPECIAL_BASE 0x5008E80ull
#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM0_MC0BIST8_MEM_BASE 0x5009000ull
#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM0_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM0_MC0BIST8_MEM_SPECIAL_BASE 0x5009E80ull
#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM0_MC1_BASE 0x5020000ull
#define HBM0_MC1_MAX_OFFSET 0x1000
#define HBM0_MC1_SECTION 0xE800
#define mmHBM0_MC1_SPECIAL_BASE 0x5020E80ull
#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST0_BASE 0x5021000ull
#define HBM0_MC1BIST0_MAX_OFFSET 0x1000
#define HBM0_MC1BIST0_SECTION 0xE800
#define mmHBM0_MC1BIST0_SPECIAL_BASE 0x5021E80ull
#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST1_BASE 0x5022000ull
#define HBM0_MC1BIST1_MAX_OFFSET 0x1000
#define HBM0_MC1BIST1_SECTION 0xE800
#define mmHBM0_MC1BIST1_SPECIAL_BASE 0x5022E80ull
#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST2_BASE 0x5023000ull
#define HBM0_MC1BIST2_MAX_OFFSET 0x1000
#define HBM0_MC1BIST2_SECTION 0xE800
#define mmHBM0_MC1BIST2_SPECIAL_BASE 0x5023E80ull
#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST3_BASE 0x5024000ull
#define HBM0_MC1BIST3_MAX_OFFSET 0x1000
#define HBM0_MC1BIST3_SECTION 0xE800
#define mmHBM0_MC1BIST3_SPECIAL_BASE 0x5024E80ull
#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST4_BASE 0x5025000ull
#define HBM0_MC1BIST4_MAX_OFFSET 0x1000
#define HBM0_MC1BIST4_SECTION 0xE800
#define mmHBM0_MC1BIST4_SPECIAL_BASE 0x5025E80ull
#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST5_BASE 0x5026000ull
#define HBM0_MC1BIST5_MAX_OFFSET 0x1000
#define HBM0_MC1BIST5_SECTION 0xE800
#define mmHBM0_MC1BIST5_SPECIAL_BASE 0x5026E80ull
#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST6_BASE 0x5027000ull
#define HBM0_MC1BIST6_MAX_OFFSET 0x1000
#define HBM0_MC1BIST6_SECTION 0xE800
#define mmHBM0_MC1BIST6_SPECIAL_BASE 0x5027E80ull
#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST7_BASE 0x5028000ull
#define HBM0_MC1BIST7_MAX_OFFSET 0x1000
#define HBM0_MC1BIST7_SECTION 0xE800
#define mmHBM0_MC1BIST7_SPECIAL_BASE 0x5028E80ull
#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM0_MC1BIST8_MEM_BASE 0x5029000ull
#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM0_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM0_MC1BIST8_MEM_SPECIAL_BASE 0x5029E80ull
#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM0_PHY_BASE 0x5040000ull
#define HBM0_PHY_MAX_OFFSET 0x4000
#define HBM0_PHY_SECTION 0x40000
#define mmHBM1_MC0_BASE 0x5080000ull
#define HBM1_MC0_MAX_OFFSET 0x1000
#define HBM1_MC0_SECTION 0xE800
#define mmHBM1_MC0_SPECIAL_BASE 0x5080E80ull
#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST0_BASE 0x5081000ull
#define HBM1_MC0BIST0_MAX_OFFSET 0x1000
#define HBM1_MC0BIST0_SECTION 0xE800
#define mmHBM1_MC0BIST0_SPECIAL_BASE 0x5081E80ull
#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST1_BASE 0x5082000ull
#define HBM1_MC0BIST1_MAX_OFFSET 0x1000
#define HBM1_MC0BIST1_SECTION 0xE800
#define mmHBM1_MC0BIST1_SPECIAL_BASE 0x5082E80ull
#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST2_BASE 0x5083000ull
#define HBM1_MC0BIST2_MAX_OFFSET 0x1000
#define HBM1_MC0BIST2_SECTION 0xE800
#define mmHBM1_MC0BIST2_SPECIAL_BASE 0x5083E80ull
#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST3_BASE 0x5084000ull
#define HBM1_MC0BIST3_MAX_OFFSET 0x1000
#define HBM1_MC0BIST3_SECTION 0xE800
#define mmHBM1_MC0BIST3_SPECIAL_BASE 0x5084E80ull
#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST4_BASE 0x5085000ull
#define HBM1_MC0BIST4_MAX_OFFSET 0x1000
#define HBM1_MC0BIST4_SECTION 0xE800
#define mmHBM1_MC0BIST4_SPECIAL_BASE 0x5085E80ull
#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST5_BASE 0x5086000ull
#define HBM1_MC0BIST5_MAX_OFFSET 0x1000
#define HBM1_MC0BIST5_SECTION 0xE800
#define mmHBM1_MC0BIST5_SPECIAL_BASE 0x5086E80ull
#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST6_BASE 0x5087000ull
#define HBM1_MC0BIST6_MAX_OFFSET 0x1000
#define HBM1_MC0BIST6_SECTION 0xE800
#define mmHBM1_MC0BIST6_SPECIAL_BASE 0x5087E80ull
#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST7_BASE 0x5088000ull
#define HBM1_MC0BIST7_MAX_OFFSET 0x1000
#define HBM1_MC0BIST7_SECTION 0xE800
#define mmHBM1_MC0BIST7_SPECIAL_BASE 0x5088E80ull
#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM1_MC0BIST8_MEM_BASE 0x5089000ull
#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM1_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM1_MC0BIST8_MEM_SPECIAL_BASE 0x5089E80ull
#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM1_MC1_BASE 0x50A0000ull
#define HBM1_MC1_MAX_OFFSET 0x1000
#define HBM1_MC1_SECTION 0xE800
#define mmHBM1_MC1_SPECIAL_BASE 0x50A0E80ull
#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST0_BASE 0x50A1000ull
#define HBM1_MC1BIST0_MAX_OFFSET 0x1000
#define HBM1_MC1BIST0_SECTION 0xE800
#define mmHBM1_MC1BIST0_SPECIAL_BASE 0x50A1E80ull
#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST1_BASE 0x50A2000ull
#define HBM1_MC1BIST1_MAX_OFFSET 0x1000
#define HBM1_MC1BIST1_SECTION 0xE800
#define mmHBM1_MC1BIST1_SPECIAL_BASE 0x50A2E80ull
#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST2_BASE 0x50A3000ull
#define HBM1_MC1BIST2_MAX_OFFSET 0x1000
#define HBM1_MC1BIST2_SECTION 0xE800
#define mmHBM1_MC1BIST2_SPECIAL_BASE 0x50A3E80ull
#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST3_BASE 0x50A4000ull
#define HBM1_MC1BIST3_MAX_OFFSET 0x1000
#define HBM1_MC1BIST3_SECTION 0xE800
#define mmHBM1_MC1BIST3_SPECIAL_BASE 0x50A4E80ull
#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST4_BASE 0x50A5000ull
#define HBM1_MC1BIST4_MAX_OFFSET 0x1000
#define HBM1_MC1BIST4_SECTION 0xE800
#define mmHBM1_MC1BIST4_SPECIAL_BASE 0x50A5E80ull
#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST5_BASE 0x50A6000ull
#define HBM1_MC1BIST5_MAX_OFFSET 0x1000
#define HBM1_MC1BIST5_SECTION 0xE800
#define mmHBM1_MC1BIST5_SPECIAL_BASE 0x50A6E80ull
#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST6_BASE 0x50A7000ull
#define HBM1_MC1BIST6_MAX_OFFSET 0x1000
#define HBM1_MC1BIST6_SECTION 0xE800
#define mmHBM1_MC1BIST6_SPECIAL_BASE 0x50A7E80ull
#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST7_BASE 0x50A8000ull
#define HBM1_MC1BIST7_MAX_OFFSET 0x1000
#define HBM1_MC1BIST7_SECTION 0xE800
#define mmHBM1_MC1BIST7_SPECIAL_BASE 0x50A8E80ull
#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM1_MC1BIST8_MEM_BASE 0x50A9000ull
#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM1_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM1_MC1BIST8_MEM_SPECIAL_BASE 0x50A9E80ull
#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM1_PHY_BASE 0x50C0000ull
#define HBM1_PHY_MAX_OFFSET 0x4000
#define HBM1_PHY_SECTION 0x40000
#define mmHBM2_MC0_BASE 0x5100000ull
#define HBM2_MC0_MAX_OFFSET 0x1000
#define HBM2_MC0_SECTION 0xE800
#define mmHBM2_MC0_SPECIAL_BASE 0x5100E80ull
#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST0_BASE 0x5101000ull
#define HBM2_MC0BIST0_MAX_OFFSET 0x1000
#define HBM2_MC0BIST0_SECTION 0xE800
#define mmHBM2_MC0BIST0_SPECIAL_BASE 0x5101E80ull
#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST1_BASE 0x5102000ull
#define HBM2_MC0BIST1_MAX_OFFSET 0x1000
#define HBM2_MC0BIST1_SECTION 0xE800
#define mmHBM2_MC0BIST1_SPECIAL_BASE 0x5102E80ull
#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST2_BASE 0x5103000ull
#define HBM2_MC0BIST2_MAX_OFFSET 0x1000
#define HBM2_MC0BIST2_SECTION 0xE800
#define mmHBM2_MC0BIST2_SPECIAL_BASE 0x5103E80ull
#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST3_BASE 0x5104000ull
#define HBM2_MC0BIST3_MAX_OFFSET 0x1000
#define HBM2_MC0BIST3_SECTION 0xE800
#define mmHBM2_MC0BIST3_SPECIAL_BASE 0x5104E80ull
#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST4_BASE 0x5105000ull
#define HBM2_MC0BIST4_MAX_OFFSET 0x1000
#define HBM2_MC0BIST4_SECTION 0xE800
#define mmHBM2_MC0BIST4_SPECIAL_BASE 0x5105E80ull
#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST5_BASE 0x5106000ull
#define HBM2_MC0BIST5_MAX_OFFSET 0x1000
#define HBM2_MC0BIST5_SECTION 0xE800
#define mmHBM2_MC0BIST5_SPECIAL_BASE 0x5106E80ull
#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST6_BASE 0x5107000ull
#define HBM2_MC0BIST6_MAX_OFFSET 0x1000
#define HBM2_MC0BIST6_SECTION 0xE800
#define mmHBM2_MC0BIST6_SPECIAL_BASE 0x5107E80ull
#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST7_BASE 0x5108000ull
#define HBM2_MC0BIST7_MAX_OFFSET 0x1000
#define HBM2_MC0BIST7_SECTION 0xE800
#define mmHBM2_MC0BIST7_SPECIAL_BASE 0x5108E80ull
#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM2_MC0BIST8_MEM_BASE 0x5109000ull
#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM2_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM2_MC0BIST8_MEM_SPECIAL_BASE 0x5109E80ull
#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM2_MC1_BASE 0x5120000ull
#define HBM2_MC1_MAX_OFFSET 0x1000
#define HBM2_MC1_SECTION 0xE800
#define mmHBM2_MC1_SPECIAL_BASE 0x5120E80ull
#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST0_BASE 0x5121000ull
#define HBM2_MC1BIST0_MAX_OFFSET 0x1000
#define HBM2_MC1BIST0_SECTION 0xE800
#define mmHBM2_MC1BIST0_SPECIAL_BASE 0x5121E80ull
#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST1_BASE 0x5122000ull
#define HBM2_MC1BIST1_MAX_OFFSET 0x1000
#define HBM2_MC1BIST1_SECTION 0xE800
#define mmHBM2_MC1BIST1_SPECIAL_BASE 0x5122E80ull
#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST2_BASE 0x5123000ull
#define HBM2_MC1BIST2_MAX_OFFSET 0x1000
#define HBM2_MC1BIST2_SECTION 0xE800
#define mmHBM2_MC1BIST2_SPECIAL_BASE 0x5123E80ull
#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST3_BASE 0x5124000ull
#define HBM2_MC1BIST3_MAX_OFFSET 0x1000
#define HBM2_MC1BIST3_SECTION 0xE800
#define mmHBM2_MC1BIST3_SPECIAL_BASE 0x5124E80ull
#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST4_BASE 0x5125000ull
#define HBM2_MC1BIST4_MAX_OFFSET 0x1000
#define HBM2_MC1BIST4_SECTION 0xE800
#define mmHBM2_MC1BIST4_SPECIAL_BASE 0x5125E80ull
#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST5_BASE 0x5126000ull
#define HBM2_MC1BIST5_MAX_OFFSET 0x1000
#define HBM2_MC1BIST5_SECTION 0xE800
#define mmHBM2_MC1BIST5_SPECIAL_BASE 0x5126E80ull
#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST6_BASE 0x5127000ull
#define HBM2_MC1BIST6_MAX_OFFSET 0x1000
#define HBM2_MC1BIST6_SECTION 0xE800
#define mmHBM2_MC1BIST6_SPECIAL_BASE 0x5127E80ull
#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST7_BASE 0x5128000ull
#define HBM2_MC1BIST7_MAX_OFFSET 0x1000
#define HBM2_MC1BIST7_SECTION 0xE800
#define mmHBM2_MC1BIST7_SPECIAL_BASE 0x5128E80ull
#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM2_MC1BIST8_MEM_BASE 0x5129000ull
#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM2_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM2_MC1BIST8_MEM_SPECIAL_BASE 0x5129E80ull
#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM2_PHY_BASE 0x5140000ull
#define HBM2_PHY_MAX_OFFSET 0x4000
#define HBM2_PHY_SECTION 0x40000
#define mmHBM3_MC0_BASE 0x5180000ull
#define HBM3_MC0_MAX_OFFSET 0x1000
#define HBM3_MC0_SECTION 0xE800
#define mmHBM3_MC0_SPECIAL_BASE 0x5180E80ull
#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST0_BASE 0x5181000ull
#define HBM3_MC0BIST0_MAX_OFFSET 0x1000
#define HBM3_MC0BIST0_SECTION 0xE800
#define mmHBM3_MC0BIST0_SPECIAL_BASE 0x5181E80ull
#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST1_BASE 0x5182000ull
#define HBM3_MC0BIST1_MAX_OFFSET 0x1000
#define HBM3_MC0BIST1_SECTION 0xE800
#define mmHBM3_MC0BIST1_SPECIAL_BASE 0x5182E80ull
#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST2_BASE 0x5183000ull
#define HBM3_MC0BIST2_MAX_OFFSET 0x1000
#define HBM3_MC0BIST2_SECTION 0xE800
#define mmHBM3_MC0BIST2_SPECIAL_BASE 0x5183E80ull
#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST3_BASE 0x5184000ull
#define HBM3_MC0BIST3_MAX_OFFSET 0x1000
#define HBM3_MC0BIST3_SECTION 0xE800
#define mmHBM3_MC0BIST3_SPECIAL_BASE 0x5184E80ull
#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST4_BASE 0x5185000ull
#define HBM3_MC0BIST4_MAX_OFFSET 0x1000
#define HBM3_MC0BIST4_SECTION 0xE800
#define mmHBM3_MC0BIST4_SPECIAL_BASE 0x5185E80ull
#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST5_BASE 0x5186000ull
#define HBM3_MC0BIST5_MAX_OFFSET 0x1000
#define HBM3_MC0BIST5_SECTION 0xE800
#define mmHBM3_MC0BIST5_SPECIAL_BASE 0x5186E80ull
#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST6_BASE 0x5187000ull
#define HBM3_MC0BIST6_MAX_OFFSET 0x1000
#define HBM3_MC0BIST6_SECTION 0xE800
#define mmHBM3_MC0BIST6_SPECIAL_BASE 0x5187E80ull
#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST7_BASE 0x5188000ull
#define HBM3_MC0BIST7_MAX_OFFSET 0x1000
#define HBM3_MC0BIST7_SECTION 0xE800
#define mmHBM3_MC0BIST7_SPECIAL_BASE 0x5188E80ull
#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM3_MC0BIST8_MEM_BASE 0x5189000ull
#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM3_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM3_MC0BIST8_MEM_SPECIAL_BASE 0x5189E80ull
#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM3_MC1_BASE 0x51A0000ull
#define HBM3_MC1_MAX_OFFSET 0x1000
#define HBM3_MC1_SECTION 0xE800
#define mmHBM3_MC1_SPECIAL_BASE 0x51A0E80ull
#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST0_BASE 0x51A1000ull
#define HBM3_MC1BIST0_MAX_OFFSET 0x1000
#define HBM3_MC1BIST0_SECTION 0xE800
#define mmHBM3_MC1BIST0_SPECIAL_BASE 0x51A1E80ull
#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST1_BASE 0x51A2000ull
#define HBM3_MC1BIST1_MAX_OFFSET 0x1000
#define HBM3_MC1BIST1_SECTION 0xE800
#define mmHBM3_MC1BIST1_SPECIAL_BASE 0x51A2E80ull
#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST2_BASE 0x51A3000ull
#define HBM3_MC1BIST2_MAX_OFFSET 0x1000
#define HBM3_MC1BIST2_SECTION 0xE800
#define mmHBM3_MC1BIST2_SPECIAL_BASE 0x51A3E80ull
#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST3_BASE 0x51A4000ull
#define HBM3_MC1BIST3_MAX_OFFSET 0x1000
#define HBM3_MC1BIST3_SECTION 0xE800
#define mmHBM3_MC1BIST3_SPECIAL_BASE 0x51A4E80ull
#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST4_BASE 0x51A5000ull
#define HBM3_MC1BIST4_MAX_OFFSET 0x1000
#define HBM3_MC1BIST4_SECTION 0xE800
#define mmHBM3_MC1BIST4_SPECIAL_BASE 0x51A5E80ull
#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST5_BASE 0x51A6000ull
#define HBM3_MC1BIST5_MAX_OFFSET 0x1000
#define HBM3_MC1BIST5_SECTION 0xE800
#define mmHBM3_MC1BIST5_SPECIAL_BASE 0x51A6E80ull
#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST6_BASE 0x51A7000ull
#define HBM3_MC1BIST6_MAX_OFFSET 0x1000
#define HBM3_MC1BIST6_SECTION 0xE800
#define mmHBM3_MC1BIST6_SPECIAL_BASE 0x51A7E80ull
#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST7_BASE 0x51A8000ull
#define HBM3_MC1BIST7_MAX_OFFSET 0x1000
#define HBM3_MC1BIST7_SECTION 0xE800
#define mmHBM3_MC1BIST7_SPECIAL_BASE 0x51A8E80ull
#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM3_MC1BIST8_MEM_BASE 0x51A9000ull
#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM3_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM3_MC1BIST8_MEM_SPECIAL_BASE 0x51A9E80ull
#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM3_PHY_BASE 0x51C0000ull
#define HBM3_PHY_MAX_OFFSET 0x4000
#define HBM3_PHY_SECTION 0x40000
#define mmHBM4_MC0_BASE 0x5200000ull
#define HBM4_MC0_MAX_OFFSET 0x1000
#define HBM4_MC0_SECTION 0xE800
#define mmHBM4_MC0_SPECIAL_BASE 0x5200E80ull
#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST0_BASE 0x5201000ull
#define HBM4_MC0BIST0_MAX_OFFSET 0x1000
#define HBM4_MC0BIST0_SECTION 0xE800
#define mmHBM4_MC0BIST0_SPECIAL_BASE 0x5201E80ull
#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST1_BASE 0x5202000ull
#define HBM4_MC0BIST1_MAX_OFFSET 0x1000
#define HBM4_MC0BIST1_SECTION 0xE800
#define mmHBM4_MC0BIST1_SPECIAL_BASE 0x5202E80ull
#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST2_BASE 0x5203000ull
#define HBM4_MC0BIST2_MAX_OFFSET 0x1000
#define HBM4_MC0BIST2_SECTION 0xE800
#define mmHBM4_MC0BIST2_SPECIAL_BASE 0x5203E80ull
#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST3_BASE 0x5204000ull
#define HBM4_MC0BIST3_MAX_OFFSET 0x1000
#define HBM4_MC0BIST3_SECTION 0xE800
#define mmHBM4_MC0BIST3_SPECIAL_BASE 0x5204E80ull
#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST4_BASE 0x5205000ull
#define HBM4_MC0BIST4_MAX_OFFSET 0x1000
#define HBM4_MC0BIST4_SECTION 0xE800
#define mmHBM4_MC0BIST4_SPECIAL_BASE 0x5205E80ull
#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST5_BASE 0x5206000ull
#define HBM4_MC0BIST5_MAX_OFFSET 0x1000
#define HBM4_MC0BIST5_SECTION 0xE800
#define mmHBM4_MC0BIST5_SPECIAL_BASE 0x5206E80ull
#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST6_BASE 0x5207000ull
#define HBM4_MC0BIST6_MAX_OFFSET 0x1000
#define HBM4_MC0BIST6_SECTION 0xE800
#define mmHBM4_MC0BIST6_SPECIAL_BASE 0x5207E80ull
#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST7_BASE 0x5208000ull
#define HBM4_MC0BIST7_MAX_OFFSET 0x1000
#define HBM4_MC0BIST7_SECTION 0xE800
#define mmHBM4_MC0BIST7_SPECIAL_BASE 0x5208E80ull
#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM4_MC0BIST8_MEM_BASE 0x5209000ull
#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM4_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM4_MC0BIST8_MEM_SPECIAL_BASE 0x5209E80ull
#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM4_MC1_BASE 0x5220000ull
#define HBM4_MC1_MAX_OFFSET 0x1000
#define HBM4_MC1_SECTION 0xE800
#define mmHBM4_MC1_SPECIAL_BASE 0x5220E80ull
#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST0_BASE 0x5221000ull
#define HBM4_MC1BIST0_MAX_OFFSET 0x1000
#define HBM4_MC1BIST0_SECTION 0xE800
#define mmHBM4_MC1BIST0_SPECIAL_BASE 0x5221E80ull
#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST1_BASE 0x5222000ull
#define HBM4_MC1BIST1_MAX_OFFSET 0x1000
#define HBM4_MC1BIST1_SECTION 0xE800
#define mmHBM4_MC1BIST1_SPECIAL_BASE 0x5222E80ull
#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST2_BASE 0x5223000ull
#define HBM4_MC1BIST2_MAX_OFFSET 0x1000
#define HBM4_MC1BIST2_SECTION 0xE800
#define mmHBM4_MC1BIST2_SPECIAL_BASE 0x5223E80ull
#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST3_BASE 0x5224000ull
#define HBM4_MC1BIST3_MAX_OFFSET 0x1000
#define HBM4_MC1BIST3_SECTION 0xE800
#define mmHBM4_MC1BIST3_SPECIAL_BASE 0x5224E80ull
#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST4_BASE 0x5225000ull
#define HBM4_MC1BIST4_MAX_OFFSET 0x1000
#define HBM4_MC1BIST4_SECTION 0xE800
#define mmHBM4_MC1BIST4_SPECIAL_BASE 0x5225E80ull
#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST5_BASE 0x5226000ull
#define HBM4_MC1BIST5_MAX_OFFSET 0x1000
#define HBM4_MC1BIST5_SECTION 0xE800
#define mmHBM4_MC1BIST5_SPECIAL_BASE 0x5226E80ull
#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST6_BASE 0x5227000ull
#define HBM4_MC1BIST6_MAX_OFFSET 0x1000
#define HBM4_MC1BIST6_SECTION 0xE800
#define mmHBM4_MC1BIST6_SPECIAL_BASE 0x5227E80ull
#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST7_BASE 0x5228000ull
#define HBM4_MC1BIST7_MAX_OFFSET 0x1000
#define HBM4_MC1BIST7_SECTION 0xE800
#define mmHBM4_MC1BIST7_SPECIAL_BASE 0x5228E80ull
#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM4_MC1BIST8_MEM_BASE 0x5229000ull
#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM4_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM4_MC1BIST8_MEM_SPECIAL_BASE 0x5229E80ull
#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM4_PHY_BASE 0x5240000ull
#define HBM4_PHY_MAX_OFFSET 0x4000
#define HBM4_PHY_SECTION 0x40000
#define mmHBM5_MC0_BASE 0x5280000ull
#define HBM5_MC0_MAX_OFFSET 0x1000
#define HBM5_MC0_SECTION 0xE800
#define mmHBM5_MC0_SPECIAL_BASE 0x5280E80ull
#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST0_BASE 0x5281000ull
#define HBM5_MC0BIST0_MAX_OFFSET 0x1000
#define HBM5_MC0BIST0_SECTION 0xE800
#define mmHBM5_MC0BIST0_SPECIAL_BASE 0x5281E80ull
#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST1_BASE 0x5282000ull
#define HBM5_MC0BIST1_MAX_OFFSET 0x1000
#define HBM5_MC0BIST1_SECTION 0xE800
#define mmHBM5_MC0BIST1_SPECIAL_BASE 0x5282E80ull
#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST2_BASE 0x5283000ull
#define HBM5_MC0BIST2_MAX_OFFSET 0x1000
#define HBM5_MC0BIST2_SECTION 0xE800
#define mmHBM5_MC0BIST2_SPECIAL_BASE 0x5283E80ull
#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST3_BASE 0x5284000ull
#define HBM5_MC0BIST3_MAX_OFFSET 0x1000
#define HBM5_MC0BIST3_SECTION 0xE800
#define mmHBM5_MC0BIST3_SPECIAL_BASE 0x5284E80ull
#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST4_BASE 0x5285000ull
#define HBM5_MC0BIST4_MAX_OFFSET 0x1000
#define HBM5_MC0BIST4_SECTION 0xE800
#define mmHBM5_MC0BIST4_SPECIAL_BASE 0x5285E80ull
#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST5_BASE 0x5286000ull
#define HBM5_MC0BIST5_MAX_OFFSET 0x1000
#define HBM5_MC0BIST5_SECTION 0xE800
#define mmHBM5_MC0BIST5_SPECIAL_BASE 0x5286E80ull
#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST6_BASE 0x5287000ull
#define HBM5_MC0BIST6_MAX_OFFSET 0x1000
#define HBM5_MC0BIST6_SECTION 0xE800
#define mmHBM5_MC0BIST6_SPECIAL_BASE 0x5287E80ull
#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST7_BASE 0x5288000ull
#define HBM5_MC0BIST7_MAX_OFFSET 0x1000
#define HBM5_MC0BIST7_SECTION 0xE800
#define mmHBM5_MC0BIST7_SPECIAL_BASE 0x5288E80ull
#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800
#define mmHBM5_MC0BIST8_MEM_BASE 0x5289000ull
#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000
#define HBM5_MC0BIST8_MEM_SECTION 0xE800
#define mmHBM5_MC0BIST8_MEM_SPECIAL_BASE 0x5289E80ull
#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM5_MC1_BASE 0x52A0000ull
#define HBM5_MC1_MAX_OFFSET 0x1000
#define HBM5_MC1_SECTION 0xE800
#define mmHBM5_MC1_SPECIAL_BASE 0x52A0E80ull
#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST0_BASE 0x52A1000ull
#define HBM5_MC1BIST0_MAX_OFFSET 0x1000
#define HBM5_MC1BIST0_SECTION 0xE800
#define mmHBM5_MC1BIST0_SPECIAL_BASE 0x52A1E80ull
#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST1_BASE 0x52A2000ull
#define HBM5_MC1BIST1_MAX_OFFSET 0x1000
#define HBM5_MC1BIST1_SECTION 0xE800
#define mmHBM5_MC1BIST1_SPECIAL_BASE 0x52A2E80ull
#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST2_BASE 0x52A3000ull
#define HBM5_MC1BIST2_MAX_OFFSET 0x1000
#define HBM5_MC1BIST2_SECTION 0xE800
#define mmHBM5_MC1BIST2_SPECIAL_BASE 0x52A3E80ull
#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST3_BASE 0x52A4000ull
#define HBM5_MC1BIST3_MAX_OFFSET 0x1000
#define HBM5_MC1BIST3_SECTION 0xE800
#define mmHBM5_MC1BIST3_SPECIAL_BASE 0x52A4E80ull
#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST4_BASE 0x52A5000ull
#define HBM5_MC1BIST4_MAX_OFFSET 0x1000
#define HBM5_MC1BIST4_SECTION 0xE800
#define mmHBM5_MC1BIST4_SPECIAL_BASE 0x52A5E80ull
#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST5_BASE 0x52A6000ull
#define HBM5_MC1BIST5_MAX_OFFSET 0x1000
#define HBM5_MC1BIST5_SECTION 0xE800
#define mmHBM5_MC1BIST5_SPECIAL_BASE 0x52A6E80ull
#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST6_BASE 0x52A7000ull
#define HBM5_MC1BIST6_MAX_OFFSET 0x1000
#define HBM5_MC1BIST6_SECTION 0xE800
#define mmHBM5_MC1BIST6_SPECIAL_BASE 0x52A7E80ull
#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST7_BASE 0x52A8000ull
#define HBM5_MC1BIST7_MAX_OFFSET 0x1000
#define HBM5_MC1BIST7_SECTION 0xE800
#define mmHBM5_MC1BIST7_SPECIAL_BASE 0x52A8E80ull
#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800
#define mmHBM5_MC1BIST8_MEM_BASE 0x52A9000ull
#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000
#define HBM5_MC1BIST8_MEM_SECTION 0xE800
#define mmHBM5_MC1BIST8_MEM_SPECIAL_BASE 0x52A9E80ull
#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800
#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180
#define mmHBM5_PHY_BASE 0x52C0000ull
#define HBM5_PHY_MAX_OFFSET 0x4000
#define HBM5_PHY_SECTION 0x140000
#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5400000ull
#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5400080ull
#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5400100ull
#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5400180ull
#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_0_SPECIAL_BASE 0x5400E80ull
#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5401000ull
#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5401080ull
#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5401100ull
#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5401180ull
#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_1_SPECIAL_BASE 0x5401E80ull
#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5402000ull
#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5402080ull
#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5402100ull
#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5402180ull
#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_2_SPECIAL_BASE 0x5402E80ull
#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5403000ull
#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5403080ull
#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5403100ull
#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5403180ull
#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_3_SPECIAL_BASE 0x5403E80ull
#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5404000ull
#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5404080ull
#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5404100ull
#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5404180ull
#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_4_SPECIAL_BASE 0x5404E80ull
#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5405000ull
#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5405080ull
#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5405100ull
#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5405180ull
#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_5_SPECIAL_BASE 0x5405E80ull
#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5406000ull
#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5406080ull
#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5406100ull
#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5406180ull
#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_6_SPECIAL_BASE 0x5406E80ull
#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5407000ull
#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5407080ull
#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5407100ull
#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5407180ull
#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_7_SPECIAL_BASE 0x5407E80ull
#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5408000ull
#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5408080ull
#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5408100ull
#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5408180ull
#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_8_SPECIAL_BASE 0x5408E80ull
#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5409000ull
#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5409080ull
#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5409100ull
#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5409180ull
#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_9_SPECIAL_BASE 0x5409E80ull
#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x540A000ull
#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x540A080ull
#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x540A100ull
#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x540A180ull
#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_10_SPECIAL_BASE 0x540AE80ull
#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x540B000ull
#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x540B080ull
#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x540B100ull
#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x540B180ull
#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_11_SPECIAL_BASE 0x540BE80ull
#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x540C000ull
#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x540C080ull
#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x540C100ull
#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x540C180ull
#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_12_SPECIAL_BASE 0x540CE80ull
#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x540D000ull
#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x540D080ull
#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x540D100ull
#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x540D180ull
#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_13_SPECIAL_BASE 0x540DE80ull
#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x540E000ull
#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x540E080ull
#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x540E100ull
#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x540E180ull
#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR0_14_SPECIAL_BASE 0x540EE80ull
#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC0_QM_DCCM0_BASE 0x5410000ull
#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC0_QM_DCCM0_SECTION 0x8000
#define mmNIC0_QM_ARC_AUX0_BASE 0x5418000ull
#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC0_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC0_QM_ARC_AUX0_SPECIAL_BASE 0x5418E80ull
#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC0_QM0_BASE 0x541A000ull
#define NIC0_QM0_MAX_OFFSET 0x1000
#define NIC0_QM0_SECTION 0x9000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x541A900ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x541A908ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x541A910ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x541A918ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x541A920ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x541A928ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x541A930ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x541A938ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x541A940ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x541A948ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x541A950ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x541A958ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x541A960ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x541A968ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x541A970ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x541A978ull
#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC0_QM0_AXUSER_SECURED_BASE 0x541AB00ull
#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC0_QM0_AXUSER_NONSECURED_BASE 0x541AB80ull
#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC0_QM0_DBG_HBW_BASE 0x541AC00ull
#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC0_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC0_QM0_DBG_LBW_BASE 0x541AC80ull
#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC0_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC0_QM0_CGM_BASE 0x541AD80ull
#define NIC0_QM0_CGM_MAX_OFFSET 0xC000
#define NIC0_QM0_CGM_SECTION 0x1000
#define mmNIC0_QM0_SPECIAL_BASE 0x541AE80ull
#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QM0_SPECIAL_SECTION 0x4180
#define mmNIC0_QPC0_BASE 0x541F000ull
#define NIC0_QPC0_MAX_OFFSET 0x1000
#define NIC0_QPC0_SECTION 0x7200
#define mmNIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x541F720ull
#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x541F728ull
#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x541F730ull
#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x541F738ull
#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x541F740ull
#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x541F748ull
#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x541F750ull
#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x541F758ull
#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x541F760ull
#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x541F768ull
#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x541F770ull
#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x541F778ull
#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x541F780ull
#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x541F788ull
#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x541F790ull
#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x541F798ull
#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x541F7A0ull
#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x541F7A8ull
#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x541F7B0ull
#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x541F7B8ull
#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x541F7C0ull
#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x541F7C8ull
#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x541F7D0ull
#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x541F7D8ull
#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x541F7E0ull
#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x541F7E8ull
#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x541F7F0ull
#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x541F7F8ull
#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x541F800ull
#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x541F808ull
#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x541F810ull
#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x541F818ull
#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC0_QPC0_AXUSER_CONG_QUE_BASE 0x541FB80ull
#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_RXWQE_BASE 0x541FBE0ull
#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x541FC40ull
#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_DB_FIFO_BASE 0x541FCA0ull
#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x541FD00ull
#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x541FD60ull
#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_QPC_RESP_BASE 0x541FDC0ull
#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC0_QPC0_AXUSER_QPC_REQ_BASE 0x541FE20ull
#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC0_QPC0_SPECIAL_BASE 0x541FE80ull
#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5420000ull
#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5420080ull
#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5420100ull
#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5420180ull
#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_0_SPECIAL_BASE 0x5420E80ull
#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5421000ull
#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5421080ull
#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5421100ull
#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5421180ull
#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_1_SPECIAL_BASE 0x5421E80ull
#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5422000ull
#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5422080ull
#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5422100ull
#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5422180ull
#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_2_SPECIAL_BASE 0x5422E80ull
#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5423000ull
#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5423080ull
#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5423100ull
#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5423180ull
#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_3_SPECIAL_BASE 0x5423E80ull
#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5424000ull
#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5424080ull
#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5424100ull
#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5424180ull
#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_4_SPECIAL_BASE 0x5424E80ull
#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5425000ull
#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5425080ull
#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5425100ull
#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5425180ull
#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_5_SPECIAL_BASE 0x5425E80ull
#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5426000ull
#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5426080ull
#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5426100ull
#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5426180ull
#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_6_SPECIAL_BASE 0x5426E80ull
#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5427000ull
#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5427080ull
#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5427100ull
#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5427180ull
#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_7_SPECIAL_BASE 0x5427E80ull
#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5428000ull
#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5428080ull
#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5428100ull
#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5428180ull
#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_8_SPECIAL_BASE 0x5428E80ull
#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5429000ull
#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5429080ull
#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5429100ull
#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5429180ull
#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_9_SPECIAL_BASE 0x5429E80ull
#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x542A000ull
#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x542A080ull
#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x542A100ull
#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x542A180ull
#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_10_SPECIAL_BASE 0x542AE80ull
#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x542B000ull
#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x542B080ull
#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x542B100ull
#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x542B180ull
#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_11_SPECIAL_BASE 0x542BE80ull
#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x542C000ull
#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x542C080ull
#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x542C100ull
#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x542C180ull
#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_12_SPECIAL_BASE 0x542CE80ull
#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x542D000ull
#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x542D080ull
#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x542D100ull
#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x542D180ull
#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_13_SPECIAL_BASE 0x542DE80ull
#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x542E000ull
#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x542E080ull
#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x542E100ull
#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x542E180ull
#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC0_UMR1_14_SPECIAL_BASE 0x542EE80ull
#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC0_QM_DCCM1_BASE 0x5430000ull
#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC0_QM_DCCM1_SECTION 0x8000
#define mmNIC0_QM_ARC_AUX1_BASE 0x5438000ull
#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC0_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC0_QM_ARC_AUX1_SPECIAL_BASE 0x5438E80ull
#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC0_QM1_BASE 0x543A000ull
#define NIC0_QM1_MAX_OFFSET 0x1000
#define NIC0_QM1_SECTION 0x9000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x543A900ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x543A908ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x543A910ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x543A918ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x543A920ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x543A928ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x543A930ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x543A938ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x543A940ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x543A948ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x543A950ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x543A958ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x543A960ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x543A968ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x543A970ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x543A978ull
#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC0_QM1_AXUSER_SECURED_BASE 0x543AB00ull
#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC0_QM1_AXUSER_NONSECURED_BASE 0x543AB80ull
#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC0_QM1_DBG_HBW_BASE 0x543AC00ull
#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC0_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC0_QM1_DBG_LBW_BASE 0x543AC80ull
#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC0_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC0_QM1_CGM_BASE 0x543AD80ull
#define NIC0_QM1_CGM_MAX_OFFSET 0xC000
#define NIC0_QM1_CGM_SECTION 0x1000
#define mmNIC0_QM1_SPECIAL_BASE 0x543AE80ull
#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QM1_SPECIAL_SECTION 0x4180
#define mmNIC0_QPC1_BASE 0x543F000ull
#define NIC0_QPC1_MAX_OFFSET 0x1000
#define NIC0_QPC1_SECTION 0x7200
#define mmNIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x543F720ull
#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x543F728ull
#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x543F730ull
#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x543F738ull
#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x543F740ull
#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x543F748ull
#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x543F750ull
#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x543F758ull
#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x543F760ull
#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x543F768ull
#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x543F770ull
#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x543F778ull
#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x543F780ull
#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x543F788ull
#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x543F790ull
#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x543F798ull
#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x543F7A0ull
#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x543F7A8ull
#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x543F7B0ull
#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x543F7B8ull
#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x543F7C0ull
#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x543F7C8ull
#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x543F7D0ull
#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x543F7D8ull
#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x543F7E0ull
#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x543F7E8ull
#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x543F7F0ull
#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x543F7F8ull
#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x543F800ull
#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x543F808ull
#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x543F810ull
#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x543F818ull
#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC0_QPC1_AXUSER_CONG_QUE_BASE 0x543FB80ull
#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_RXWQE_BASE 0x543FBE0ull
#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x543FC40ull
#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_DB_FIFO_BASE 0x543FCA0ull
#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x543FD00ull
#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x543FD60ull
#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_QPC_RESP_BASE 0x543FDC0ull
#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC0_QPC1_AXUSER_QPC_REQ_BASE 0x543FE20ull
#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC0_QPC1_SPECIAL_BASE 0x543FE80ull
#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC0_TMR_BASE 0x5448000ull
#define NIC0_TMR_MAX_OFFSET 0x1000
#define NIC0_TMR_SECTION 0xD600
#define mmNIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5448D60ull
#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC0_TMR_AXUSER_TMR_FIFO_BASE 0x5448DC0ull
#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC0_TMR_AXUSER_TMR_FSM_BASE 0x5448E20ull
#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC0_TMR_SPECIAL_BASE 0x5448E80ull
#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TMR_SPECIAL_SECTION 0x1800
#define mmNIC0_RXB_CORE_BASE 0x5449000ull
#define NIC0_RXB_CORE_MAX_OFFSET 0x1000
#define NIC0_RXB_CORE_SECTION 0x6100
#define mmNIC0_RXB_CORE_SCT_AWUSER_BASE 0x5449610ull
#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC0_RXB_CORE_SPECIAL_BASE 0x5449E80ull
#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC0_RXE0_BASE 0x544A000ull
#define NIC0_RXE0_MAX_OFFSET 0x1000
#define NIC0_RXE0_SECTION 0x9000
#define mmNIC0_RXE0_WQE_ARUSER_BASE 0x544A900ull
#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC0_RXE0_SPECIAL_BASE 0x544AE80ull
#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC0_RXE1_BASE 0x544B000ull
#define NIC0_RXE1_MAX_OFFSET 0x1000
#define NIC0_RXE1_SECTION 0x9000
#define mmNIC0_RXE1_WQE_ARUSER_BASE 0x544B900ull
#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC0_RXE1_SPECIAL_BASE 0x544BE80ull
#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x544C000ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x544C050ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x544C0A0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x544C0F0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x544C140ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x544C190ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x544C1E0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x544C230ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x544C280ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x544C2D0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x544C320ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x544C370ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x544C3C0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x544C410ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x544C460ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x544C4B0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x544C500ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x544C550ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x544C5A0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x544C5F0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x544C640ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x544C690ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x544C6E0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x544C730ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x544C780ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x544C7D0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x544C820ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x544C870ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x544C8C0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x544C910ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x544C960ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x544C9B0ull
#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC0_RXE0_AXUSER_SPECIAL_BASE 0x544CE80ull
#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x544D000ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x544D050ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x544D0A0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x544D0F0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x544D140ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x544D190ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x544D1E0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x544D230ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x544D280ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x544D2D0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x544D320ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x544D370ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x544D3C0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x544D410ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x544D460ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x544D4B0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x544D500ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x544D550ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x544D5A0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x544D5F0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x544D640ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x544D690ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x544D6E0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x544D730ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x544D780ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x544D7D0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x544D820ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x544D870ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x544D8C0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x544D910ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x544D960ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x544D9B0ull
#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC0_RXE1_AXUSER_SPECIAL_BASE 0x544DE80ull
#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC0_TXS0_BASE 0x5450000ull
#define NIC0_TXS0_MAX_OFFSET 0x1000
#define NIC0_TXS0_SECTION 0xE800
#define mmNIC0_TXS0_SPECIAL_BASE 0x5450E80ull
#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC0_TXS1_BASE 0x5451000ull
#define NIC0_TXS1_MAX_OFFSET 0x1000
#define NIC0_TXS1_SECTION 0xE800
#define mmNIC0_TXS1_SPECIAL_BASE 0x5451E80ull
#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC0_TXE0_BASE 0x5452000ull
#define NIC0_TXE0_MAX_OFFSET 0x1000
#define NIC0_TXE0_SECTION 0xE800
#define mmNIC0_TXE0_SPECIAL_BASE 0x5452E80ull
#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC0_TXE1_BASE 0x5453000ull
#define NIC0_TXE1_MAX_OFFSET 0x1000
#define NIC0_TXE1_SECTION 0xE800
#define mmNIC0_TXE1_SPECIAL_BASE 0x5453E80ull
#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC0_TXB_BASE 0x5454000ull
#define NIC0_TXB_MAX_OFFSET 0x1000
#define NIC0_TXB_SECTION 0xE800
#define mmNIC0_TXB_SPECIAL_BASE 0x5454E80ull
#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_TXB_SPECIAL_SECTION 0x1800
#define mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x5455000ull
#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x5455200ull
#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x5455400ull
#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x5455600ull
#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC0_MSTR_IF_E2E_CRDT_BASE 0x5455800ull
#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC0_MSTR_IF_AXUSER_BASE 0x5455A80ull
#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC0_MSTR_IF_DBG_HBW_BASE 0x5455B00ull
#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC0_MSTR_IF_DBG_LBW_BASE 0x5455B80ull
#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC0_MSTR_IF_CORE_HBW_BASE 0x5455C00ull
#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC0_MSTR_IF_CORE_LBW_BASE 0x5455D80ull
#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC0_MSTR_IF_SPECIAL_BASE 0x5455E80ull
#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC0_TX_AXUSER_BASE 0x5456000ull
#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC0_TX_AXUSER_SECTION 0x2000
#define mmNIC0_SERDES0_BASE 0x5458000ull
#define NIC0_SERDES0_MAX_OFFSET 0x3E40
#define NIC0_SERDES0_SECTION 0x4000
#define mmNIC0_SERDES1_BASE 0x545C000ull
#define NIC0_SERDES1_MAX_OFFSET 0x3E40
#define NIC0_SERDES1_SECTION 0x4000
#define mmNIC0_PHY_BASE 0x5460000ull
#define NIC0_PHY_MAX_OFFSET 0x1000
#define NIC0_PHY_SECTION 0xE800
#define mmNIC0_PHY_SPECIAL_BASE 0x5460E80ull
#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC0_PHY_SPECIAL_SECTION 0x7180
#define mmPRT0_MAC_AUX_BASE 0x5468000ull
#define PRT0_MAC_AUX_MAX_OFFSET 0x1000
#define PRT0_MAC_AUX_SECTION 0xE800
#define mmPRT0_MAC_AUX_SPECIAL_BASE 0x5468E80ull
#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT0_MAC_CORE_BASE 0x5469000ull
#define PRT0_MAC_CORE_MAX_OFFSET 0x1000
#define PRT0_MAC_CORE_SECTION 0xE800
#define mmPRT0_MAC_CORE_SPECIAL_BASE 0x5469E80ull
#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC0_MAC_RS_FEC_BASE 0x546A000ull
#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC0_MAC_RS_FEC_SECTION 0x1000
#define mmNIC0_MAC_GLOB_STAT_CONTROL_REG_BASE 0x546B000ull
#define NIC0_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC0_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC0_MAC_GLOB_STAT_RX0_BASE 0x546B100ull
#define NIC0_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC0_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC0_MAC_GLOB_STAT_RX1_BASE 0x546B18Cull
#define NIC0_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC0_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC0_MAC_GLOB_STAT_RX2_BASE 0x546B218ull
#define NIC0_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC0_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC0_MAC_GLOB_STAT_RX3_BASE 0x546B2A4ull
#define NIC0_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC0_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC0_MAC_GLOB_STAT_TX0_BASE 0x546B330ull
#define NIC0_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC0_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC0_MAC_GLOB_STAT_TX1_BASE 0x546B398ull
#define NIC0_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC0_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC0_MAC_GLOB_STAT_TX2_BASE 0x546B400ull
#define NIC0_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC0_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC0_MAC_GLOB_STAT_TX3_BASE 0x546B468ull
#define NIC0_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC0_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC0_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x546B800ull
#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC0_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC0_MAC_CH0_MAC_PCS_BASE 0x546C000ull
#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC0_MAC_CH0_MAC_128_BASE 0x546C400ull
#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC0_MAC_CH0_MAC_AN_BASE 0x546C800ull
#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC0_MAC_CH1_MAC_PCS_BASE 0x546D000ull
#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC0_MAC_CH1_MAC_128_BASE 0x546D400ull
#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC0_MAC_CH1_MAC_AN_BASE 0x546D800ull
#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC0_MAC_CH2_MAC_PCS_BASE 0x546E000ull
#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC0_MAC_CH2_MAC_128_BASE 0x546E400ull
#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC0_MAC_CH2_MAC_AN_BASE 0x546E800ull
#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC0_MAC_CH3_MAC_PCS_BASE 0x546F000ull
#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC0_MAC_CH3_MAC_128_BASE 0x546F400ull
#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC0_MAC_CH3_MAC_AN_BASE 0x546F800ull
#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5480000ull
#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5480080ull
#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5480100ull
#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5480180ull
#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_0_SPECIAL_BASE 0x5480E80ull
#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5481000ull
#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5481080ull
#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5481100ull
#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5481180ull
#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_1_SPECIAL_BASE 0x5481E80ull
#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5482000ull
#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5482080ull
#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5482100ull
#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5482180ull
#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_2_SPECIAL_BASE 0x5482E80ull
#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5483000ull
#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5483080ull
#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5483100ull
#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5483180ull
#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_3_SPECIAL_BASE 0x5483E80ull
#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5484000ull
#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5484080ull
#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5484100ull
#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5484180ull
#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_4_SPECIAL_BASE 0x5484E80ull
#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5485000ull
#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5485080ull
#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5485100ull
#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5485180ull
#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_5_SPECIAL_BASE 0x5485E80ull
#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5486000ull
#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5486080ull
#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5486100ull
#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5486180ull
#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_6_SPECIAL_BASE 0x5486E80ull
#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5487000ull
#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5487080ull
#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5487100ull
#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5487180ull
#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_7_SPECIAL_BASE 0x5487E80ull
#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5488000ull
#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5488080ull
#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5488100ull
#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5488180ull
#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_8_SPECIAL_BASE 0x5488E80ull
#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5489000ull
#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5489080ull
#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5489100ull
#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5489180ull
#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_9_SPECIAL_BASE 0x5489E80ull
#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x548A000ull
#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x548A080ull
#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x548A100ull
#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x548A180ull
#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_10_SPECIAL_BASE 0x548AE80ull
#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x548B000ull
#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x548B080ull
#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x548B100ull
#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x548B180ull
#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_11_SPECIAL_BASE 0x548BE80ull
#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x548C000ull
#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x548C080ull
#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x548C100ull
#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x548C180ull
#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_12_SPECIAL_BASE 0x548CE80ull
#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x548D000ull
#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x548D080ull
#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x548D100ull
#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x548D180ull
#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_13_SPECIAL_BASE 0x548DE80ull
#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x548E000ull
#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x548E080ull
#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x548E100ull
#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x548E180ull
#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR0_14_SPECIAL_BASE 0x548EE80ull
#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC1_QM_DCCM0_BASE 0x5490000ull
#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC1_QM_DCCM0_SECTION 0x8000
#define mmNIC1_QM_ARC_AUX0_BASE 0x5498000ull
#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC1_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC1_QM_ARC_AUX0_SPECIAL_BASE 0x5498E80ull
#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC1_QM0_BASE 0x549A000ull
#define NIC1_QM0_MAX_OFFSET 0x1000
#define NIC1_QM0_SECTION 0x9000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x549A900ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x549A908ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x549A910ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x549A918ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x549A920ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x549A928ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x549A930ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x549A938ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x549A940ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x549A948ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x549A950ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x549A958ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x549A960ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x549A968ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x549A970ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x549A978ull
#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC1_QM0_AXUSER_SECURED_BASE 0x549AB00ull
#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC1_QM0_AXUSER_NONSECURED_BASE 0x549AB80ull
#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC1_QM0_DBG_HBW_BASE 0x549AC00ull
#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC1_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC1_QM0_DBG_LBW_BASE 0x549AC80ull
#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC1_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC1_QM0_CGM_BASE 0x549AD80ull
#define NIC1_QM0_CGM_MAX_OFFSET 0xC000
#define NIC1_QM0_CGM_SECTION 0x1000
#define mmNIC1_QM0_SPECIAL_BASE 0x549AE80ull
#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QM0_SPECIAL_SECTION 0x4180
#define mmNIC1_QPC0_BASE 0x549F000ull
#define NIC1_QPC0_MAX_OFFSET 0x1000
#define NIC1_QPC0_SECTION 0x7200
#define mmNIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x549F720ull
#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x549F728ull
#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x549F730ull
#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x549F738ull
#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x549F740ull
#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x549F748ull
#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x549F750ull
#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x549F758ull
#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x549F760ull
#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x549F768ull
#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x549F770ull
#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x549F778ull
#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x549F780ull
#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x549F788ull
#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x549F790ull
#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x549F798ull
#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x549F7A0ull
#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x549F7A8ull
#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x549F7B0ull
#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x549F7B8ull
#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x549F7C0ull
#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x549F7C8ull
#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x549F7D0ull
#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x549F7D8ull
#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x549F7E0ull
#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x549F7E8ull
#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x549F7F0ull
#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x549F7F8ull
#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x549F800ull
#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x549F808ull
#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x549F810ull
#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x549F818ull
#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC1_QPC0_AXUSER_CONG_QUE_BASE 0x549FB80ull
#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_RXWQE_BASE 0x549FBE0ull
#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x549FC40ull
#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_DB_FIFO_BASE 0x549FCA0ull
#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x549FD00ull
#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x549FD60ull
#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_QPC_RESP_BASE 0x549FDC0ull
#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC1_QPC0_AXUSER_QPC_REQ_BASE 0x549FE20ull
#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC1_QPC0_SPECIAL_BASE 0x549FE80ull
#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x54A0000ull
#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x54A0080ull
#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x54A0100ull
#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x54A0180ull
#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_0_SPECIAL_BASE 0x54A0E80ull
#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x54A1000ull
#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x54A1080ull
#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x54A1100ull
#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x54A1180ull
#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_1_SPECIAL_BASE 0x54A1E80ull
#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x54A2000ull
#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x54A2080ull
#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x54A2100ull
#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x54A2180ull
#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_2_SPECIAL_BASE 0x54A2E80ull
#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x54A3000ull
#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x54A3080ull
#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x54A3100ull
#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x54A3180ull
#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_3_SPECIAL_BASE 0x54A3E80ull
#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x54A4000ull
#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x54A4080ull
#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x54A4100ull
#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x54A4180ull
#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_4_SPECIAL_BASE 0x54A4E80ull
#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x54A5000ull
#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x54A5080ull
#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x54A5100ull
#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x54A5180ull
#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_5_SPECIAL_BASE 0x54A5E80ull
#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x54A6000ull
#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x54A6080ull
#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x54A6100ull
#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x54A6180ull
#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_6_SPECIAL_BASE 0x54A6E80ull
#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x54A7000ull
#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x54A7080ull
#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x54A7100ull
#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x54A7180ull
#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_7_SPECIAL_BASE 0x54A7E80ull
#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x54A8000ull
#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x54A8080ull
#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x54A8100ull
#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x54A8180ull
#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_8_SPECIAL_BASE 0x54A8E80ull
#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x54A9000ull
#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x54A9080ull
#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x54A9100ull
#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x54A9180ull
#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_9_SPECIAL_BASE 0x54A9E80ull
#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x54AA000ull
#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x54AA080ull
#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x54AA100ull
#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x54AA180ull
#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_10_SPECIAL_BASE 0x54AAE80ull
#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x54AB000ull
#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x54AB080ull
#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x54AB100ull
#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x54AB180ull
#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_11_SPECIAL_BASE 0x54ABE80ull
#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x54AC000ull
#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x54AC080ull
#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x54AC100ull
#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x54AC180ull
#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_12_SPECIAL_BASE 0x54ACE80ull
#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x54AD000ull
#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x54AD080ull
#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x54AD100ull
#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x54AD180ull
#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_13_SPECIAL_BASE 0x54ADE80ull
#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x54AE000ull
#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x54AE080ull
#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x54AE100ull
#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x54AE180ull
#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC1_UMR1_14_SPECIAL_BASE 0x54AEE80ull
#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC1_QM_DCCM1_BASE 0x54B0000ull
#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC1_QM_DCCM1_SECTION 0x8000
#define mmNIC1_QM_ARC_AUX1_BASE 0x54B8000ull
#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC1_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC1_QM_ARC_AUX1_SPECIAL_BASE 0x54B8E80ull
#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC1_QM1_BASE 0x54BA000ull
#define NIC1_QM1_MAX_OFFSET 0x1000
#define NIC1_QM1_SECTION 0x9000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x54BA900ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x54BA908ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x54BA910ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x54BA918ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x54BA920ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x54BA928ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x54BA930ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x54BA938ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x54BA940ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x54BA948ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x54BA950ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x54BA958ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x54BA960ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x54BA968ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x54BA970ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x54BA978ull
#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC1_QM1_AXUSER_SECURED_BASE 0x54BAB00ull
#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC1_QM1_AXUSER_NONSECURED_BASE 0x54BAB80ull
#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC1_QM1_DBG_HBW_BASE 0x54BAC00ull
#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC1_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC1_QM1_DBG_LBW_BASE 0x54BAC80ull
#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC1_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC1_QM1_CGM_BASE 0x54BAD80ull
#define NIC1_QM1_CGM_MAX_OFFSET 0xC000
#define NIC1_QM1_CGM_SECTION 0x1000
#define mmNIC1_QM1_SPECIAL_BASE 0x54BAE80ull
#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QM1_SPECIAL_SECTION 0x4180
#define mmNIC1_QPC1_BASE 0x54BF000ull
#define NIC1_QPC1_MAX_OFFSET 0x1000
#define NIC1_QPC1_SECTION 0x7200
#define mmNIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x54BF720ull
#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x54BF728ull
#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x54BF730ull
#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x54BF738ull
#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x54BF740ull
#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x54BF748ull
#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x54BF750ull
#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x54BF758ull
#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x54BF760ull
#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x54BF768ull
#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x54BF770ull
#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x54BF778ull
#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x54BF780ull
#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x54BF788ull
#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x54BF790ull
#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x54BF798ull
#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x54BF7A0ull
#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x54BF7A8ull
#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x54BF7B0ull
#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x54BF7B8ull
#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x54BF7C0ull
#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x54BF7C8ull
#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x54BF7D0ull
#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x54BF7D8ull
#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x54BF7E0ull
#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x54BF7E8ull
#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x54BF7F0ull
#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x54BF7F8ull
#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x54BF800ull
#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x54BF808ull
#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x54BF810ull
#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x54BF818ull
#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC1_QPC1_AXUSER_CONG_QUE_BASE 0x54BFB80ull
#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_RXWQE_BASE 0x54BFBE0ull
#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x54BFC40ull
#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_DB_FIFO_BASE 0x54BFCA0ull
#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x54BFD00ull
#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x54BFD60ull
#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_QPC_RESP_BASE 0x54BFDC0ull
#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC1_QPC1_AXUSER_QPC_REQ_BASE 0x54BFE20ull
#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC1_QPC1_SPECIAL_BASE 0x54BFE80ull
#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC1_TMR_BASE 0x54C8000ull
#define NIC1_TMR_MAX_OFFSET 0x1000
#define NIC1_TMR_SECTION 0xD600
#define mmNIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x54C8D60ull
#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC1_TMR_AXUSER_TMR_FIFO_BASE 0x54C8DC0ull
#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC1_TMR_AXUSER_TMR_FSM_BASE 0x54C8E20ull
#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC1_TMR_SPECIAL_BASE 0x54C8E80ull
#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TMR_SPECIAL_SECTION 0x1800
#define mmNIC1_RXB_CORE_BASE 0x54C9000ull
#define NIC1_RXB_CORE_MAX_OFFSET 0x1000
#define NIC1_RXB_CORE_SECTION 0x6100
#define mmNIC1_RXB_CORE_SCT_AWUSER_BASE 0x54C9610ull
#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC1_RXB_CORE_SPECIAL_BASE 0x54C9E80ull
#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC1_RXE0_BASE 0x54CA000ull
#define NIC1_RXE0_MAX_OFFSET 0x1000
#define NIC1_RXE0_SECTION 0x9000
#define mmNIC1_RXE0_WQE_ARUSER_BASE 0x54CA900ull
#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC1_RXE0_SPECIAL_BASE 0x54CAE80ull
#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC1_RXE1_BASE 0x54CB000ull
#define NIC1_RXE1_MAX_OFFSET 0x1000
#define NIC1_RXE1_SECTION 0x9000
#define mmNIC1_RXE1_WQE_ARUSER_BASE 0x54CB900ull
#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC1_RXE1_SPECIAL_BASE 0x54CBE80ull
#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x54CC000ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x54CC050ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x54CC0A0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x54CC0F0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x54CC140ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x54CC190ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x54CC1E0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x54CC230ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x54CC280ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x54CC2D0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x54CC320ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x54CC370ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x54CC3C0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x54CC410ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x54CC460ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x54CC4B0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x54CC500ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x54CC550ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x54CC5A0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x54CC5F0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x54CC640ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x54CC690ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x54CC6E0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x54CC730ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x54CC780ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x54CC7D0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x54CC820ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x54CC870ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x54CC8C0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x54CC910ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x54CC960ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x54CC9B0ull
#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC1_RXE0_AXUSER_SPECIAL_BASE 0x54CCE80ull
#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x54CD000ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x54CD050ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x54CD0A0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x54CD0F0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x54CD140ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x54CD190ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x54CD1E0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x54CD230ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x54CD280ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x54CD2D0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x54CD320ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x54CD370ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x54CD3C0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x54CD410ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x54CD460ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x54CD4B0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x54CD500ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x54CD550ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x54CD5A0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x54CD5F0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x54CD640ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x54CD690ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x54CD6E0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x54CD730ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x54CD780ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x54CD7D0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x54CD820ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x54CD870ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x54CD8C0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x54CD910ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x54CD960ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x54CD9B0ull
#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC1_RXE1_AXUSER_SPECIAL_BASE 0x54CDE80ull
#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC1_TXS0_BASE 0x54D0000ull
#define NIC1_TXS0_MAX_OFFSET 0x1000
#define NIC1_TXS0_SECTION 0xE800
#define mmNIC1_TXS0_SPECIAL_BASE 0x54D0E80ull
#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC1_TXS1_BASE 0x54D1000ull
#define NIC1_TXS1_MAX_OFFSET 0x1000
#define NIC1_TXS1_SECTION 0xE800
#define mmNIC1_TXS1_SPECIAL_BASE 0x54D1E80ull
#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC1_TXE0_BASE 0x54D2000ull
#define NIC1_TXE0_MAX_OFFSET 0x1000
#define NIC1_TXE0_SECTION 0xE800
#define mmNIC1_TXE0_SPECIAL_BASE 0x54D2E80ull
#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC1_TXE1_BASE 0x54D3000ull
#define NIC1_TXE1_MAX_OFFSET 0x1000
#define NIC1_TXE1_SECTION 0xE800
#define mmNIC1_TXE1_SPECIAL_BASE 0x54D3E80ull
#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC1_TXB_BASE 0x54D4000ull
#define NIC1_TXB_MAX_OFFSET 0x1000
#define NIC1_TXB_SECTION 0xE800
#define mmNIC1_TXB_SPECIAL_BASE 0x54D4E80ull
#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_TXB_SPECIAL_SECTION 0x1800
#define mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x54D5000ull
#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x54D5200ull
#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x54D5400ull
#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x54D5600ull
#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC1_MSTR_IF_E2E_CRDT_BASE 0x54D5800ull
#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC1_MSTR_IF_AXUSER_BASE 0x54D5A80ull
#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC1_MSTR_IF_DBG_HBW_BASE 0x54D5B00ull
#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC1_MSTR_IF_DBG_LBW_BASE 0x54D5B80ull
#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC1_MSTR_IF_CORE_HBW_BASE 0x54D5C00ull
#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC1_MSTR_IF_CORE_LBW_BASE 0x54D5D80ull
#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC1_MSTR_IF_SPECIAL_BASE 0x54D5E80ull
#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC1_TX_AXUSER_BASE 0x54D6000ull
#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC1_TX_AXUSER_SECTION 0x2000
#define mmNIC1_SERDES0_BASE 0x54D8000ull
#define NIC1_SERDES0_MAX_OFFSET 0x3E40
#define NIC1_SERDES0_SECTION 0x4000
#define mmNIC1_SERDES1_BASE 0x54DC000ull
#define NIC1_SERDES1_MAX_OFFSET 0x3E40
#define NIC1_SERDES1_SECTION 0x4000
#define mmNIC1_PHY_BASE 0x54E0000ull
#define NIC1_PHY_MAX_OFFSET 0x1000
#define NIC1_PHY_SECTION 0xE800
#define mmNIC1_PHY_SPECIAL_BASE 0x54E0E80ull
#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC1_PHY_SPECIAL_SECTION 0x7180
#define mmPRT1_MAC_AUX_BASE 0x54E8000ull
#define PRT1_MAC_AUX_MAX_OFFSET 0x1000
#define PRT1_MAC_AUX_SECTION 0xE800
#define mmPRT1_MAC_AUX_SPECIAL_BASE 0x54E8E80ull
#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT1_MAC_CORE_BASE 0x54E9000ull
#define PRT1_MAC_CORE_MAX_OFFSET 0x1000
#define PRT1_MAC_CORE_SECTION 0xE800
#define mmPRT1_MAC_CORE_SPECIAL_BASE 0x54E9E80ull
#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC1_MAC_RS_FEC_BASE 0x54EA000ull
#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC1_MAC_RS_FEC_SECTION 0x1000
#define mmNIC1_MAC_GLOB_STAT_CONTROL_REG_BASE 0x54EB000ull
#define NIC1_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC1_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC1_MAC_GLOB_STAT_RX0_BASE 0x54EB100ull
#define NIC1_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC1_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC1_MAC_GLOB_STAT_RX1_BASE 0x54EB18Cull
#define NIC1_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC1_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC1_MAC_GLOB_STAT_RX2_BASE 0x54EB218ull
#define NIC1_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC1_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC1_MAC_GLOB_STAT_RX3_BASE 0x54EB2A4ull
#define NIC1_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC1_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC1_MAC_GLOB_STAT_TX0_BASE 0x54EB330ull
#define NIC1_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC1_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC1_MAC_GLOB_STAT_TX1_BASE 0x54EB398ull
#define NIC1_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC1_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC1_MAC_GLOB_STAT_TX2_BASE 0x54EB400ull
#define NIC1_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC1_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC1_MAC_GLOB_STAT_TX3_BASE 0x54EB468ull
#define NIC1_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC1_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC1_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x54EB800ull
#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC1_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC1_MAC_CH0_MAC_PCS_BASE 0x54EC000ull
#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC1_MAC_CH0_MAC_128_BASE 0x54EC400ull
#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC1_MAC_CH0_MAC_AN_BASE 0x54EC800ull
#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC1_MAC_CH1_MAC_PCS_BASE 0x54ED000ull
#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC1_MAC_CH1_MAC_128_BASE 0x54ED400ull
#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC1_MAC_CH1_MAC_AN_BASE 0x54ED800ull
#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC1_MAC_CH2_MAC_PCS_BASE 0x54EE000ull
#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC1_MAC_CH2_MAC_128_BASE 0x54EE400ull
#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC1_MAC_CH2_MAC_AN_BASE 0x54EE800ull
#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC1_MAC_CH3_MAC_PCS_BASE 0x54EF000ull
#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC1_MAC_CH3_MAC_128_BASE 0x54EF400ull
#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC1_MAC_CH3_MAC_AN_BASE 0x54EF800ull
#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5500000ull
#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5500080ull
#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5500100ull
#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5500180ull
#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_0_SPECIAL_BASE 0x5500E80ull
#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5501000ull
#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5501080ull
#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5501100ull
#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5501180ull
#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_1_SPECIAL_BASE 0x5501E80ull
#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5502000ull
#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5502080ull
#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5502100ull
#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5502180ull
#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_2_SPECIAL_BASE 0x5502E80ull
#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5503000ull
#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5503080ull
#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5503100ull
#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5503180ull
#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_3_SPECIAL_BASE 0x5503E80ull
#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5504000ull
#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5504080ull
#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5504100ull
#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5504180ull
#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_4_SPECIAL_BASE 0x5504E80ull
#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5505000ull
#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5505080ull
#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5505100ull
#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5505180ull
#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_5_SPECIAL_BASE 0x5505E80ull
#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5506000ull
#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5506080ull
#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5506100ull
#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5506180ull
#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_6_SPECIAL_BASE 0x5506E80ull
#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5507000ull
#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5507080ull
#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5507100ull
#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5507180ull
#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_7_SPECIAL_BASE 0x5507E80ull
#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5508000ull
#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5508080ull
#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5508100ull
#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5508180ull
#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_8_SPECIAL_BASE 0x5508E80ull
#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5509000ull
#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5509080ull
#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5509100ull
#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5509180ull
#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_9_SPECIAL_BASE 0x5509E80ull
#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x550A000ull
#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x550A080ull
#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x550A100ull
#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x550A180ull
#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_10_SPECIAL_BASE 0x550AE80ull
#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x550B000ull
#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x550B080ull
#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x550B100ull
#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x550B180ull
#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_11_SPECIAL_BASE 0x550BE80ull
#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x550C000ull
#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x550C080ull
#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x550C100ull
#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x550C180ull
#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_12_SPECIAL_BASE 0x550CE80ull
#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x550D000ull
#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x550D080ull
#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x550D100ull
#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x550D180ull
#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_13_SPECIAL_BASE 0x550DE80ull
#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x550E000ull
#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x550E080ull
#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x550E100ull
#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x550E180ull
#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR0_14_SPECIAL_BASE 0x550EE80ull
#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC2_QM_DCCM0_BASE 0x5510000ull
#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC2_QM_DCCM0_SECTION 0x8000
#define mmNIC2_QM_ARC_AUX0_BASE 0x5518000ull
#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC2_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC2_QM_ARC_AUX0_SPECIAL_BASE 0x5518E80ull
#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC2_QM0_BASE 0x551A000ull
#define NIC2_QM0_MAX_OFFSET 0x1000
#define NIC2_QM0_SECTION 0x9000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x551A900ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x551A908ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x551A910ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x551A918ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x551A920ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x551A928ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x551A930ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x551A938ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x551A940ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x551A948ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x551A950ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x551A958ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x551A960ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x551A968ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x551A970ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x551A978ull
#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC2_QM0_AXUSER_SECURED_BASE 0x551AB00ull
#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC2_QM0_AXUSER_NONSECURED_BASE 0x551AB80ull
#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC2_QM0_DBG_HBW_BASE 0x551AC00ull
#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC2_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC2_QM0_DBG_LBW_BASE 0x551AC80ull
#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC2_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC2_QM0_CGM_BASE 0x551AD80ull
#define NIC2_QM0_CGM_MAX_OFFSET 0xC000
#define NIC2_QM0_CGM_SECTION 0x1000
#define mmNIC2_QM0_SPECIAL_BASE 0x551AE80ull
#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QM0_SPECIAL_SECTION 0x4180
#define mmNIC2_QPC0_BASE 0x551F000ull
#define NIC2_QPC0_MAX_OFFSET 0x1000
#define NIC2_QPC0_SECTION 0x7200
#define mmNIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x551F720ull
#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x551F728ull
#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x551F730ull
#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x551F738ull
#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x551F740ull
#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x551F748ull
#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x551F750ull
#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x551F758ull
#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x551F760ull
#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x551F768ull
#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x551F770ull
#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x551F778ull
#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x551F780ull
#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x551F788ull
#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x551F790ull
#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x551F798ull
#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x551F7A0ull
#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x551F7A8ull
#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x551F7B0ull
#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x551F7B8ull
#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x551F7C0ull
#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x551F7C8ull
#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x551F7D0ull
#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x551F7D8ull
#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x551F7E0ull
#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x551F7E8ull
#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x551F7F0ull
#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x551F7F8ull
#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x551F800ull
#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x551F808ull
#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x551F810ull
#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x551F818ull
#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC2_QPC0_AXUSER_CONG_QUE_BASE 0x551FB80ull
#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_RXWQE_BASE 0x551FBE0ull
#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x551FC40ull
#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_DB_FIFO_BASE 0x551FCA0ull
#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x551FD00ull
#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x551FD60ull
#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_QPC_RESP_BASE 0x551FDC0ull
#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC2_QPC0_AXUSER_QPC_REQ_BASE 0x551FE20ull
#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC2_QPC0_SPECIAL_BASE 0x551FE80ull
#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5520000ull
#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5520080ull
#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5520100ull
#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5520180ull
#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_0_SPECIAL_BASE 0x5520E80ull
#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5521000ull
#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5521080ull
#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5521100ull
#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5521180ull
#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_1_SPECIAL_BASE 0x5521E80ull
#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5522000ull
#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5522080ull
#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5522100ull
#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5522180ull
#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_2_SPECIAL_BASE 0x5522E80ull
#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5523000ull
#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5523080ull
#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5523100ull
#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5523180ull
#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_3_SPECIAL_BASE 0x5523E80ull
#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5524000ull
#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5524080ull
#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5524100ull
#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5524180ull
#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_4_SPECIAL_BASE 0x5524E80ull
#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5525000ull
#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5525080ull
#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5525100ull
#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5525180ull
#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_5_SPECIAL_BASE 0x5525E80ull
#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5526000ull
#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5526080ull
#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5526100ull
#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5526180ull
#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_6_SPECIAL_BASE 0x5526E80ull
#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5527000ull
#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5527080ull
#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5527100ull
#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5527180ull
#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_7_SPECIAL_BASE 0x5527E80ull
#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5528000ull
#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5528080ull
#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5528100ull
#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5528180ull
#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_8_SPECIAL_BASE 0x5528E80ull
#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5529000ull
#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5529080ull
#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5529100ull
#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5529180ull
#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_9_SPECIAL_BASE 0x5529E80ull
#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x552A000ull
#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x552A080ull
#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x552A100ull
#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x552A180ull
#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_10_SPECIAL_BASE 0x552AE80ull
#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x552B000ull
#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x552B080ull
#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x552B100ull
#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x552B180ull
#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_11_SPECIAL_BASE 0x552BE80ull
#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x552C000ull
#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x552C080ull
#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x552C100ull
#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x552C180ull
#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_12_SPECIAL_BASE 0x552CE80ull
#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x552D000ull
#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x552D080ull
#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x552D100ull
#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x552D180ull
#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_13_SPECIAL_BASE 0x552DE80ull
#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x552E000ull
#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x552E080ull
#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x552E100ull
#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x552E180ull
#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC2_UMR1_14_SPECIAL_BASE 0x552EE80ull
#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC2_QM_DCCM1_BASE 0x5530000ull
#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC2_QM_DCCM1_SECTION 0x8000
#define mmNIC2_QM_ARC_AUX1_BASE 0x5538000ull
#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC2_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC2_QM_ARC_AUX1_SPECIAL_BASE 0x5538E80ull
#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC2_QM1_BASE 0x553A000ull
#define NIC2_QM1_MAX_OFFSET 0x1000
#define NIC2_QM1_SECTION 0x9000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x553A900ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x553A908ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x553A910ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x553A918ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x553A920ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x553A928ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x553A930ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x553A938ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x553A940ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x553A948ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x553A950ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x553A958ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x553A960ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x553A968ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x553A970ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x553A978ull
#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC2_QM1_AXUSER_SECURED_BASE 0x553AB00ull
#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC2_QM1_AXUSER_NONSECURED_BASE 0x553AB80ull
#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC2_QM1_DBG_HBW_BASE 0x553AC00ull
#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC2_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC2_QM1_DBG_LBW_BASE 0x553AC80ull
#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC2_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC2_QM1_CGM_BASE 0x553AD80ull
#define NIC2_QM1_CGM_MAX_OFFSET 0xC000
#define NIC2_QM1_CGM_SECTION 0x1000
#define mmNIC2_QM1_SPECIAL_BASE 0x553AE80ull
#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QM1_SPECIAL_SECTION 0x4180
#define mmNIC2_QPC1_BASE 0x553F000ull
#define NIC2_QPC1_MAX_OFFSET 0x1000
#define NIC2_QPC1_SECTION 0x7200
#define mmNIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x553F720ull
#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x553F728ull
#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x553F730ull
#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x553F738ull
#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x553F740ull
#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x553F748ull
#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x553F750ull
#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x553F758ull
#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x553F760ull
#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x553F768ull
#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x553F770ull
#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x553F778ull
#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x553F780ull
#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x553F788ull
#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x553F790ull
#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x553F798ull
#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x553F7A0ull
#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x553F7A8ull
#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x553F7B0ull
#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x553F7B8ull
#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x553F7C0ull
#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x553F7C8ull
#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x553F7D0ull
#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x553F7D8ull
#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x553F7E0ull
#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x553F7E8ull
#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x553F7F0ull
#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x553F7F8ull
#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x553F800ull
#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x553F808ull
#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x553F810ull
#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x553F818ull
#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC2_QPC1_AXUSER_CONG_QUE_BASE 0x553FB80ull
#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_RXWQE_BASE 0x553FBE0ull
#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x553FC40ull
#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_DB_FIFO_BASE 0x553FCA0ull
#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x553FD00ull
#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x553FD60ull
#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_QPC_RESP_BASE 0x553FDC0ull
#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC2_QPC1_AXUSER_QPC_REQ_BASE 0x553FE20ull
#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC2_QPC1_SPECIAL_BASE 0x553FE80ull
#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC2_TMR_BASE 0x5548000ull
#define NIC2_TMR_MAX_OFFSET 0x1000
#define NIC2_TMR_SECTION 0xD600
#define mmNIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5548D60ull
#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC2_TMR_AXUSER_TMR_FIFO_BASE 0x5548DC0ull
#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC2_TMR_AXUSER_TMR_FSM_BASE 0x5548E20ull
#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC2_TMR_SPECIAL_BASE 0x5548E80ull
#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TMR_SPECIAL_SECTION 0x1800
#define mmNIC2_RXB_CORE_BASE 0x5549000ull
#define NIC2_RXB_CORE_MAX_OFFSET 0x1000
#define NIC2_RXB_CORE_SECTION 0x6100
#define mmNIC2_RXB_CORE_SCT_AWUSER_BASE 0x5549610ull
#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC2_RXB_CORE_SPECIAL_BASE 0x5549E80ull
#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC2_RXE0_BASE 0x554A000ull
#define NIC2_RXE0_MAX_OFFSET 0x1000
#define NIC2_RXE0_SECTION 0x9000
#define mmNIC2_RXE0_WQE_ARUSER_BASE 0x554A900ull
#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC2_RXE0_SPECIAL_BASE 0x554AE80ull
#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC2_RXE1_BASE 0x554B000ull
#define NIC2_RXE1_MAX_OFFSET 0x1000
#define NIC2_RXE1_SECTION 0x9000
#define mmNIC2_RXE1_WQE_ARUSER_BASE 0x554B900ull
#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC2_RXE1_SPECIAL_BASE 0x554BE80ull
#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x554C000ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x554C050ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x554C0A0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x554C0F0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x554C140ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x554C190ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x554C1E0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x554C230ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x554C280ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x554C2D0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x554C320ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x554C370ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x554C3C0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x554C410ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x554C460ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x554C4B0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x554C500ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x554C550ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x554C5A0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x554C5F0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x554C640ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x554C690ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x554C6E0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x554C730ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x554C780ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x554C7D0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x554C820ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x554C870ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x554C8C0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x554C910ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x554C960ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x554C9B0ull
#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC2_RXE0_AXUSER_SPECIAL_BASE 0x554CE80ull
#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x554D000ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x554D050ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x554D0A0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x554D0F0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x554D140ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x554D190ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x554D1E0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x554D230ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x554D280ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x554D2D0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x554D320ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x554D370ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x554D3C0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x554D410ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x554D460ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x554D4B0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x554D500ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x554D550ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x554D5A0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x554D5F0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x554D640ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x554D690ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x554D6E0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x554D730ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x554D780ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x554D7D0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x554D820ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x554D870ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x554D8C0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x554D910ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x554D960ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x554D9B0ull
#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC2_RXE1_AXUSER_SPECIAL_BASE 0x554DE80ull
#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC2_TXS0_BASE 0x5550000ull
#define NIC2_TXS0_MAX_OFFSET 0x1000
#define NIC2_TXS0_SECTION 0xE800
#define mmNIC2_TXS0_SPECIAL_BASE 0x5550E80ull
#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC2_TXS1_BASE 0x5551000ull
#define NIC2_TXS1_MAX_OFFSET 0x1000
#define NIC2_TXS1_SECTION 0xE800
#define mmNIC2_TXS1_SPECIAL_BASE 0x5551E80ull
#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC2_TXE0_BASE 0x5552000ull
#define NIC2_TXE0_MAX_OFFSET 0x1000
#define NIC2_TXE0_SECTION 0xE800
#define mmNIC2_TXE0_SPECIAL_BASE 0x5552E80ull
#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC2_TXE1_BASE 0x5553000ull
#define NIC2_TXE1_MAX_OFFSET 0x1000
#define NIC2_TXE1_SECTION 0xE800
#define mmNIC2_TXE1_SPECIAL_BASE 0x5553E80ull
#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC2_TXB_BASE 0x5554000ull
#define NIC2_TXB_MAX_OFFSET 0x1000
#define NIC2_TXB_SECTION 0xE800
#define mmNIC2_TXB_SPECIAL_BASE 0x5554E80ull
#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_TXB_SPECIAL_SECTION 0x1800
#define mmNIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x5555000ull
#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x5555200ull
#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x5555400ull
#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x5555600ull
#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC2_MSTR_IF_E2E_CRDT_BASE 0x5555800ull
#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC2_MSTR_IF_AXUSER_BASE 0x5555A80ull
#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC2_MSTR_IF_DBG_HBW_BASE 0x5555B00ull
#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC2_MSTR_IF_DBG_LBW_BASE 0x5555B80ull
#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC2_MSTR_IF_CORE_HBW_BASE 0x5555C00ull
#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC2_MSTR_IF_CORE_LBW_BASE 0x5555D80ull
#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC2_MSTR_IF_SPECIAL_BASE 0x5555E80ull
#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC2_TX_AXUSER_BASE 0x5556000ull
#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC2_TX_AXUSER_SECTION 0x2000
#define mmNIC2_SERDES0_BASE 0x5558000ull
#define NIC2_SERDES0_MAX_OFFSET 0x3E40
#define NIC2_SERDES0_SECTION 0x4000
#define mmNIC2_SERDES1_BASE 0x555C000ull
#define NIC2_SERDES1_MAX_OFFSET 0x3E40
#define NIC2_SERDES1_SECTION 0x4000
#define mmNIC2_PHY_BASE 0x5560000ull
#define NIC2_PHY_MAX_OFFSET 0x1000
#define NIC2_PHY_SECTION 0xE800
#define mmNIC2_PHY_SPECIAL_BASE 0x5560E80ull
#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC2_PHY_SPECIAL_SECTION 0x7180
#define mmPRT2_MAC_AUX_BASE 0x5568000ull
#define PRT2_MAC_AUX_MAX_OFFSET 0x1000
#define PRT2_MAC_AUX_SECTION 0xE800
#define mmPRT2_MAC_AUX_SPECIAL_BASE 0x5568E80ull
#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT2_MAC_CORE_BASE 0x5569000ull
#define PRT2_MAC_CORE_MAX_OFFSET 0x1000
#define PRT2_MAC_CORE_SECTION 0xE800
#define mmPRT2_MAC_CORE_SPECIAL_BASE 0x5569E80ull
#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC2_MAC_RS_FEC_BASE 0x556A000ull
#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC2_MAC_RS_FEC_SECTION 0x1000
#define mmNIC2_MAC_GLOB_STAT_CONTROL_REG_BASE 0x556B000ull
#define NIC2_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC2_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC2_MAC_GLOB_STAT_RX0_BASE 0x556B100ull
#define NIC2_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC2_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC2_MAC_GLOB_STAT_RX1_BASE 0x556B18Cull
#define NIC2_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC2_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC2_MAC_GLOB_STAT_RX2_BASE 0x556B218ull
#define NIC2_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC2_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC2_MAC_GLOB_STAT_RX3_BASE 0x556B2A4ull
#define NIC2_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC2_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC2_MAC_GLOB_STAT_TX0_BASE 0x556B330ull
#define NIC2_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC2_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC2_MAC_GLOB_STAT_TX1_BASE 0x556B398ull
#define NIC2_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC2_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC2_MAC_GLOB_STAT_TX2_BASE 0x556B400ull
#define NIC2_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC2_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC2_MAC_GLOB_STAT_TX3_BASE 0x556B468ull
#define NIC2_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC2_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC2_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x556B800ull
#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC2_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC2_MAC_CH0_MAC_PCS_BASE 0x556C000ull
#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC2_MAC_CH0_MAC_128_BASE 0x556C400ull
#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC2_MAC_CH0_MAC_AN_BASE 0x556C800ull
#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC2_MAC_CH1_MAC_PCS_BASE 0x556D000ull
#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC2_MAC_CH1_MAC_128_BASE 0x556D400ull
#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC2_MAC_CH1_MAC_AN_BASE 0x556D800ull
#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC2_MAC_CH2_MAC_PCS_BASE 0x556E000ull
#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC2_MAC_CH2_MAC_128_BASE 0x556E400ull
#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC2_MAC_CH2_MAC_AN_BASE 0x556E800ull
#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC2_MAC_CH3_MAC_PCS_BASE 0x556F000ull
#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC2_MAC_CH3_MAC_128_BASE 0x556F400ull
#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC2_MAC_CH3_MAC_AN_BASE 0x556F800ull
#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5580000ull
#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5580080ull
#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5580100ull
#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5580180ull
#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_0_SPECIAL_BASE 0x5580E80ull
#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5581000ull
#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5581080ull
#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5581100ull
#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5581180ull
#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_1_SPECIAL_BASE 0x5581E80ull
#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5582000ull
#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5582080ull
#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5582100ull
#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5582180ull
#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_2_SPECIAL_BASE 0x5582E80ull
#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5583000ull
#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5583080ull
#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5583100ull
#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5583180ull
#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_3_SPECIAL_BASE 0x5583E80ull
#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5584000ull
#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5584080ull
#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5584100ull
#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5584180ull
#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_4_SPECIAL_BASE 0x5584E80ull
#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5585000ull
#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5585080ull
#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5585100ull
#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5585180ull
#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_5_SPECIAL_BASE 0x5585E80ull
#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5586000ull
#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5586080ull
#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5586100ull
#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5586180ull
#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_6_SPECIAL_BASE 0x5586E80ull
#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5587000ull
#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5587080ull
#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5587100ull
#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5587180ull
#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_7_SPECIAL_BASE 0x5587E80ull
#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5588000ull
#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5588080ull
#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5588100ull
#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5588180ull
#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_8_SPECIAL_BASE 0x5588E80ull
#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5589000ull
#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5589080ull
#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5589100ull
#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5589180ull
#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_9_SPECIAL_BASE 0x5589E80ull
#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x558A000ull
#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x558A080ull
#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x558A100ull
#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x558A180ull
#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_10_SPECIAL_BASE 0x558AE80ull
#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x558B000ull
#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x558B080ull
#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x558B100ull
#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x558B180ull
#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_11_SPECIAL_BASE 0x558BE80ull
#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x558C000ull
#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x558C080ull
#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x558C100ull
#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x558C180ull
#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_12_SPECIAL_BASE 0x558CE80ull
#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x558D000ull
#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x558D080ull
#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x558D100ull
#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x558D180ull
#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_13_SPECIAL_BASE 0x558DE80ull
#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x558E000ull
#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x558E080ull
#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x558E100ull
#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x558E180ull
#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR0_14_SPECIAL_BASE 0x558EE80ull
#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC3_QM_DCCM0_BASE 0x5590000ull
#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC3_QM_DCCM0_SECTION 0x8000
#define mmNIC3_QM_ARC_AUX0_BASE 0x5598000ull
#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC3_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC3_QM_ARC_AUX0_SPECIAL_BASE 0x5598E80ull
#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC3_QM0_BASE 0x559A000ull
#define NIC3_QM0_MAX_OFFSET 0x1000
#define NIC3_QM0_SECTION 0x9000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x559A900ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x559A908ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x559A910ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x559A918ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x559A920ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x559A928ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x559A930ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x559A938ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x559A940ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x559A948ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x559A950ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x559A958ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x559A960ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x559A968ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x559A970ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x559A978ull
#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC3_QM0_AXUSER_SECURED_BASE 0x559AB00ull
#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC3_QM0_AXUSER_NONSECURED_BASE 0x559AB80ull
#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC3_QM0_DBG_HBW_BASE 0x559AC00ull
#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC3_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC3_QM0_DBG_LBW_BASE 0x559AC80ull
#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC3_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC3_QM0_CGM_BASE 0x559AD80ull
#define NIC3_QM0_CGM_MAX_OFFSET 0xC000
#define NIC3_QM0_CGM_SECTION 0x1000
#define mmNIC3_QM0_SPECIAL_BASE 0x559AE80ull
#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QM0_SPECIAL_SECTION 0x4180
#define mmNIC3_QPC0_BASE 0x559F000ull
#define NIC3_QPC0_MAX_OFFSET 0x1000
#define NIC3_QPC0_SECTION 0x7200
#define mmNIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x559F720ull
#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x559F728ull
#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x559F730ull
#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x559F738ull
#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x559F740ull
#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x559F748ull
#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x559F750ull
#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x559F758ull
#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x559F760ull
#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x559F768ull
#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x559F770ull
#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x559F778ull
#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x559F780ull
#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x559F788ull
#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x559F790ull
#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x559F798ull
#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x559F7A0ull
#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x559F7A8ull
#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x559F7B0ull
#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x559F7B8ull
#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x559F7C0ull
#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x559F7C8ull
#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x559F7D0ull
#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x559F7D8ull
#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x559F7E0ull
#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x559F7E8ull
#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x559F7F0ull
#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x559F7F8ull
#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x559F800ull
#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x559F808ull
#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x559F810ull
#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x559F818ull
#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC3_QPC0_AXUSER_CONG_QUE_BASE 0x559FB80ull
#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_RXWQE_BASE 0x559FBE0ull
#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x559FC40ull
#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_DB_FIFO_BASE 0x559FCA0ull
#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x559FD00ull
#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x559FD60ull
#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_QPC_RESP_BASE 0x559FDC0ull
#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC3_QPC0_AXUSER_QPC_REQ_BASE 0x559FE20ull
#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC3_QPC0_SPECIAL_BASE 0x559FE80ull
#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x55A0000ull
#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x55A0080ull
#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x55A0100ull
#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x55A0180ull
#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_0_SPECIAL_BASE 0x55A0E80ull
#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x55A1000ull
#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x55A1080ull
#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x55A1100ull
#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x55A1180ull
#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_1_SPECIAL_BASE 0x55A1E80ull
#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x55A2000ull
#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x55A2080ull
#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x55A2100ull
#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x55A2180ull
#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_2_SPECIAL_BASE 0x55A2E80ull
#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x55A3000ull
#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x55A3080ull
#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x55A3100ull
#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x55A3180ull
#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_3_SPECIAL_BASE 0x55A3E80ull
#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x55A4000ull
#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x55A4080ull
#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x55A4100ull
#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x55A4180ull
#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_4_SPECIAL_BASE 0x55A4E80ull
#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x55A5000ull
#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x55A5080ull
#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x55A5100ull
#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x55A5180ull
#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_5_SPECIAL_BASE 0x55A5E80ull
#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x55A6000ull
#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x55A6080ull
#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x55A6100ull
#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x55A6180ull
#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_6_SPECIAL_BASE 0x55A6E80ull
#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x55A7000ull
#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x55A7080ull
#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x55A7100ull
#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x55A7180ull
#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_7_SPECIAL_BASE 0x55A7E80ull
#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x55A8000ull
#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x55A8080ull
#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x55A8100ull
#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x55A8180ull
#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_8_SPECIAL_BASE 0x55A8E80ull
#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x55A9000ull
#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x55A9080ull
#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x55A9100ull
#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x55A9180ull
#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_9_SPECIAL_BASE 0x55A9E80ull
#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x55AA000ull
#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x55AA080ull
#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x55AA100ull
#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x55AA180ull
#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_10_SPECIAL_BASE 0x55AAE80ull
#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x55AB000ull
#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x55AB080ull
#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x55AB100ull
#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x55AB180ull
#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_11_SPECIAL_BASE 0x55ABE80ull
#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x55AC000ull
#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x55AC080ull
#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x55AC100ull
#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x55AC180ull
#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_12_SPECIAL_BASE 0x55ACE80ull
#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x55AD000ull
#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x55AD080ull
#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x55AD100ull
#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x55AD180ull
#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_13_SPECIAL_BASE 0x55ADE80ull
#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x55AE000ull
#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x55AE080ull
#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x55AE100ull
#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x55AE180ull
#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC3_UMR1_14_SPECIAL_BASE 0x55AEE80ull
#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC3_QM_DCCM1_BASE 0x55B0000ull
#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC3_QM_DCCM1_SECTION 0x8000
#define mmNIC3_QM_ARC_AUX1_BASE 0x55B8000ull
#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC3_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC3_QM_ARC_AUX1_SPECIAL_BASE 0x55B8E80ull
#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC3_QM1_BASE 0x55BA000ull
#define NIC3_QM1_MAX_OFFSET 0x1000
#define NIC3_QM1_SECTION 0x9000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x55BA900ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x55BA908ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x55BA910ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x55BA918ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x55BA920ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x55BA928ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x55BA930ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x55BA938ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x55BA940ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x55BA948ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x55BA950ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x55BA958ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x55BA960ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x55BA968ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x55BA970ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x55BA978ull
#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC3_QM1_AXUSER_SECURED_BASE 0x55BAB00ull
#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC3_QM1_AXUSER_NONSECURED_BASE 0x55BAB80ull
#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC3_QM1_DBG_HBW_BASE 0x55BAC00ull
#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC3_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC3_QM1_DBG_LBW_BASE 0x55BAC80ull
#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC3_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC3_QM1_CGM_BASE 0x55BAD80ull
#define NIC3_QM1_CGM_MAX_OFFSET 0xC000
#define NIC3_QM1_CGM_SECTION 0x1000
#define mmNIC3_QM1_SPECIAL_BASE 0x55BAE80ull
#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QM1_SPECIAL_SECTION 0x4180
#define mmNIC3_QPC1_BASE 0x55BF000ull
#define NIC3_QPC1_MAX_OFFSET 0x1000
#define NIC3_QPC1_SECTION 0x7200
#define mmNIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x55BF720ull
#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x55BF728ull
#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x55BF730ull
#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x55BF738ull
#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x55BF740ull
#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x55BF748ull
#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x55BF750ull
#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x55BF758ull
#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x55BF760ull
#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x55BF768ull
#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x55BF770ull
#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x55BF778ull
#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x55BF780ull
#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x55BF788ull
#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x55BF790ull
#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x55BF798ull
#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x55BF7A0ull
#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x55BF7A8ull
#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x55BF7B0ull
#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x55BF7B8ull
#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x55BF7C0ull
#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x55BF7C8ull
#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x55BF7D0ull
#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x55BF7D8ull
#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x55BF7E0ull
#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x55BF7E8ull
#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x55BF7F0ull
#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x55BF7F8ull
#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x55BF800ull
#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x55BF808ull
#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x55BF810ull
#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x55BF818ull
#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC3_QPC1_AXUSER_CONG_QUE_BASE 0x55BFB80ull
#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_RXWQE_BASE 0x55BFBE0ull
#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x55BFC40ull
#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_DB_FIFO_BASE 0x55BFCA0ull
#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x55BFD00ull
#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x55BFD60ull
#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_QPC_RESP_BASE 0x55BFDC0ull
#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC3_QPC1_AXUSER_QPC_REQ_BASE 0x55BFE20ull
#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC3_QPC1_SPECIAL_BASE 0x55BFE80ull
#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC3_TMR_BASE 0x55C8000ull
#define NIC3_TMR_MAX_OFFSET 0x1000
#define NIC3_TMR_SECTION 0xD600
#define mmNIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x55C8D60ull
#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC3_TMR_AXUSER_TMR_FIFO_BASE 0x55C8DC0ull
#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC3_TMR_AXUSER_TMR_FSM_BASE 0x55C8E20ull
#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC3_TMR_SPECIAL_BASE 0x55C8E80ull
#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TMR_SPECIAL_SECTION 0x1800
#define mmNIC3_RXB_CORE_BASE 0x55C9000ull
#define NIC3_RXB_CORE_MAX_OFFSET 0x1000
#define NIC3_RXB_CORE_SECTION 0x6100
#define mmNIC3_RXB_CORE_SCT_AWUSER_BASE 0x55C9610ull
#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC3_RXB_CORE_SPECIAL_BASE 0x55C9E80ull
#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC3_RXE0_BASE 0x55CA000ull
#define NIC3_RXE0_MAX_OFFSET 0x1000
#define NIC3_RXE0_SECTION 0x9000
#define mmNIC3_RXE0_WQE_ARUSER_BASE 0x55CA900ull
#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC3_RXE0_SPECIAL_BASE 0x55CAE80ull
#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC3_RXE1_BASE 0x55CB000ull
#define NIC3_RXE1_MAX_OFFSET 0x1000
#define NIC3_RXE1_SECTION 0x9000
#define mmNIC3_RXE1_WQE_ARUSER_BASE 0x55CB900ull
#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC3_RXE1_SPECIAL_BASE 0x55CBE80ull
#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x55CC000ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x55CC050ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x55CC0A0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x55CC0F0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x55CC140ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x55CC190ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x55CC1E0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x55CC230ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x55CC280ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x55CC2D0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x55CC320ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x55CC370ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x55CC3C0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x55CC410ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x55CC460ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x55CC4B0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x55CC500ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x55CC550ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x55CC5A0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x55CC5F0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x55CC640ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x55CC690ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x55CC6E0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x55CC730ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x55CC780ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x55CC7D0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x55CC820ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x55CC870ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x55CC8C0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x55CC910ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x55CC960ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x55CC9B0ull
#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC3_RXE0_AXUSER_SPECIAL_BASE 0x55CCE80ull
#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x55CD000ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x55CD050ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x55CD0A0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x55CD0F0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x55CD140ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x55CD190ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x55CD1E0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x55CD230ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x55CD280ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x55CD2D0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x55CD320ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x55CD370ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x55CD3C0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x55CD410ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x55CD460ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x55CD4B0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x55CD500ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x55CD550ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x55CD5A0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x55CD5F0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x55CD640ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x55CD690ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x55CD6E0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x55CD730ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x55CD780ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x55CD7D0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x55CD820ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x55CD870ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x55CD8C0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x55CD910ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x55CD960ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x55CD9B0ull
#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC3_RXE1_AXUSER_SPECIAL_BASE 0x55CDE80ull
#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC3_TXS0_BASE 0x55D0000ull
#define NIC3_TXS0_MAX_OFFSET 0x1000
#define NIC3_TXS0_SECTION 0xE800
#define mmNIC3_TXS0_SPECIAL_BASE 0x55D0E80ull
#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC3_TXS1_BASE 0x55D1000ull
#define NIC3_TXS1_MAX_OFFSET 0x1000
#define NIC3_TXS1_SECTION 0xE800
#define mmNIC3_TXS1_SPECIAL_BASE 0x55D1E80ull
#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC3_TXE0_BASE 0x55D2000ull
#define NIC3_TXE0_MAX_OFFSET 0x1000
#define NIC3_TXE0_SECTION 0xE800
#define mmNIC3_TXE0_SPECIAL_BASE 0x55D2E80ull
#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC3_TXE1_BASE 0x55D3000ull
#define NIC3_TXE1_MAX_OFFSET 0x1000
#define NIC3_TXE1_SECTION 0xE800
#define mmNIC3_TXE1_SPECIAL_BASE 0x55D3E80ull
#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC3_TXB_BASE 0x55D4000ull
#define NIC3_TXB_MAX_OFFSET 0x1000
#define NIC3_TXB_SECTION 0xE800
#define mmNIC3_TXB_SPECIAL_BASE 0x55D4E80ull
#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_TXB_SPECIAL_SECTION 0x1800
#define mmNIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x55D5000ull
#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x55D5200ull
#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x55D5400ull
#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x55D5600ull
#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC3_MSTR_IF_E2E_CRDT_BASE 0x55D5800ull
#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC3_MSTR_IF_AXUSER_BASE 0x55D5A80ull
#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC3_MSTR_IF_DBG_HBW_BASE 0x55D5B00ull
#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC3_MSTR_IF_DBG_LBW_BASE 0x55D5B80ull
#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC3_MSTR_IF_CORE_HBW_BASE 0x55D5C00ull
#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC3_MSTR_IF_CORE_LBW_BASE 0x55D5D80ull
#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC3_MSTR_IF_SPECIAL_BASE 0x55D5E80ull
#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC3_TX_AXUSER_BASE 0x55D6000ull
#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC3_TX_AXUSER_SECTION 0x2000
#define mmNIC3_SERDES0_BASE 0x55D8000ull
#define NIC3_SERDES0_MAX_OFFSET 0x3E40
#define NIC3_SERDES0_SECTION 0x4000
#define mmNIC3_SERDES1_BASE 0x55DC000ull
#define NIC3_SERDES1_MAX_OFFSET 0x3E40
#define NIC3_SERDES1_SECTION 0x4000
#define mmNIC3_PHY_BASE 0x55E0000ull
#define NIC3_PHY_MAX_OFFSET 0x1000
#define NIC3_PHY_SECTION 0xE800
#define mmNIC3_PHY_SPECIAL_BASE 0x55E0E80ull
#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC3_PHY_SPECIAL_SECTION 0x7180
#define mmPRT3_MAC_AUX_BASE 0x55E8000ull
#define PRT3_MAC_AUX_MAX_OFFSET 0x1000
#define PRT3_MAC_AUX_SECTION 0xE800
#define mmPRT3_MAC_AUX_SPECIAL_BASE 0x55E8E80ull
#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT3_MAC_CORE_BASE 0x55E9000ull
#define PRT3_MAC_CORE_MAX_OFFSET 0x1000
#define PRT3_MAC_CORE_SECTION 0xE800
#define mmPRT3_MAC_CORE_SPECIAL_BASE 0x55E9E80ull
#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC3_MAC_RS_FEC_BASE 0x55EA000ull
#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC3_MAC_RS_FEC_SECTION 0x1000
#define mmNIC3_MAC_GLOB_STAT_CONTROL_REG_BASE 0x55EB000ull
#define NIC3_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC3_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC3_MAC_GLOB_STAT_RX0_BASE 0x55EB100ull
#define NIC3_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC3_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC3_MAC_GLOB_STAT_RX1_BASE 0x55EB18Cull
#define NIC3_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC3_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC3_MAC_GLOB_STAT_RX2_BASE 0x55EB218ull
#define NIC3_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC3_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC3_MAC_GLOB_STAT_RX3_BASE 0x55EB2A4ull
#define NIC3_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC3_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC3_MAC_GLOB_STAT_TX0_BASE 0x55EB330ull
#define NIC3_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC3_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC3_MAC_GLOB_STAT_TX1_BASE 0x55EB398ull
#define NIC3_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC3_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC3_MAC_GLOB_STAT_TX2_BASE 0x55EB400ull
#define NIC3_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC3_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC3_MAC_GLOB_STAT_TX3_BASE 0x55EB468ull
#define NIC3_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC3_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC3_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x55EB800ull
#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC3_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC3_MAC_CH0_MAC_PCS_BASE 0x55EC000ull
#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC3_MAC_CH0_MAC_128_BASE 0x55EC400ull
#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC3_MAC_CH0_MAC_AN_BASE 0x55EC800ull
#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC3_MAC_CH1_MAC_PCS_BASE 0x55ED000ull
#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC3_MAC_CH1_MAC_128_BASE 0x55ED400ull
#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC3_MAC_CH1_MAC_AN_BASE 0x55ED800ull
#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC3_MAC_CH2_MAC_PCS_BASE 0x55EE000ull
#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC3_MAC_CH2_MAC_128_BASE 0x55EE400ull
#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC3_MAC_CH2_MAC_AN_BASE 0x55EE800ull
#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC3_MAC_CH3_MAC_PCS_BASE 0x55EF000ull
#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC3_MAC_CH3_MAC_128_BASE 0x55EF400ull
#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC3_MAC_CH3_MAC_AN_BASE 0x55EF800ull
#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5600000ull
#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5600080ull
#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5600100ull
#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5600180ull
#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_0_SPECIAL_BASE 0x5600E80ull
#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5601000ull
#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5601080ull
#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5601100ull
#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5601180ull
#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_1_SPECIAL_BASE 0x5601E80ull
#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5602000ull
#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5602080ull
#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5602100ull
#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5602180ull
#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_2_SPECIAL_BASE 0x5602E80ull
#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5603000ull
#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5603080ull
#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5603100ull
#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5603180ull
#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_3_SPECIAL_BASE 0x5603E80ull
#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5604000ull
#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5604080ull
#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5604100ull
#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5604180ull
#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_4_SPECIAL_BASE 0x5604E80ull
#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5605000ull
#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5605080ull
#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5605100ull
#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5605180ull
#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_5_SPECIAL_BASE 0x5605E80ull
#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5606000ull
#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5606080ull
#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5606100ull
#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5606180ull
#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_6_SPECIAL_BASE 0x5606E80ull
#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5607000ull
#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5607080ull
#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5607100ull
#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5607180ull
#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_7_SPECIAL_BASE 0x5607E80ull
#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5608000ull
#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5608080ull
#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5608100ull
#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5608180ull
#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_8_SPECIAL_BASE 0x5608E80ull
#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5609000ull
#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5609080ull
#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5609100ull
#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5609180ull
#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_9_SPECIAL_BASE 0x5609E80ull
#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x560A000ull
#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x560A080ull
#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x560A100ull
#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x560A180ull
#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_10_SPECIAL_BASE 0x560AE80ull
#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x560B000ull
#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x560B080ull
#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x560B100ull
#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x560B180ull
#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_11_SPECIAL_BASE 0x560BE80ull
#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x560C000ull
#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x560C080ull
#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x560C100ull
#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x560C180ull
#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_12_SPECIAL_BASE 0x560CE80ull
#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x560D000ull
#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x560D080ull
#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x560D100ull
#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x560D180ull
#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_13_SPECIAL_BASE 0x560DE80ull
#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x560E000ull
#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x560E080ull
#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x560E100ull
#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x560E180ull
#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR0_14_SPECIAL_BASE 0x560EE80ull
#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC4_QM_DCCM0_BASE 0x5610000ull
#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC4_QM_DCCM0_SECTION 0x8000
#define mmNIC4_QM_ARC_AUX0_BASE 0x5618000ull
#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC4_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC4_QM_ARC_AUX0_SPECIAL_BASE 0x5618E80ull
#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC4_QM0_BASE 0x561A000ull
#define NIC4_QM0_MAX_OFFSET 0x1000
#define NIC4_QM0_SECTION 0x9000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x561A900ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x561A908ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x561A910ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x561A918ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x561A920ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x561A928ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x561A930ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x561A938ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x561A940ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x561A948ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x561A950ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x561A958ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x561A960ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x561A968ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x561A970ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x561A978ull
#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC4_QM0_AXUSER_SECURED_BASE 0x561AB00ull
#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC4_QM0_AXUSER_NONSECURED_BASE 0x561AB80ull
#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC4_QM0_DBG_HBW_BASE 0x561AC00ull
#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC4_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC4_QM0_DBG_LBW_BASE 0x561AC80ull
#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC4_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC4_QM0_CGM_BASE 0x561AD80ull
#define NIC4_QM0_CGM_MAX_OFFSET 0xC000
#define NIC4_QM0_CGM_SECTION 0x1000
#define mmNIC4_QM0_SPECIAL_BASE 0x561AE80ull
#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QM0_SPECIAL_SECTION 0x4180
#define mmNIC4_QPC0_BASE 0x561F000ull
#define NIC4_QPC0_MAX_OFFSET 0x1000
#define NIC4_QPC0_SECTION 0x7200
#define mmNIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x561F720ull
#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x561F728ull
#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x561F730ull
#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x561F738ull
#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x561F740ull
#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x561F748ull
#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x561F750ull
#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x561F758ull
#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x561F760ull
#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x561F768ull
#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x561F770ull
#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x561F778ull
#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x561F780ull
#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x561F788ull
#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x561F790ull
#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x561F798ull
#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x561F7A0ull
#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x561F7A8ull
#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x561F7B0ull
#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x561F7B8ull
#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x561F7C0ull
#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x561F7C8ull
#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x561F7D0ull
#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x561F7D8ull
#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x561F7E0ull
#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x561F7E8ull
#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x561F7F0ull
#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x561F7F8ull
#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x561F800ull
#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x561F808ull
#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x561F810ull
#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x561F818ull
#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC4_QPC0_AXUSER_CONG_QUE_BASE 0x561FB80ull
#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_RXWQE_BASE 0x561FBE0ull
#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x561FC40ull
#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_DB_FIFO_BASE 0x561FCA0ull
#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x561FD00ull
#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x561FD60ull
#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_QPC_RESP_BASE 0x561FDC0ull
#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC4_QPC0_AXUSER_QPC_REQ_BASE 0x561FE20ull
#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC4_QPC0_SPECIAL_BASE 0x561FE80ull
#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5620000ull
#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5620080ull
#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5620100ull
#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5620180ull
#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_0_SPECIAL_BASE 0x5620E80ull
#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5621000ull
#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5621080ull
#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5621100ull
#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5621180ull
#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_1_SPECIAL_BASE 0x5621E80ull
#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5622000ull
#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5622080ull
#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5622100ull
#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5622180ull
#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_2_SPECIAL_BASE 0x5622E80ull
#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5623000ull
#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5623080ull
#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5623100ull
#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5623180ull
#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_3_SPECIAL_BASE 0x5623E80ull
#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5624000ull
#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5624080ull
#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5624100ull
#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5624180ull
#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_4_SPECIAL_BASE 0x5624E80ull
#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5625000ull
#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5625080ull
#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5625100ull
#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5625180ull
#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_5_SPECIAL_BASE 0x5625E80ull
#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5626000ull
#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5626080ull
#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5626100ull
#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5626180ull
#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_6_SPECIAL_BASE 0x5626E80ull
#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5627000ull
#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5627080ull
#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5627100ull
#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5627180ull
#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_7_SPECIAL_BASE 0x5627E80ull
#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5628000ull
#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5628080ull
#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5628100ull
#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5628180ull
#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_8_SPECIAL_BASE 0x5628E80ull
#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5629000ull
#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5629080ull
#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5629100ull
#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5629180ull
#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_9_SPECIAL_BASE 0x5629E80ull
#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x562A000ull
#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x562A080ull
#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x562A100ull
#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x562A180ull
#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_10_SPECIAL_BASE 0x562AE80ull
#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x562B000ull
#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x562B080ull
#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x562B100ull
#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x562B180ull
#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_11_SPECIAL_BASE 0x562BE80ull
#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x562C000ull
#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x562C080ull
#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x562C100ull
#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x562C180ull
#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_12_SPECIAL_BASE 0x562CE80ull
#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x562D000ull
#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x562D080ull
#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x562D100ull
#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x562D180ull
#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_13_SPECIAL_BASE 0x562DE80ull
#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x562E000ull
#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x562E080ull
#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x562E100ull
#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x562E180ull
#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC4_UMR1_14_SPECIAL_BASE 0x562EE80ull
#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC4_QM_DCCM1_BASE 0x5630000ull
#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC4_QM_DCCM1_SECTION 0x8000
#define mmNIC4_QM_ARC_AUX1_BASE 0x5638000ull
#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC4_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC4_QM_ARC_AUX1_SPECIAL_BASE 0x5638E80ull
#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC4_QM1_BASE 0x563A000ull
#define NIC4_QM1_MAX_OFFSET 0x1000
#define NIC4_QM1_SECTION 0x9000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x563A900ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x563A908ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x563A910ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x563A918ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x563A920ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x563A928ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x563A930ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x563A938ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x563A940ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x563A948ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x563A950ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x563A958ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x563A960ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x563A968ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x563A970ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x563A978ull
#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC4_QM1_AXUSER_SECURED_BASE 0x563AB00ull
#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC4_QM1_AXUSER_NONSECURED_BASE 0x563AB80ull
#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC4_QM1_DBG_HBW_BASE 0x563AC00ull
#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC4_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC4_QM1_DBG_LBW_BASE 0x563AC80ull
#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC4_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC4_QM1_CGM_BASE 0x563AD80ull
#define NIC4_QM1_CGM_MAX_OFFSET 0xC000
#define NIC4_QM1_CGM_SECTION 0x1000
#define mmNIC4_QM1_SPECIAL_BASE 0x563AE80ull
#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QM1_SPECIAL_SECTION 0x4180
#define mmNIC4_QPC1_BASE 0x563F000ull
#define NIC4_QPC1_MAX_OFFSET 0x1000
#define NIC4_QPC1_SECTION 0x7200
#define mmNIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x563F720ull
#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x563F728ull
#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x563F730ull
#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x563F738ull
#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x563F740ull
#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x563F748ull
#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x563F750ull
#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x563F758ull
#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x563F760ull
#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x563F768ull
#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x563F770ull
#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x563F778ull
#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x563F780ull
#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x563F788ull
#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x563F790ull
#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x563F798ull
#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x563F7A0ull
#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x563F7A8ull
#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x563F7B0ull
#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x563F7B8ull
#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x563F7C0ull
#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x563F7C8ull
#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x563F7D0ull
#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x563F7D8ull
#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x563F7E0ull
#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x563F7E8ull
#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x563F7F0ull
#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x563F7F8ull
#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x563F800ull
#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x563F808ull
#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x563F810ull
#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x563F818ull
#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC4_QPC1_AXUSER_CONG_QUE_BASE 0x563FB80ull
#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_RXWQE_BASE 0x563FBE0ull
#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x563FC40ull
#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_DB_FIFO_BASE 0x563FCA0ull
#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x563FD00ull
#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x563FD60ull
#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_QPC_RESP_BASE 0x563FDC0ull
#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC4_QPC1_AXUSER_QPC_REQ_BASE 0x563FE20ull
#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC4_QPC1_SPECIAL_BASE 0x563FE80ull
#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC4_TMR_BASE 0x5648000ull
#define NIC4_TMR_MAX_OFFSET 0x1000
#define NIC4_TMR_SECTION 0xD600
#define mmNIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5648D60ull
#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC4_TMR_AXUSER_TMR_FIFO_BASE 0x5648DC0ull
#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC4_TMR_AXUSER_TMR_FSM_BASE 0x5648E20ull
#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC4_TMR_SPECIAL_BASE 0x5648E80ull
#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TMR_SPECIAL_SECTION 0x1800
#define mmNIC4_RXB_CORE_BASE 0x5649000ull
#define NIC4_RXB_CORE_MAX_OFFSET 0x1000
#define NIC4_RXB_CORE_SECTION 0x6100
#define mmNIC4_RXB_CORE_SCT_AWUSER_BASE 0x5649610ull
#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC4_RXB_CORE_SPECIAL_BASE 0x5649E80ull
#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC4_RXE0_BASE 0x564A000ull
#define NIC4_RXE0_MAX_OFFSET 0x1000
#define NIC4_RXE0_SECTION 0x9000
#define mmNIC4_RXE0_WQE_ARUSER_BASE 0x564A900ull
#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC4_RXE0_SPECIAL_BASE 0x564AE80ull
#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC4_RXE1_BASE 0x564B000ull
#define NIC4_RXE1_MAX_OFFSET 0x1000
#define NIC4_RXE1_SECTION 0x9000
#define mmNIC4_RXE1_WQE_ARUSER_BASE 0x564B900ull
#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC4_RXE1_SPECIAL_BASE 0x564BE80ull
#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x564C000ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x564C050ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x564C0A0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x564C0F0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x564C140ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x564C190ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x564C1E0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x564C230ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x564C280ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x564C2D0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x564C320ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x564C370ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x564C3C0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x564C410ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x564C460ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x564C4B0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x564C500ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x564C550ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x564C5A0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x564C5F0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x564C640ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x564C690ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x564C6E0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x564C730ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x564C780ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x564C7D0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x564C820ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x564C870ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x564C8C0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x564C910ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x564C960ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x564C9B0ull
#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC4_RXE0_AXUSER_SPECIAL_BASE 0x564CE80ull
#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x564D000ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x564D050ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x564D0A0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x564D0F0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x564D140ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x564D190ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x564D1E0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x564D230ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x564D280ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x564D2D0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x564D320ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x564D370ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x564D3C0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x564D410ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x564D460ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x564D4B0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x564D500ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x564D550ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x564D5A0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x564D5F0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x564D640ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x564D690ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x564D6E0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x564D730ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x564D780ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x564D7D0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x564D820ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x564D870ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x564D8C0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x564D910ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x564D960ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x564D9B0ull
#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC4_RXE1_AXUSER_SPECIAL_BASE 0x564DE80ull
#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC4_TXS0_BASE 0x5650000ull
#define NIC4_TXS0_MAX_OFFSET 0x1000
#define NIC4_TXS0_SECTION 0xE800
#define mmNIC4_TXS0_SPECIAL_BASE 0x5650E80ull
#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC4_TXS1_BASE 0x5651000ull
#define NIC4_TXS1_MAX_OFFSET 0x1000
#define NIC4_TXS1_SECTION 0xE800
#define mmNIC4_TXS1_SPECIAL_BASE 0x5651E80ull
#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC4_TXE0_BASE 0x5652000ull
#define NIC4_TXE0_MAX_OFFSET 0x1000
#define NIC4_TXE0_SECTION 0xE800
#define mmNIC4_TXE0_SPECIAL_BASE 0x5652E80ull
#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC4_TXE1_BASE 0x5653000ull
#define NIC4_TXE1_MAX_OFFSET 0x1000
#define NIC4_TXE1_SECTION 0xE800
#define mmNIC4_TXE1_SPECIAL_BASE 0x5653E80ull
#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC4_TXB_BASE 0x5654000ull
#define NIC4_TXB_MAX_OFFSET 0x1000
#define NIC4_TXB_SECTION 0xE800
#define mmNIC4_TXB_SPECIAL_BASE 0x5654E80ull
#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_TXB_SPECIAL_SECTION 0x1800
#define mmNIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x5655000ull
#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x5655200ull
#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x5655400ull
#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x5655600ull
#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC4_MSTR_IF_E2E_CRDT_BASE 0x5655800ull
#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC4_MSTR_IF_AXUSER_BASE 0x5655A80ull
#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC4_MSTR_IF_DBG_HBW_BASE 0x5655B00ull
#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC4_MSTR_IF_DBG_LBW_BASE 0x5655B80ull
#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC4_MSTR_IF_CORE_HBW_BASE 0x5655C00ull
#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC4_MSTR_IF_CORE_LBW_BASE 0x5655D80ull
#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC4_MSTR_IF_SPECIAL_BASE 0x5655E80ull
#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC4_TX_AXUSER_BASE 0x5656000ull
#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC4_TX_AXUSER_SECTION 0x2000
#define mmNIC4_SERDES0_BASE 0x5658000ull
#define NIC4_SERDES0_MAX_OFFSET 0x3E40
#define NIC4_SERDES0_SECTION 0x4000
#define mmNIC4_SERDES1_BASE 0x565C000ull
#define NIC4_SERDES1_MAX_OFFSET 0x3E40
#define NIC4_SERDES1_SECTION 0x4000
#define mmNIC4_PHY_BASE 0x5660000ull
#define NIC4_PHY_MAX_OFFSET 0x1000
#define NIC4_PHY_SECTION 0xE800
#define mmNIC4_PHY_SPECIAL_BASE 0x5660E80ull
#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC4_PHY_SPECIAL_SECTION 0x7180
#define mmPRT4_MAC_AUX_BASE 0x5668000ull
#define PRT4_MAC_AUX_MAX_OFFSET 0x1000
#define PRT4_MAC_AUX_SECTION 0xE800
#define mmPRT4_MAC_AUX_SPECIAL_BASE 0x5668E80ull
#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT4_MAC_CORE_BASE 0x5669000ull
#define PRT4_MAC_CORE_MAX_OFFSET 0x1000
#define PRT4_MAC_CORE_SECTION 0xE800
#define mmPRT4_MAC_CORE_SPECIAL_BASE 0x5669E80ull
#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC4_MAC_RS_FEC_BASE 0x566A000ull
#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC4_MAC_RS_FEC_SECTION 0x1000
#define mmNIC4_MAC_GLOB_STAT_CONTROL_REG_BASE 0x566B000ull
#define NIC4_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC4_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC4_MAC_GLOB_STAT_RX0_BASE 0x566B100ull
#define NIC4_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC4_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC4_MAC_GLOB_STAT_RX1_BASE 0x566B18Cull
#define NIC4_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC4_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC4_MAC_GLOB_STAT_RX2_BASE 0x566B218ull
#define NIC4_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC4_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC4_MAC_GLOB_STAT_RX3_BASE 0x566B2A4ull
#define NIC4_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC4_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC4_MAC_GLOB_STAT_TX0_BASE 0x566B330ull
#define NIC4_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC4_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC4_MAC_GLOB_STAT_TX1_BASE 0x566B398ull
#define NIC4_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC4_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC4_MAC_GLOB_STAT_TX2_BASE 0x566B400ull
#define NIC4_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC4_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC4_MAC_GLOB_STAT_TX3_BASE 0x566B468ull
#define NIC4_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC4_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC4_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x566B800ull
#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC4_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC4_MAC_CH0_MAC_PCS_BASE 0x566C000ull
#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC4_MAC_CH0_MAC_128_BASE 0x566C400ull
#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC4_MAC_CH0_MAC_AN_BASE 0x566C800ull
#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC4_MAC_CH1_MAC_PCS_BASE 0x566D000ull
#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC4_MAC_CH1_MAC_128_BASE 0x566D400ull
#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC4_MAC_CH1_MAC_AN_BASE 0x566D800ull
#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC4_MAC_CH2_MAC_PCS_BASE 0x566E000ull
#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC4_MAC_CH2_MAC_128_BASE 0x566E400ull
#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC4_MAC_CH2_MAC_AN_BASE 0x566E800ull
#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC4_MAC_CH3_MAC_PCS_BASE 0x566F000ull
#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC4_MAC_CH3_MAC_128_BASE 0x566F400ull
#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC4_MAC_CH3_MAC_AN_BASE 0x566F800ull
#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5680000ull
#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5680080ull
#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5680100ull
#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5680180ull
#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_0_SPECIAL_BASE 0x5680E80ull
#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5681000ull
#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5681080ull
#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5681100ull
#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5681180ull
#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_1_SPECIAL_BASE 0x5681E80ull
#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5682000ull
#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5682080ull
#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5682100ull
#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5682180ull
#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_2_SPECIAL_BASE 0x5682E80ull
#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5683000ull
#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5683080ull
#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5683100ull
#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5683180ull
#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_3_SPECIAL_BASE 0x5683E80ull
#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5684000ull
#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5684080ull
#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5684100ull
#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5684180ull
#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_4_SPECIAL_BASE 0x5684E80ull
#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5685000ull
#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5685080ull
#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5685100ull
#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5685180ull
#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_5_SPECIAL_BASE 0x5685E80ull
#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5686000ull
#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5686080ull
#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5686100ull
#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5686180ull
#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_6_SPECIAL_BASE 0x5686E80ull
#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5687000ull
#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5687080ull
#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5687100ull
#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5687180ull
#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_7_SPECIAL_BASE 0x5687E80ull
#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5688000ull
#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5688080ull
#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5688100ull
#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5688180ull
#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_8_SPECIAL_BASE 0x5688E80ull
#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5689000ull
#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5689080ull
#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5689100ull
#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5689180ull
#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_9_SPECIAL_BASE 0x5689E80ull
#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x568A000ull
#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x568A080ull
#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x568A100ull
#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x568A180ull
#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_10_SPECIAL_BASE 0x568AE80ull
#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x568B000ull
#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x568B080ull
#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x568B100ull
#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x568B180ull
#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_11_SPECIAL_BASE 0x568BE80ull
#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x568C000ull
#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x568C080ull
#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x568C100ull
#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x568C180ull
#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_12_SPECIAL_BASE 0x568CE80ull
#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x568D000ull
#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x568D080ull
#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x568D100ull
#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x568D180ull
#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_13_SPECIAL_BASE 0x568DE80ull
#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x568E000ull
#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x568E080ull
#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x568E100ull
#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x568E180ull
#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR0_14_SPECIAL_BASE 0x568EE80ull
#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC5_QM_DCCM0_BASE 0x5690000ull
#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC5_QM_DCCM0_SECTION 0x8000
#define mmNIC5_QM_ARC_AUX0_BASE 0x5698000ull
#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC5_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC5_QM_ARC_AUX0_SPECIAL_BASE 0x5698E80ull
#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC5_QM0_BASE 0x569A000ull
#define NIC5_QM0_MAX_OFFSET 0x1000
#define NIC5_QM0_SECTION 0x9000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x569A900ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x569A908ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x569A910ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x569A918ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x569A920ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x569A928ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x569A930ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x569A938ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x569A940ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x569A948ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x569A950ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x569A958ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x569A960ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x569A968ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x569A970ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x569A978ull
#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC5_QM0_AXUSER_SECURED_BASE 0x569AB00ull
#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC5_QM0_AXUSER_NONSECURED_BASE 0x569AB80ull
#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC5_QM0_DBG_HBW_BASE 0x569AC00ull
#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC5_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC5_QM0_DBG_LBW_BASE 0x569AC80ull
#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC5_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC5_QM0_CGM_BASE 0x569AD80ull
#define NIC5_QM0_CGM_MAX_OFFSET 0xC000
#define NIC5_QM0_CGM_SECTION 0x1000
#define mmNIC5_QM0_SPECIAL_BASE 0x569AE80ull
#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QM0_SPECIAL_SECTION 0x4180
#define mmNIC5_QPC0_BASE 0x569F000ull
#define NIC5_QPC0_MAX_OFFSET 0x1000
#define NIC5_QPC0_SECTION 0x7200
#define mmNIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x569F720ull
#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x569F728ull
#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x569F730ull
#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x569F738ull
#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x569F740ull
#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x569F748ull
#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x569F750ull
#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x569F758ull
#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x569F760ull
#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x569F768ull
#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x569F770ull
#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x569F778ull
#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x569F780ull
#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x569F788ull
#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x569F790ull
#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x569F798ull
#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x569F7A0ull
#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x569F7A8ull
#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x569F7B0ull
#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x569F7B8ull
#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x569F7C0ull
#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x569F7C8ull
#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x569F7D0ull
#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x569F7D8ull
#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x569F7E0ull
#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x569F7E8ull
#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x569F7F0ull
#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x569F7F8ull
#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x569F800ull
#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x569F808ull
#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x569F810ull
#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x569F818ull
#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC5_QPC0_AXUSER_CONG_QUE_BASE 0x569FB80ull
#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_RXWQE_BASE 0x569FBE0ull
#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x569FC40ull
#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_DB_FIFO_BASE 0x569FCA0ull
#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x569FD00ull
#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x569FD60ull
#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_QPC_RESP_BASE 0x569FDC0ull
#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC5_QPC0_AXUSER_QPC_REQ_BASE 0x569FE20ull
#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC5_QPC0_SPECIAL_BASE 0x569FE80ull
#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x56A0000ull
#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x56A0080ull
#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x56A0100ull
#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x56A0180ull
#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_0_SPECIAL_BASE 0x56A0E80ull
#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x56A1000ull
#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x56A1080ull
#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x56A1100ull
#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x56A1180ull
#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_1_SPECIAL_BASE 0x56A1E80ull
#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x56A2000ull
#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x56A2080ull
#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x56A2100ull
#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x56A2180ull
#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_2_SPECIAL_BASE 0x56A2E80ull
#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x56A3000ull
#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x56A3080ull
#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x56A3100ull
#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x56A3180ull
#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_3_SPECIAL_BASE 0x56A3E80ull
#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x56A4000ull
#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x56A4080ull
#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x56A4100ull
#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x56A4180ull
#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_4_SPECIAL_BASE 0x56A4E80ull
#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x56A5000ull
#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x56A5080ull
#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x56A5100ull
#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x56A5180ull
#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_5_SPECIAL_BASE 0x56A5E80ull
#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x56A6000ull
#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x56A6080ull
#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x56A6100ull
#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x56A6180ull
#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_6_SPECIAL_BASE 0x56A6E80ull
#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x56A7000ull
#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x56A7080ull
#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x56A7100ull
#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x56A7180ull
#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_7_SPECIAL_BASE 0x56A7E80ull
#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x56A8000ull
#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x56A8080ull
#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x56A8100ull
#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x56A8180ull
#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_8_SPECIAL_BASE 0x56A8E80ull
#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x56A9000ull
#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x56A9080ull
#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x56A9100ull
#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x56A9180ull
#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_9_SPECIAL_BASE 0x56A9E80ull
#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x56AA000ull
#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x56AA080ull
#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x56AA100ull
#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x56AA180ull
#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_10_SPECIAL_BASE 0x56AAE80ull
#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x56AB000ull
#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x56AB080ull
#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x56AB100ull
#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x56AB180ull
#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_11_SPECIAL_BASE 0x56ABE80ull
#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x56AC000ull
#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x56AC080ull
#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x56AC100ull
#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x56AC180ull
#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_12_SPECIAL_BASE 0x56ACE80ull
#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x56AD000ull
#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x56AD080ull
#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x56AD100ull
#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x56AD180ull
#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_13_SPECIAL_BASE 0x56ADE80ull
#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x56AE000ull
#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x56AE080ull
#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x56AE100ull
#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x56AE180ull
#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC5_UMR1_14_SPECIAL_BASE 0x56AEE80ull
#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC5_QM_DCCM1_BASE 0x56B0000ull
#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC5_QM_DCCM1_SECTION 0x8000
#define mmNIC5_QM_ARC_AUX1_BASE 0x56B8000ull
#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC5_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC5_QM_ARC_AUX1_SPECIAL_BASE 0x56B8E80ull
#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC5_QM1_BASE 0x56BA000ull
#define NIC5_QM1_MAX_OFFSET 0x1000
#define NIC5_QM1_SECTION 0x9000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x56BA900ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x56BA908ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x56BA910ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x56BA918ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x56BA920ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x56BA928ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x56BA930ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x56BA938ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x56BA940ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x56BA948ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x56BA950ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x56BA958ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x56BA960ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x56BA968ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x56BA970ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x56BA978ull
#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC5_QM1_AXUSER_SECURED_BASE 0x56BAB00ull
#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC5_QM1_AXUSER_NONSECURED_BASE 0x56BAB80ull
#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC5_QM1_DBG_HBW_BASE 0x56BAC00ull
#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC5_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC5_QM1_DBG_LBW_BASE 0x56BAC80ull
#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC5_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC5_QM1_CGM_BASE 0x56BAD80ull
#define NIC5_QM1_CGM_MAX_OFFSET 0xC000
#define NIC5_QM1_CGM_SECTION 0x1000
#define mmNIC5_QM1_SPECIAL_BASE 0x56BAE80ull
#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QM1_SPECIAL_SECTION 0x4180
#define mmNIC5_QPC1_BASE 0x56BF000ull
#define NIC5_QPC1_MAX_OFFSET 0x1000
#define NIC5_QPC1_SECTION 0x7200
#define mmNIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x56BF720ull
#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x56BF728ull
#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x56BF730ull
#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x56BF738ull
#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x56BF740ull
#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x56BF748ull
#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x56BF750ull
#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x56BF758ull
#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x56BF760ull
#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x56BF768ull
#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x56BF770ull
#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x56BF778ull
#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x56BF780ull
#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x56BF788ull
#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x56BF790ull
#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x56BF798ull
#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x56BF7A0ull
#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x56BF7A8ull
#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x56BF7B0ull
#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x56BF7B8ull
#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x56BF7C0ull
#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x56BF7C8ull
#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x56BF7D0ull
#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x56BF7D8ull
#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x56BF7E0ull
#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x56BF7E8ull
#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x56BF7F0ull
#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x56BF7F8ull
#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x56BF800ull
#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x56BF808ull
#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x56BF810ull
#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x56BF818ull
#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC5_QPC1_AXUSER_CONG_QUE_BASE 0x56BFB80ull
#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_RXWQE_BASE 0x56BFBE0ull
#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x56BFC40ull
#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_DB_FIFO_BASE 0x56BFCA0ull
#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x56BFD00ull
#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x56BFD60ull
#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_QPC_RESP_BASE 0x56BFDC0ull
#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC5_QPC1_AXUSER_QPC_REQ_BASE 0x56BFE20ull
#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC5_QPC1_SPECIAL_BASE 0x56BFE80ull
#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC5_TMR_BASE 0x56C8000ull
#define NIC5_TMR_MAX_OFFSET 0x1000
#define NIC5_TMR_SECTION 0xD600
#define mmNIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x56C8D60ull
#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC5_TMR_AXUSER_TMR_FIFO_BASE 0x56C8DC0ull
#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC5_TMR_AXUSER_TMR_FSM_BASE 0x56C8E20ull
#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC5_TMR_SPECIAL_BASE 0x56C8E80ull
#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TMR_SPECIAL_SECTION 0x1800
#define mmNIC5_RXB_CORE_BASE 0x56C9000ull
#define NIC5_RXB_CORE_MAX_OFFSET 0x1000
#define NIC5_RXB_CORE_SECTION 0x6100
#define mmNIC5_RXB_CORE_SCT_AWUSER_BASE 0x56C9610ull
#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC5_RXB_CORE_SPECIAL_BASE 0x56C9E80ull
#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC5_RXE0_BASE 0x56CA000ull
#define NIC5_RXE0_MAX_OFFSET 0x1000
#define NIC5_RXE0_SECTION 0x9000
#define mmNIC5_RXE0_WQE_ARUSER_BASE 0x56CA900ull
#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC5_RXE0_SPECIAL_BASE 0x56CAE80ull
#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC5_RXE1_BASE 0x56CB000ull
#define NIC5_RXE1_MAX_OFFSET 0x1000
#define NIC5_RXE1_SECTION 0x9000
#define mmNIC5_RXE1_WQE_ARUSER_BASE 0x56CB900ull
#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC5_RXE1_SPECIAL_BASE 0x56CBE80ull
#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x56CC000ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x56CC050ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x56CC0A0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x56CC0F0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x56CC140ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x56CC190ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x56CC1E0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x56CC230ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x56CC280ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x56CC2D0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x56CC320ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x56CC370ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x56CC3C0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x56CC410ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x56CC460ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x56CC4B0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x56CC500ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x56CC550ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x56CC5A0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x56CC5F0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x56CC640ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x56CC690ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x56CC6E0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x56CC730ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x56CC780ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x56CC7D0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x56CC820ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x56CC870ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x56CC8C0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x56CC910ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x56CC960ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x56CC9B0ull
#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC5_RXE0_AXUSER_SPECIAL_BASE 0x56CCE80ull
#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x56CD000ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x56CD050ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x56CD0A0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x56CD0F0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x56CD140ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x56CD190ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x56CD1E0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x56CD230ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x56CD280ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x56CD2D0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x56CD320ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x56CD370ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x56CD3C0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x56CD410ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x56CD460ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x56CD4B0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x56CD500ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x56CD550ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x56CD5A0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x56CD5F0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x56CD640ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x56CD690ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x56CD6E0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x56CD730ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x56CD780ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x56CD7D0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x56CD820ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x56CD870ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x56CD8C0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x56CD910ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x56CD960ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x56CD9B0ull
#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC5_RXE1_AXUSER_SPECIAL_BASE 0x56CDE80ull
#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC5_TXS0_BASE 0x56D0000ull
#define NIC5_TXS0_MAX_OFFSET 0x1000
#define NIC5_TXS0_SECTION 0xE800
#define mmNIC5_TXS0_SPECIAL_BASE 0x56D0E80ull
#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC5_TXS1_BASE 0x56D1000ull
#define NIC5_TXS1_MAX_OFFSET 0x1000
#define NIC5_TXS1_SECTION 0xE800
#define mmNIC5_TXS1_SPECIAL_BASE 0x56D1E80ull
#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC5_TXE0_BASE 0x56D2000ull
#define NIC5_TXE0_MAX_OFFSET 0x1000
#define NIC5_TXE0_SECTION 0xE800
#define mmNIC5_TXE0_SPECIAL_BASE 0x56D2E80ull
#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC5_TXE1_BASE 0x56D3000ull
#define NIC5_TXE1_MAX_OFFSET 0x1000
#define NIC5_TXE1_SECTION 0xE800
#define mmNIC5_TXE1_SPECIAL_BASE 0x56D3E80ull
#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC5_TXB_BASE 0x56D4000ull
#define NIC5_TXB_MAX_OFFSET 0x1000
#define NIC5_TXB_SECTION 0xE800
#define mmNIC5_TXB_SPECIAL_BASE 0x56D4E80ull
#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_TXB_SPECIAL_SECTION 0x1800
#define mmNIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x56D5000ull
#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x56D5200ull
#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x56D5400ull
#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x56D5600ull
#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC5_MSTR_IF_E2E_CRDT_BASE 0x56D5800ull
#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC5_MSTR_IF_AXUSER_BASE 0x56D5A80ull
#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC5_MSTR_IF_DBG_HBW_BASE 0x56D5B00ull
#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC5_MSTR_IF_DBG_LBW_BASE 0x56D5B80ull
#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC5_MSTR_IF_CORE_HBW_BASE 0x56D5C00ull
#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC5_MSTR_IF_CORE_LBW_BASE 0x56D5D80ull
#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC5_MSTR_IF_SPECIAL_BASE 0x56D5E80ull
#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC5_TX_AXUSER_BASE 0x56D6000ull
#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC5_TX_AXUSER_SECTION 0x2000
#define mmNIC5_SERDES0_BASE 0x56D8000ull
#define NIC5_SERDES0_MAX_OFFSET 0x3E40
#define NIC5_SERDES0_SECTION 0x4000
#define mmNIC5_SERDES1_BASE 0x56DC000ull
#define NIC5_SERDES1_MAX_OFFSET 0x3E40
#define NIC5_SERDES1_SECTION 0x4000
#define mmNIC5_PHY_BASE 0x56E0000ull
#define NIC5_PHY_MAX_OFFSET 0x1000
#define NIC5_PHY_SECTION 0xE800
#define mmNIC5_PHY_SPECIAL_BASE 0x56E0E80ull
#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC5_PHY_SPECIAL_SECTION 0x7180
#define mmPRT5_MAC_AUX_BASE 0x56E8000ull
#define PRT5_MAC_AUX_MAX_OFFSET 0x1000
#define PRT5_MAC_AUX_SECTION 0xE800
#define mmPRT5_MAC_AUX_SPECIAL_BASE 0x56E8E80ull
#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT5_MAC_CORE_BASE 0x56E9000ull
#define PRT5_MAC_CORE_MAX_OFFSET 0x1000
#define PRT5_MAC_CORE_SECTION 0xE800
#define mmPRT5_MAC_CORE_SPECIAL_BASE 0x56E9E80ull
#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC5_MAC_RS_FEC_BASE 0x56EA000ull
#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC5_MAC_RS_FEC_SECTION 0x1000
#define mmNIC5_MAC_GLOB_STAT_CONTROL_REG_BASE 0x56EB000ull
#define NIC5_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC5_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC5_MAC_GLOB_STAT_RX0_BASE 0x56EB100ull
#define NIC5_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC5_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC5_MAC_GLOB_STAT_RX1_BASE 0x56EB18Cull
#define NIC5_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC5_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC5_MAC_GLOB_STAT_RX2_BASE 0x56EB218ull
#define NIC5_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC5_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC5_MAC_GLOB_STAT_RX3_BASE 0x56EB2A4ull
#define NIC5_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC5_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC5_MAC_GLOB_STAT_TX0_BASE 0x56EB330ull
#define NIC5_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC5_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC5_MAC_GLOB_STAT_TX1_BASE 0x56EB398ull
#define NIC5_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC5_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC5_MAC_GLOB_STAT_TX2_BASE 0x56EB400ull
#define NIC5_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC5_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC5_MAC_GLOB_STAT_TX3_BASE 0x56EB468ull
#define NIC5_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC5_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC5_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x56EB800ull
#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC5_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC5_MAC_CH0_MAC_PCS_BASE 0x56EC000ull
#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC5_MAC_CH0_MAC_128_BASE 0x56EC400ull
#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC5_MAC_CH0_MAC_AN_BASE 0x56EC800ull
#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC5_MAC_CH1_MAC_PCS_BASE 0x56ED000ull
#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC5_MAC_CH1_MAC_128_BASE 0x56ED400ull
#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC5_MAC_CH1_MAC_AN_BASE 0x56ED800ull
#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC5_MAC_CH2_MAC_PCS_BASE 0x56EE000ull
#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC5_MAC_CH2_MAC_128_BASE 0x56EE400ull
#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC5_MAC_CH2_MAC_AN_BASE 0x56EE800ull
#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC5_MAC_CH3_MAC_PCS_BASE 0x56EF000ull
#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC5_MAC_CH3_MAC_128_BASE 0x56EF400ull
#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC5_MAC_CH3_MAC_AN_BASE 0x56EF800ull
#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5700000ull
#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5700080ull
#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5700100ull
#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5700180ull
#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_0_SPECIAL_BASE 0x5700E80ull
#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5701000ull
#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5701080ull
#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5701100ull
#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5701180ull
#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_1_SPECIAL_BASE 0x5701E80ull
#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5702000ull
#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5702080ull
#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5702100ull
#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5702180ull
#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_2_SPECIAL_BASE 0x5702E80ull
#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5703000ull
#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5703080ull
#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5703100ull
#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5703180ull
#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_3_SPECIAL_BASE 0x5703E80ull
#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5704000ull
#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5704080ull
#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5704100ull
#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5704180ull
#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_4_SPECIAL_BASE 0x5704E80ull
#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5705000ull
#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5705080ull
#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5705100ull
#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5705180ull
#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_5_SPECIAL_BASE 0x5705E80ull
#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5706000ull
#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5706080ull
#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5706100ull
#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5706180ull
#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_6_SPECIAL_BASE 0x5706E80ull
#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5707000ull
#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5707080ull
#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5707100ull
#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5707180ull
#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_7_SPECIAL_BASE 0x5707E80ull
#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5708000ull
#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5708080ull
#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5708100ull
#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5708180ull
#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_8_SPECIAL_BASE 0x5708E80ull
#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5709000ull
#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5709080ull
#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5709100ull
#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5709180ull
#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_9_SPECIAL_BASE 0x5709E80ull
#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x570A000ull
#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x570A080ull
#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x570A100ull
#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x570A180ull
#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_10_SPECIAL_BASE 0x570AE80ull
#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x570B000ull
#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x570B080ull
#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x570B100ull
#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x570B180ull
#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_11_SPECIAL_BASE 0x570BE80ull
#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x570C000ull
#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x570C080ull
#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x570C100ull
#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x570C180ull
#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_12_SPECIAL_BASE 0x570CE80ull
#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x570D000ull
#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x570D080ull
#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x570D100ull
#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x570D180ull
#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_13_SPECIAL_BASE 0x570DE80ull
#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x570E000ull
#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x570E080ull
#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x570E100ull
#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x570E180ull
#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR0_14_SPECIAL_BASE 0x570EE80ull
#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC6_QM_DCCM0_BASE 0x5710000ull
#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC6_QM_DCCM0_SECTION 0x8000
#define mmNIC6_QM_ARC_AUX0_BASE 0x5718000ull
#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC6_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC6_QM_ARC_AUX0_SPECIAL_BASE 0x5718E80ull
#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC6_QM0_BASE 0x571A000ull
#define NIC6_QM0_MAX_OFFSET 0x1000
#define NIC6_QM0_SECTION 0x9000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x571A900ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x571A908ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x571A910ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x571A918ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x571A920ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x571A928ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x571A930ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x571A938ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x571A940ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x571A948ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x571A950ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x571A958ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x571A960ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x571A968ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x571A970ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x571A978ull
#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC6_QM0_AXUSER_SECURED_BASE 0x571AB00ull
#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC6_QM0_AXUSER_NONSECURED_BASE 0x571AB80ull
#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC6_QM0_DBG_HBW_BASE 0x571AC00ull
#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC6_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC6_QM0_DBG_LBW_BASE 0x571AC80ull
#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC6_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC6_QM0_CGM_BASE 0x571AD80ull
#define NIC6_QM0_CGM_MAX_OFFSET 0xC000
#define NIC6_QM0_CGM_SECTION 0x1000
#define mmNIC6_QM0_SPECIAL_BASE 0x571AE80ull
#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QM0_SPECIAL_SECTION 0x4180
#define mmNIC6_QPC0_BASE 0x571F000ull
#define NIC6_QPC0_MAX_OFFSET 0x1000
#define NIC6_QPC0_SECTION 0x7200
#define mmNIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x571F720ull
#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x571F728ull
#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x571F730ull
#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x571F738ull
#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x571F740ull
#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x571F748ull
#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x571F750ull
#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x571F758ull
#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x571F760ull
#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x571F768ull
#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x571F770ull
#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x571F778ull
#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x571F780ull
#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x571F788ull
#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x571F790ull
#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x571F798ull
#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x571F7A0ull
#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x571F7A8ull
#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x571F7B0ull
#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x571F7B8ull
#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x571F7C0ull
#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x571F7C8ull
#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x571F7D0ull
#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x571F7D8ull
#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x571F7E0ull
#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x571F7E8ull
#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x571F7F0ull
#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x571F7F8ull
#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x571F800ull
#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x571F808ull
#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x571F810ull
#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x571F818ull
#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC6_QPC0_AXUSER_CONG_QUE_BASE 0x571FB80ull
#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_RXWQE_BASE 0x571FBE0ull
#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x571FC40ull
#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_DB_FIFO_BASE 0x571FCA0ull
#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x571FD00ull
#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x571FD60ull
#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_QPC_RESP_BASE 0x571FDC0ull
#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC6_QPC0_AXUSER_QPC_REQ_BASE 0x571FE20ull
#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC6_QPC0_SPECIAL_BASE 0x571FE80ull
#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5720000ull
#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5720080ull
#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5720100ull
#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5720180ull
#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_0_SPECIAL_BASE 0x5720E80ull
#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5721000ull
#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5721080ull
#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5721100ull
#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5721180ull
#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_1_SPECIAL_BASE 0x5721E80ull
#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5722000ull
#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5722080ull
#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5722100ull
#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5722180ull
#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_2_SPECIAL_BASE 0x5722E80ull
#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5723000ull
#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5723080ull
#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5723100ull
#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5723180ull
#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_3_SPECIAL_BASE 0x5723E80ull
#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5724000ull
#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5724080ull
#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5724100ull
#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5724180ull
#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_4_SPECIAL_BASE 0x5724E80ull
#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5725000ull
#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5725080ull
#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5725100ull
#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5725180ull
#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_5_SPECIAL_BASE 0x5725E80ull
#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5726000ull
#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5726080ull
#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5726100ull
#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5726180ull
#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_6_SPECIAL_BASE 0x5726E80ull
#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5727000ull
#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5727080ull
#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5727100ull
#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5727180ull
#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_7_SPECIAL_BASE 0x5727E80ull
#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5728000ull
#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5728080ull
#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5728100ull
#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5728180ull
#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_8_SPECIAL_BASE 0x5728E80ull
#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5729000ull
#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5729080ull
#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5729100ull
#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5729180ull
#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_9_SPECIAL_BASE 0x5729E80ull
#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x572A000ull
#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x572A080ull
#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x572A100ull
#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x572A180ull
#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_10_SPECIAL_BASE 0x572AE80ull
#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x572B000ull
#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x572B080ull
#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x572B100ull
#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x572B180ull
#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_11_SPECIAL_BASE 0x572BE80ull
#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x572C000ull
#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x572C080ull
#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x572C100ull
#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x572C180ull
#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_12_SPECIAL_BASE 0x572CE80ull
#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x572D000ull
#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x572D080ull
#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x572D100ull
#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x572D180ull
#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_13_SPECIAL_BASE 0x572DE80ull
#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x572E000ull
#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x572E080ull
#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x572E100ull
#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x572E180ull
#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC6_UMR1_14_SPECIAL_BASE 0x572EE80ull
#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC6_QM_DCCM1_BASE 0x5730000ull
#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC6_QM_DCCM1_SECTION 0x8000
#define mmNIC6_QM_ARC_AUX1_BASE 0x5738000ull
#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC6_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC6_QM_ARC_AUX1_SPECIAL_BASE 0x5738E80ull
#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC6_QM1_BASE 0x573A000ull
#define NIC6_QM1_MAX_OFFSET 0x1000
#define NIC6_QM1_SECTION 0x9000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x573A900ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x573A908ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x573A910ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x573A918ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x573A920ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x573A928ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x573A930ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x573A938ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x573A940ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x573A948ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x573A950ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x573A958ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x573A960ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x573A968ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x573A970ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x573A978ull
#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC6_QM1_AXUSER_SECURED_BASE 0x573AB00ull
#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC6_QM1_AXUSER_NONSECURED_BASE 0x573AB80ull
#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC6_QM1_DBG_HBW_BASE 0x573AC00ull
#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC6_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC6_QM1_DBG_LBW_BASE 0x573AC80ull
#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC6_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC6_QM1_CGM_BASE 0x573AD80ull
#define NIC6_QM1_CGM_MAX_OFFSET 0xC000
#define NIC6_QM1_CGM_SECTION 0x1000
#define mmNIC6_QM1_SPECIAL_BASE 0x573AE80ull
#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QM1_SPECIAL_SECTION 0x4180
#define mmNIC6_QPC1_BASE 0x573F000ull
#define NIC6_QPC1_MAX_OFFSET 0x1000
#define NIC6_QPC1_SECTION 0x7200
#define mmNIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x573F720ull
#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x573F728ull
#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x573F730ull
#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x573F738ull
#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x573F740ull
#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x573F748ull
#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x573F750ull
#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x573F758ull
#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x573F760ull
#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x573F768ull
#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x573F770ull
#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x573F778ull
#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x573F780ull
#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x573F788ull
#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x573F790ull
#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x573F798ull
#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x573F7A0ull
#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x573F7A8ull
#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x573F7B0ull
#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x573F7B8ull
#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x573F7C0ull
#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x573F7C8ull
#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x573F7D0ull
#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x573F7D8ull
#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x573F7E0ull
#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x573F7E8ull
#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x573F7F0ull
#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x573F7F8ull
#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x573F800ull
#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x573F808ull
#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x573F810ull
#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x573F818ull
#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC6_QPC1_AXUSER_CONG_QUE_BASE 0x573FB80ull
#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_RXWQE_BASE 0x573FBE0ull
#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x573FC40ull
#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_DB_FIFO_BASE 0x573FCA0ull
#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x573FD00ull
#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x573FD60ull
#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_QPC_RESP_BASE 0x573FDC0ull
#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC6_QPC1_AXUSER_QPC_REQ_BASE 0x573FE20ull
#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC6_QPC1_SPECIAL_BASE 0x573FE80ull
#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC6_TMR_BASE 0x5748000ull
#define NIC6_TMR_MAX_OFFSET 0x1000
#define NIC6_TMR_SECTION 0xD600
#define mmNIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5748D60ull
#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC6_TMR_AXUSER_TMR_FIFO_BASE 0x5748DC0ull
#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC6_TMR_AXUSER_TMR_FSM_BASE 0x5748E20ull
#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC6_TMR_SPECIAL_BASE 0x5748E80ull
#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TMR_SPECIAL_SECTION 0x1800
#define mmNIC6_RXB_CORE_BASE 0x5749000ull
#define NIC6_RXB_CORE_MAX_OFFSET 0x1000
#define NIC6_RXB_CORE_SECTION 0x6100
#define mmNIC6_RXB_CORE_SCT_AWUSER_BASE 0x5749610ull
#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC6_RXB_CORE_SPECIAL_BASE 0x5749E80ull
#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC6_RXE0_BASE 0x574A000ull
#define NIC6_RXE0_MAX_OFFSET 0x1000
#define NIC6_RXE0_SECTION 0x9000
#define mmNIC6_RXE0_WQE_ARUSER_BASE 0x574A900ull
#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC6_RXE0_SPECIAL_BASE 0x574AE80ull
#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC6_RXE1_BASE 0x574B000ull
#define NIC6_RXE1_MAX_OFFSET 0x1000
#define NIC6_RXE1_SECTION 0x9000
#define mmNIC6_RXE1_WQE_ARUSER_BASE 0x574B900ull
#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC6_RXE1_SPECIAL_BASE 0x574BE80ull
#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x574C000ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x574C050ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x574C0A0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x574C0F0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x574C140ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x574C190ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x574C1E0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x574C230ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x574C280ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x574C2D0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x574C320ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x574C370ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x574C3C0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x574C410ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x574C460ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x574C4B0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x574C500ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x574C550ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x574C5A0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x574C5F0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x574C640ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x574C690ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x574C6E0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x574C730ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x574C780ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x574C7D0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x574C820ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x574C870ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x574C8C0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x574C910ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x574C960ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x574C9B0ull
#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC6_RXE0_AXUSER_SPECIAL_BASE 0x574CE80ull
#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x574D000ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x574D050ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x574D0A0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x574D0F0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x574D140ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x574D190ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x574D1E0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x574D230ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x574D280ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x574D2D0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x574D320ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x574D370ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x574D3C0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x574D410ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x574D460ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x574D4B0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x574D500ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x574D550ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x574D5A0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x574D5F0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x574D640ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x574D690ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x574D6E0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x574D730ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x574D780ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x574D7D0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x574D820ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x574D870ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x574D8C0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x574D910ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x574D960ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x574D9B0ull
#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC6_RXE1_AXUSER_SPECIAL_BASE 0x574DE80ull
#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC6_TXS0_BASE 0x5750000ull
#define NIC6_TXS0_MAX_OFFSET 0x1000
#define NIC6_TXS0_SECTION 0xE800
#define mmNIC6_TXS0_SPECIAL_BASE 0x5750E80ull
#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC6_TXS1_BASE 0x5751000ull
#define NIC6_TXS1_MAX_OFFSET 0x1000
#define NIC6_TXS1_SECTION 0xE800
#define mmNIC6_TXS1_SPECIAL_BASE 0x5751E80ull
#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC6_TXE0_BASE 0x5752000ull
#define NIC6_TXE0_MAX_OFFSET 0x1000
#define NIC6_TXE0_SECTION 0xE800
#define mmNIC6_TXE0_SPECIAL_BASE 0x5752E80ull
#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC6_TXE1_BASE 0x5753000ull
#define NIC6_TXE1_MAX_OFFSET 0x1000
#define NIC6_TXE1_SECTION 0xE800
#define mmNIC6_TXE1_SPECIAL_BASE 0x5753E80ull
#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC6_TXB_BASE 0x5754000ull
#define NIC6_TXB_MAX_OFFSET 0x1000
#define NIC6_TXB_SECTION 0xE800
#define mmNIC6_TXB_SPECIAL_BASE 0x5754E80ull
#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_TXB_SPECIAL_SECTION 0x1800
#define mmNIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x5755000ull
#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x5755200ull
#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x5755400ull
#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x5755600ull
#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC6_MSTR_IF_E2E_CRDT_BASE 0x5755800ull
#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC6_MSTR_IF_AXUSER_BASE 0x5755A80ull
#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC6_MSTR_IF_DBG_HBW_BASE 0x5755B00ull
#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC6_MSTR_IF_DBG_LBW_BASE 0x5755B80ull
#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC6_MSTR_IF_CORE_HBW_BASE 0x5755C00ull
#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC6_MSTR_IF_CORE_LBW_BASE 0x5755D80ull
#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC6_MSTR_IF_SPECIAL_BASE 0x5755E80ull
#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC6_TX_AXUSER_BASE 0x5756000ull
#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC6_TX_AXUSER_SECTION 0x2000
#define mmNIC6_SERDES0_BASE 0x5758000ull
#define NIC6_SERDES0_MAX_OFFSET 0x3E40
#define NIC6_SERDES0_SECTION 0x4000
#define mmNIC6_SERDES1_BASE 0x575C000ull
#define NIC6_SERDES1_MAX_OFFSET 0x3E40
#define NIC6_SERDES1_SECTION 0x4000
#define mmNIC6_PHY_BASE 0x5760000ull
#define NIC6_PHY_MAX_OFFSET 0x1000
#define NIC6_PHY_SECTION 0xE800
#define mmNIC6_PHY_SPECIAL_BASE 0x5760E80ull
#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC6_PHY_SPECIAL_SECTION 0x7180
#define mmPRT6_MAC_AUX_BASE 0x5768000ull
#define PRT6_MAC_AUX_MAX_OFFSET 0x1000
#define PRT6_MAC_AUX_SECTION 0xE800
#define mmPRT6_MAC_AUX_SPECIAL_BASE 0x5768E80ull
#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT6_MAC_CORE_BASE 0x5769000ull
#define PRT6_MAC_CORE_MAX_OFFSET 0x1000
#define PRT6_MAC_CORE_SECTION 0xE800
#define mmPRT6_MAC_CORE_SPECIAL_BASE 0x5769E80ull
#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC6_MAC_RS_FEC_BASE 0x576A000ull
#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC6_MAC_RS_FEC_SECTION 0x1000
#define mmNIC6_MAC_GLOB_STAT_CONTROL_REG_BASE 0x576B000ull
#define NIC6_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC6_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC6_MAC_GLOB_STAT_RX0_BASE 0x576B100ull
#define NIC6_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC6_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC6_MAC_GLOB_STAT_RX1_BASE 0x576B18Cull
#define NIC6_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC6_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC6_MAC_GLOB_STAT_RX2_BASE 0x576B218ull
#define NIC6_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC6_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC6_MAC_GLOB_STAT_RX3_BASE 0x576B2A4ull
#define NIC6_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC6_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC6_MAC_GLOB_STAT_TX0_BASE 0x576B330ull
#define NIC6_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC6_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC6_MAC_GLOB_STAT_TX1_BASE 0x576B398ull
#define NIC6_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC6_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC6_MAC_GLOB_STAT_TX2_BASE 0x576B400ull
#define NIC6_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC6_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC6_MAC_GLOB_STAT_TX3_BASE 0x576B468ull
#define NIC6_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC6_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC6_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x576B800ull
#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC6_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC6_MAC_CH0_MAC_PCS_BASE 0x576C000ull
#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC6_MAC_CH0_MAC_128_BASE 0x576C400ull
#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC6_MAC_CH0_MAC_AN_BASE 0x576C800ull
#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC6_MAC_CH1_MAC_PCS_BASE 0x576D000ull
#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC6_MAC_CH1_MAC_128_BASE 0x576D400ull
#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC6_MAC_CH1_MAC_AN_BASE 0x576D800ull
#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC6_MAC_CH2_MAC_PCS_BASE 0x576E000ull
#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC6_MAC_CH2_MAC_128_BASE 0x576E400ull
#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC6_MAC_CH2_MAC_AN_BASE 0x576E800ull
#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC6_MAC_CH3_MAC_PCS_BASE 0x576F000ull
#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC6_MAC_CH3_MAC_128_BASE 0x576F400ull
#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC6_MAC_CH3_MAC_AN_BASE 0x576F800ull
#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5780000ull
#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5780080ull
#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5780100ull
#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5780180ull
#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_0_SPECIAL_BASE 0x5780E80ull
#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5781000ull
#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5781080ull
#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5781100ull
#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5781180ull
#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_1_SPECIAL_BASE 0x5781E80ull
#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5782000ull
#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5782080ull
#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5782100ull
#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5782180ull
#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_2_SPECIAL_BASE 0x5782E80ull
#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5783000ull
#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5783080ull
#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5783100ull
#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5783180ull
#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_3_SPECIAL_BASE 0x5783E80ull
#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5784000ull
#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5784080ull
#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5784100ull
#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5784180ull
#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_4_SPECIAL_BASE 0x5784E80ull
#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5785000ull
#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5785080ull
#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5785100ull
#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5785180ull
#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_5_SPECIAL_BASE 0x5785E80ull
#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5786000ull
#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5786080ull
#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5786100ull
#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5786180ull
#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_6_SPECIAL_BASE 0x5786E80ull
#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5787000ull
#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5787080ull
#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5787100ull
#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5787180ull
#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_7_SPECIAL_BASE 0x5787E80ull
#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5788000ull
#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5788080ull
#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5788100ull
#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5788180ull
#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_8_SPECIAL_BASE 0x5788E80ull
#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5789000ull
#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5789080ull
#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5789100ull
#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5789180ull
#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_9_SPECIAL_BASE 0x5789E80ull
#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x578A000ull
#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x578A080ull
#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x578A100ull
#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x578A180ull
#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_10_SPECIAL_BASE 0x578AE80ull
#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x578B000ull
#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x578B080ull
#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x578B100ull
#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x578B180ull
#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_11_SPECIAL_BASE 0x578BE80ull
#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x578C000ull
#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x578C080ull
#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x578C100ull
#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x578C180ull
#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_12_SPECIAL_BASE 0x578CE80ull
#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x578D000ull
#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x578D080ull
#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x578D100ull
#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x578D180ull
#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_13_SPECIAL_BASE 0x578DE80ull
#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x578E000ull
#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x578E080ull
#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x578E100ull
#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x578E180ull
#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR0_14_SPECIAL_BASE 0x578EE80ull
#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC7_QM_DCCM0_BASE 0x5790000ull
#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC7_QM_DCCM0_SECTION 0x8000
#define mmNIC7_QM_ARC_AUX0_BASE 0x5798000ull
#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC7_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC7_QM_ARC_AUX0_SPECIAL_BASE 0x5798E80ull
#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC7_QM0_BASE 0x579A000ull
#define NIC7_QM0_MAX_OFFSET 0x1000
#define NIC7_QM0_SECTION 0x9000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x579A900ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x579A908ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x579A910ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x579A918ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x579A920ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x579A928ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x579A930ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x579A938ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x579A940ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x579A948ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x579A950ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x579A958ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x579A960ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x579A968ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x579A970ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x579A978ull
#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC7_QM0_AXUSER_SECURED_BASE 0x579AB00ull
#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC7_QM0_AXUSER_NONSECURED_BASE 0x579AB80ull
#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC7_QM0_DBG_HBW_BASE 0x579AC00ull
#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC7_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC7_QM0_DBG_LBW_BASE 0x579AC80ull
#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC7_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC7_QM0_CGM_BASE 0x579AD80ull
#define NIC7_QM0_CGM_MAX_OFFSET 0xC000
#define NIC7_QM0_CGM_SECTION 0x1000
#define mmNIC7_QM0_SPECIAL_BASE 0x579AE80ull
#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QM0_SPECIAL_SECTION 0x4180
#define mmNIC7_QPC0_BASE 0x579F000ull
#define NIC7_QPC0_MAX_OFFSET 0x1000
#define NIC7_QPC0_SECTION 0x7200
#define mmNIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x579F720ull
#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x579F728ull
#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x579F730ull
#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x579F738ull
#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x579F740ull
#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x579F748ull
#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x579F750ull
#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x579F758ull
#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x579F760ull
#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x579F768ull
#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x579F770ull
#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x579F778ull
#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x579F780ull
#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x579F788ull
#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x579F790ull
#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x579F798ull
#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x579F7A0ull
#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x579F7A8ull
#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x579F7B0ull
#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x579F7B8ull
#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x579F7C0ull
#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x579F7C8ull
#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x579F7D0ull
#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x579F7D8ull
#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x579F7E0ull
#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x579F7E8ull
#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x579F7F0ull
#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x579F7F8ull
#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x579F800ull
#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x579F808ull
#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x579F810ull
#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x579F818ull
#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC7_QPC0_AXUSER_CONG_QUE_BASE 0x579FB80ull
#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_RXWQE_BASE 0x579FBE0ull
#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x579FC40ull
#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_DB_FIFO_BASE 0x579FCA0ull
#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x579FD00ull
#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x579FD60ull
#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_QPC_RESP_BASE 0x579FDC0ull
#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC7_QPC0_AXUSER_QPC_REQ_BASE 0x579FE20ull
#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC7_QPC0_SPECIAL_BASE 0x579FE80ull
#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x57A0000ull
#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x57A0080ull
#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x57A0100ull
#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x57A0180ull
#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_0_SPECIAL_BASE 0x57A0E80ull
#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x57A1000ull
#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x57A1080ull
#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x57A1100ull
#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x57A1180ull
#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_1_SPECIAL_BASE 0x57A1E80ull
#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x57A2000ull
#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x57A2080ull
#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x57A2100ull
#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x57A2180ull
#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_2_SPECIAL_BASE 0x57A2E80ull
#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x57A3000ull
#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x57A3080ull
#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x57A3100ull
#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x57A3180ull
#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_3_SPECIAL_BASE 0x57A3E80ull
#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x57A4000ull
#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x57A4080ull
#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x57A4100ull
#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x57A4180ull
#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_4_SPECIAL_BASE 0x57A4E80ull
#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x57A5000ull
#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x57A5080ull
#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x57A5100ull
#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x57A5180ull
#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_5_SPECIAL_BASE 0x57A5E80ull
#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x57A6000ull
#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x57A6080ull
#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x57A6100ull
#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x57A6180ull
#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_6_SPECIAL_BASE 0x57A6E80ull
#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x57A7000ull
#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x57A7080ull
#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x57A7100ull
#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x57A7180ull
#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_7_SPECIAL_BASE 0x57A7E80ull
#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x57A8000ull
#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x57A8080ull
#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x57A8100ull
#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x57A8180ull
#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_8_SPECIAL_BASE 0x57A8E80ull
#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x57A9000ull
#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x57A9080ull
#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x57A9100ull
#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x57A9180ull
#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_9_SPECIAL_BASE 0x57A9E80ull
#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x57AA000ull
#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x57AA080ull
#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x57AA100ull
#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x57AA180ull
#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_10_SPECIAL_BASE 0x57AAE80ull
#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x57AB000ull
#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x57AB080ull
#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x57AB100ull
#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x57AB180ull
#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_11_SPECIAL_BASE 0x57ABE80ull
#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x57AC000ull
#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x57AC080ull
#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x57AC100ull
#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x57AC180ull
#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_12_SPECIAL_BASE 0x57ACE80ull
#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x57AD000ull
#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x57AD080ull
#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x57AD100ull
#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x57AD180ull
#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_13_SPECIAL_BASE 0x57ADE80ull
#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x57AE000ull
#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x57AE080ull
#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x57AE100ull
#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x57AE180ull
#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC7_UMR1_14_SPECIAL_BASE 0x57AEE80ull
#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC7_QM_DCCM1_BASE 0x57B0000ull
#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC7_QM_DCCM1_SECTION 0x8000
#define mmNIC7_QM_ARC_AUX1_BASE 0x57B8000ull
#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC7_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC7_QM_ARC_AUX1_SPECIAL_BASE 0x57B8E80ull
#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC7_QM1_BASE 0x57BA000ull
#define NIC7_QM1_MAX_OFFSET 0x1000
#define NIC7_QM1_SECTION 0x9000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x57BA900ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x57BA908ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x57BA910ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x57BA918ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x57BA920ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x57BA928ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x57BA930ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x57BA938ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x57BA940ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x57BA948ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x57BA950ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x57BA958ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x57BA960ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x57BA968ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x57BA970ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x57BA978ull
#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC7_QM1_AXUSER_SECURED_BASE 0x57BAB00ull
#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC7_QM1_AXUSER_NONSECURED_BASE 0x57BAB80ull
#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC7_QM1_DBG_HBW_BASE 0x57BAC00ull
#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC7_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC7_QM1_DBG_LBW_BASE 0x57BAC80ull
#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC7_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC7_QM1_CGM_BASE 0x57BAD80ull
#define NIC7_QM1_CGM_MAX_OFFSET 0xC000
#define NIC7_QM1_CGM_SECTION 0x1000
#define mmNIC7_QM1_SPECIAL_BASE 0x57BAE80ull
#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QM1_SPECIAL_SECTION 0x4180
#define mmNIC7_QPC1_BASE 0x57BF000ull
#define NIC7_QPC1_MAX_OFFSET 0x1000
#define NIC7_QPC1_SECTION 0x7200
#define mmNIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x57BF720ull
#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x57BF728ull
#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x57BF730ull
#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x57BF738ull
#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x57BF740ull
#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x57BF748ull
#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x57BF750ull
#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x57BF758ull
#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x57BF760ull
#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x57BF768ull
#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x57BF770ull
#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x57BF778ull
#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x57BF780ull
#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x57BF788ull
#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x57BF790ull
#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x57BF798ull
#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x57BF7A0ull
#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x57BF7A8ull
#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x57BF7B0ull
#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x57BF7B8ull
#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x57BF7C0ull
#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x57BF7C8ull
#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x57BF7D0ull
#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x57BF7D8ull
#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x57BF7E0ull
#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x57BF7E8ull
#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x57BF7F0ull
#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x57BF7F8ull
#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x57BF800ull
#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x57BF808ull
#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x57BF810ull
#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x57BF818ull
#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC7_QPC1_AXUSER_CONG_QUE_BASE 0x57BFB80ull
#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_RXWQE_BASE 0x57BFBE0ull
#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x57BFC40ull
#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_DB_FIFO_BASE 0x57BFCA0ull
#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x57BFD00ull
#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x57BFD60ull
#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_QPC_RESP_BASE 0x57BFDC0ull
#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC7_QPC1_AXUSER_QPC_REQ_BASE 0x57BFE20ull
#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC7_QPC1_SPECIAL_BASE 0x57BFE80ull
#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC7_TMR_BASE 0x57C8000ull
#define NIC7_TMR_MAX_OFFSET 0x1000
#define NIC7_TMR_SECTION 0xD600
#define mmNIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x57C8D60ull
#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC7_TMR_AXUSER_TMR_FIFO_BASE 0x57C8DC0ull
#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC7_TMR_AXUSER_TMR_FSM_BASE 0x57C8E20ull
#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC7_TMR_SPECIAL_BASE 0x57C8E80ull
#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TMR_SPECIAL_SECTION 0x1800
#define mmNIC7_RXB_CORE_BASE 0x57C9000ull
#define NIC7_RXB_CORE_MAX_OFFSET 0x1000
#define NIC7_RXB_CORE_SECTION 0x6100
#define mmNIC7_RXB_CORE_SCT_AWUSER_BASE 0x57C9610ull
#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC7_RXB_CORE_SPECIAL_BASE 0x57C9E80ull
#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC7_RXE0_BASE 0x57CA000ull
#define NIC7_RXE0_MAX_OFFSET 0x1000
#define NIC7_RXE0_SECTION 0x9000
#define mmNIC7_RXE0_WQE_ARUSER_BASE 0x57CA900ull
#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC7_RXE0_SPECIAL_BASE 0x57CAE80ull
#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC7_RXE1_BASE 0x57CB000ull
#define NIC7_RXE1_MAX_OFFSET 0x1000
#define NIC7_RXE1_SECTION 0x9000
#define mmNIC7_RXE1_WQE_ARUSER_BASE 0x57CB900ull
#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC7_RXE1_SPECIAL_BASE 0x57CBE80ull
#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x57CC000ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x57CC050ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x57CC0A0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x57CC0F0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x57CC140ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x57CC190ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x57CC1E0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x57CC230ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x57CC280ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x57CC2D0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x57CC320ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x57CC370ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x57CC3C0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x57CC410ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x57CC460ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x57CC4B0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x57CC500ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x57CC550ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x57CC5A0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x57CC5F0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x57CC640ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x57CC690ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x57CC6E0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x57CC730ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x57CC780ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x57CC7D0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x57CC820ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x57CC870ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x57CC8C0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x57CC910ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x57CC960ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x57CC9B0ull
#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC7_RXE0_AXUSER_SPECIAL_BASE 0x57CCE80ull
#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x57CD000ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x57CD050ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x57CD0A0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x57CD0F0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x57CD140ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x57CD190ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x57CD1E0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x57CD230ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x57CD280ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x57CD2D0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x57CD320ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x57CD370ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x57CD3C0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x57CD410ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x57CD460ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x57CD4B0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x57CD500ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x57CD550ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x57CD5A0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x57CD5F0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x57CD640ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x57CD690ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x57CD6E0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x57CD730ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x57CD780ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x57CD7D0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x57CD820ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x57CD870ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x57CD8C0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x57CD910ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x57CD960ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x57CD9B0ull
#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC7_RXE1_AXUSER_SPECIAL_BASE 0x57CDE80ull
#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC7_TXS0_BASE 0x57D0000ull
#define NIC7_TXS0_MAX_OFFSET 0x1000
#define NIC7_TXS0_SECTION 0xE800
#define mmNIC7_TXS0_SPECIAL_BASE 0x57D0E80ull
#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC7_TXS1_BASE 0x57D1000ull
#define NIC7_TXS1_MAX_OFFSET 0x1000
#define NIC7_TXS1_SECTION 0xE800
#define mmNIC7_TXS1_SPECIAL_BASE 0x57D1E80ull
#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC7_TXE0_BASE 0x57D2000ull
#define NIC7_TXE0_MAX_OFFSET 0x1000
#define NIC7_TXE0_SECTION 0xE800
#define mmNIC7_TXE0_SPECIAL_BASE 0x57D2E80ull
#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC7_TXE1_BASE 0x57D3000ull
#define NIC7_TXE1_MAX_OFFSET 0x1000
#define NIC7_TXE1_SECTION 0xE800
#define mmNIC7_TXE1_SPECIAL_BASE 0x57D3E80ull
#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC7_TXB_BASE 0x57D4000ull
#define NIC7_TXB_MAX_OFFSET 0x1000
#define NIC7_TXB_SECTION 0xE800
#define mmNIC7_TXB_SPECIAL_BASE 0x57D4E80ull
#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_TXB_SPECIAL_SECTION 0x1800
#define mmNIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x57D5000ull
#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x57D5200ull
#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x57D5400ull
#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x57D5600ull
#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC7_MSTR_IF_E2E_CRDT_BASE 0x57D5800ull
#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC7_MSTR_IF_AXUSER_BASE 0x57D5A80ull
#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC7_MSTR_IF_DBG_HBW_BASE 0x57D5B00ull
#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC7_MSTR_IF_DBG_LBW_BASE 0x57D5B80ull
#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC7_MSTR_IF_CORE_HBW_BASE 0x57D5C00ull
#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC7_MSTR_IF_CORE_LBW_BASE 0x57D5D80ull
#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC7_MSTR_IF_SPECIAL_BASE 0x57D5E80ull
#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC7_TX_AXUSER_BASE 0x57D6000ull
#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC7_TX_AXUSER_SECTION 0x2000
#define mmNIC7_SERDES0_BASE 0x57D8000ull
#define NIC7_SERDES0_MAX_OFFSET 0x3E40
#define NIC7_SERDES0_SECTION 0x4000
#define mmNIC7_SERDES1_BASE 0x57DC000ull
#define NIC7_SERDES1_MAX_OFFSET 0x3E40
#define NIC7_SERDES1_SECTION 0x4000
#define mmNIC7_PHY_BASE 0x57E0000ull
#define NIC7_PHY_MAX_OFFSET 0x1000
#define NIC7_PHY_SECTION 0xE800
#define mmNIC7_PHY_SPECIAL_BASE 0x57E0E80ull
#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC7_PHY_SPECIAL_SECTION 0x7180
#define mmPRT7_MAC_AUX_BASE 0x57E8000ull
#define PRT7_MAC_AUX_MAX_OFFSET 0x1000
#define PRT7_MAC_AUX_SECTION 0xE800
#define mmPRT7_MAC_AUX_SPECIAL_BASE 0x57E8E80ull
#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT7_MAC_CORE_BASE 0x57E9000ull
#define PRT7_MAC_CORE_MAX_OFFSET 0x1000
#define PRT7_MAC_CORE_SECTION 0xE800
#define mmPRT7_MAC_CORE_SPECIAL_BASE 0x57E9E80ull
#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC7_MAC_RS_FEC_BASE 0x57EA000ull
#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC7_MAC_RS_FEC_SECTION 0x1000
#define mmNIC7_MAC_GLOB_STAT_CONTROL_REG_BASE 0x57EB000ull
#define NIC7_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC7_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC7_MAC_GLOB_STAT_RX0_BASE 0x57EB100ull
#define NIC7_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC7_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC7_MAC_GLOB_STAT_RX1_BASE 0x57EB18Cull
#define NIC7_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC7_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC7_MAC_GLOB_STAT_RX2_BASE 0x57EB218ull
#define NIC7_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC7_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC7_MAC_GLOB_STAT_RX3_BASE 0x57EB2A4ull
#define NIC7_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC7_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC7_MAC_GLOB_STAT_TX0_BASE 0x57EB330ull
#define NIC7_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC7_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC7_MAC_GLOB_STAT_TX1_BASE 0x57EB398ull
#define NIC7_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC7_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC7_MAC_GLOB_STAT_TX2_BASE 0x57EB400ull
#define NIC7_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC7_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC7_MAC_GLOB_STAT_TX3_BASE 0x57EB468ull
#define NIC7_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC7_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC7_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x57EB800ull
#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC7_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC7_MAC_CH0_MAC_PCS_BASE 0x57EC000ull
#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC7_MAC_CH0_MAC_128_BASE 0x57EC400ull
#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC7_MAC_CH0_MAC_AN_BASE 0x57EC800ull
#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC7_MAC_CH1_MAC_PCS_BASE 0x57ED000ull
#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC7_MAC_CH1_MAC_128_BASE 0x57ED400ull
#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC7_MAC_CH1_MAC_AN_BASE 0x57ED800ull
#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC7_MAC_CH2_MAC_PCS_BASE 0x57EE000ull
#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC7_MAC_CH2_MAC_128_BASE 0x57EE400ull
#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC7_MAC_CH2_MAC_AN_BASE 0x57EE800ull
#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC7_MAC_CH3_MAC_PCS_BASE 0x57EF000ull
#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC7_MAC_CH3_MAC_128_BASE 0x57EF400ull
#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC7_MAC_CH3_MAC_AN_BASE 0x57EF800ull
#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5800000ull
#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5800080ull
#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5800100ull
#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5800180ull
#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_0_SPECIAL_BASE 0x5800E80ull
#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5801000ull
#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5801080ull
#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5801100ull
#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5801180ull
#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_1_SPECIAL_BASE 0x5801E80ull
#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5802000ull
#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5802080ull
#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5802100ull
#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5802180ull
#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_2_SPECIAL_BASE 0x5802E80ull
#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5803000ull
#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5803080ull
#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5803100ull
#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5803180ull
#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_3_SPECIAL_BASE 0x5803E80ull
#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5804000ull
#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5804080ull
#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5804100ull
#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5804180ull
#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_4_SPECIAL_BASE 0x5804E80ull
#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5805000ull
#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5805080ull
#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5805100ull
#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5805180ull
#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_5_SPECIAL_BASE 0x5805E80ull
#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5806000ull
#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5806080ull
#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5806100ull
#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5806180ull
#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_6_SPECIAL_BASE 0x5806E80ull
#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5807000ull
#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5807080ull
#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5807100ull
#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5807180ull
#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_7_SPECIAL_BASE 0x5807E80ull
#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5808000ull
#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5808080ull
#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5808100ull
#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5808180ull
#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_8_SPECIAL_BASE 0x5808E80ull
#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5809000ull
#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5809080ull
#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5809100ull
#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5809180ull
#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_9_SPECIAL_BASE 0x5809E80ull
#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x580A000ull
#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x580A080ull
#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x580A100ull
#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x580A180ull
#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_10_SPECIAL_BASE 0x580AE80ull
#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x580B000ull
#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x580B080ull
#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x580B100ull
#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x580B180ull
#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_11_SPECIAL_BASE 0x580BE80ull
#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x580C000ull
#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x580C080ull
#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x580C100ull
#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x580C180ull
#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_12_SPECIAL_BASE 0x580CE80ull
#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x580D000ull
#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x580D080ull
#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x580D100ull
#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x580D180ull
#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_13_SPECIAL_BASE 0x580DE80ull
#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x580E000ull
#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x580E080ull
#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x580E100ull
#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x580E180ull
#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR0_14_SPECIAL_BASE 0x580EE80ull
#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC8_QM_DCCM0_BASE 0x5810000ull
#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC8_QM_DCCM0_SECTION 0x8000
#define mmNIC8_QM_ARC_AUX0_BASE 0x5818000ull
#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC8_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC8_QM_ARC_AUX0_SPECIAL_BASE 0x5818E80ull
#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC8_QM0_BASE 0x581A000ull
#define NIC8_QM0_MAX_OFFSET 0x1000
#define NIC8_QM0_SECTION 0x9000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x581A900ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x581A908ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x581A910ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x581A918ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x581A920ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x581A928ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x581A930ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x581A938ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x581A940ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x581A948ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x581A950ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x581A958ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x581A960ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x581A968ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x581A970ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x581A978ull
#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC8_QM0_AXUSER_SECURED_BASE 0x581AB00ull
#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC8_QM0_AXUSER_NONSECURED_BASE 0x581AB80ull
#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC8_QM0_DBG_HBW_BASE 0x581AC00ull
#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC8_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC8_QM0_DBG_LBW_BASE 0x581AC80ull
#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC8_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC8_QM0_CGM_BASE 0x581AD80ull
#define NIC8_QM0_CGM_MAX_OFFSET 0xC000
#define NIC8_QM0_CGM_SECTION 0x1000
#define mmNIC8_QM0_SPECIAL_BASE 0x581AE80ull
#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QM0_SPECIAL_SECTION 0x4180
#define mmNIC8_QPC0_BASE 0x581F000ull
#define NIC8_QPC0_MAX_OFFSET 0x1000
#define NIC8_QPC0_SECTION 0x7200
#define mmNIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x581F720ull
#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x581F728ull
#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x581F730ull
#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x581F738ull
#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x581F740ull
#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x581F748ull
#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x581F750ull
#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x581F758ull
#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x581F760ull
#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x581F768ull
#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x581F770ull
#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x581F778ull
#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x581F780ull
#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x581F788ull
#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x581F790ull
#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x581F798ull
#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x581F7A0ull
#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x581F7A8ull
#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x581F7B0ull
#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x581F7B8ull
#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x581F7C0ull
#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x581F7C8ull
#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x581F7D0ull
#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x581F7D8ull
#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x581F7E0ull
#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x581F7E8ull
#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x581F7F0ull
#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x581F7F8ull
#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x581F800ull
#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x581F808ull
#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x581F810ull
#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x581F818ull
#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC8_QPC0_AXUSER_CONG_QUE_BASE 0x581FB80ull
#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_RXWQE_BASE 0x581FBE0ull
#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x581FC40ull
#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_DB_FIFO_BASE 0x581FCA0ull
#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x581FD00ull
#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x581FD60ull
#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_QPC_RESP_BASE 0x581FDC0ull
#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC8_QPC0_AXUSER_QPC_REQ_BASE 0x581FE20ull
#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC8_QPC0_SPECIAL_BASE 0x581FE80ull
#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5820000ull
#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5820080ull
#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5820100ull
#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5820180ull
#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_0_SPECIAL_BASE 0x5820E80ull
#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5821000ull
#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5821080ull
#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5821100ull
#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5821180ull
#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_1_SPECIAL_BASE 0x5821E80ull
#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5822000ull
#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5822080ull
#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5822100ull
#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5822180ull
#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_2_SPECIAL_BASE 0x5822E80ull
#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5823000ull
#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5823080ull
#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5823100ull
#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5823180ull
#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_3_SPECIAL_BASE 0x5823E80ull
#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5824000ull
#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5824080ull
#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5824100ull
#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5824180ull
#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_4_SPECIAL_BASE 0x5824E80ull
#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5825000ull
#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5825080ull
#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5825100ull
#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5825180ull
#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_5_SPECIAL_BASE 0x5825E80ull
#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5826000ull
#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5826080ull
#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5826100ull
#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5826180ull
#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_6_SPECIAL_BASE 0x5826E80ull
#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5827000ull
#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5827080ull
#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5827100ull
#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5827180ull
#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_7_SPECIAL_BASE 0x5827E80ull
#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5828000ull
#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5828080ull
#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5828100ull
#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5828180ull
#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_8_SPECIAL_BASE 0x5828E80ull
#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5829000ull
#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5829080ull
#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5829100ull
#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5829180ull
#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_9_SPECIAL_BASE 0x5829E80ull
#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x582A000ull
#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x582A080ull
#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x582A100ull
#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x582A180ull
#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_10_SPECIAL_BASE 0x582AE80ull
#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x582B000ull
#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x582B080ull
#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x582B100ull
#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x582B180ull
#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_11_SPECIAL_BASE 0x582BE80ull
#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x582C000ull
#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x582C080ull
#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x582C100ull
#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x582C180ull
#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_12_SPECIAL_BASE 0x582CE80ull
#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x582D000ull
#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x582D080ull
#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x582D100ull
#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x582D180ull
#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_13_SPECIAL_BASE 0x582DE80ull
#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x582E000ull
#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x582E080ull
#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x582E100ull
#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x582E180ull
#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC8_UMR1_14_SPECIAL_BASE 0x582EE80ull
#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC8_QM_DCCM1_BASE 0x5830000ull
#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC8_QM_DCCM1_SECTION 0x8000
#define mmNIC8_QM_ARC_AUX1_BASE 0x5838000ull
#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC8_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC8_QM_ARC_AUX1_SPECIAL_BASE 0x5838E80ull
#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC8_QM1_BASE 0x583A000ull
#define NIC8_QM1_MAX_OFFSET 0x1000
#define NIC8_QM1_SECTION 0x9000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x583A900ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x583A908ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x583A910ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x583A918ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x583A920ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x583A928ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x583A930ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x583A938ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x583A940ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x583A948ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x583A950ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x583A958ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x583A960ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x583A968ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x583A970ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x583A978ull
#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC8_QM1_AXUSER_SECURED_BASE 0x583AB00ull
#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC8_QM1_AXUSER_NONSECURED_BASE 0x583AB80ull
#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC8_QM1_DBG_HBW_BASE 0x583AC00ull
#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC8_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC8_QM1_DBG_LBW_BASE 0x583AC80ull
#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC8_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC8_QM1_CGM_BASE 0x583AD80ull
#define NIC8_QM1_CGM_MAX_OFFSET 0xC000
#define NIC8_QM1_CGM_SECTION 0x1000
#define mmNIC8_QM1_SPECIAL_BASE 0x583AE80ull
#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QM1_SPECIAL_SECTION 0x4180
#define mmNIC8_QPC1_BASE 0x583F000ull
#define NIC8_QPC1_MAX_OFFSET 0x1000
#define NIC8_QPC1_SECTION 0x7200
#define mmNIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x583F720ull
#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x583F728ull
#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x583F730ull
#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x583F738ull
#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x583F740ull
#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x583F748ull
#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x583F750ull
#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x583F758ull
#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x583F760ull
#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x583F768ull
#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x583F770ull
#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x583F778ull
#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x583F780ull
#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x583F788ull
#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x583F790ull
#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x583F798ull
#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x583F7A0ull
#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x583F7A8ull
#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x583F7B0ull
#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x583F7B8ull
#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x583F7C0ull
#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x583F7C8ull
#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x583F7D0ull
#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x583F7D8ull
#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x583F7E0ull
#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x583F7E8ull
#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x583F7F0ull
#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x583F7F8ull
#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x583F800ull
#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x583F808ull
#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x583F810ull
#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x583F818ull
#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC8_QPC1_AXUSER_CONG_QUE_BASE 0x583FB80ull
#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_RXWQE_BASE 0x583FBE0ull
#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x583FC40ull
#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_DB_FIFO_BASE 0x583FCA0ull
#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x583FD00ull
#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x583FD60ull
#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_QPC_RESP_BASE 0x583FDC0ull
#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC8_QPC1_AXUSER_QPC_REQ_BASE 0x583FE20ull
#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC8_QPC1_SPECIAL_BASE 0x583FE80ull
#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC8_TMR_BASE 0x5848000ull
#define NIC8_TMR_MAX_OFFSET 0x1000
#define NIC8_TMR_SECTION 0xD600
#define mmNIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5848D60ull
#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC8_TMR_AXUSER_TMR_FIFO_BASE 0x5848DC0ull
#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC8_TMR_AXUSER_TMR_FSM_BASE 0x5848E20ull
#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC8_TMR_SPECIAL_BASE 0x5848E80ull
#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TMR_SPECIAL_SECTION 0x1800
#define mmNIC8_RXB_CORE_BASE 0x5849000ull
#define NIC8_RXB_CORE_MAX_OFFSET 0x1000
#define NIC8_RXB_CORE_SECTION 0x6100
#define mmNIC8_RXB_CORE_SCT_AWUSER_BASE 0x5849610ull
#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC8_RXB_CORE_SPECIAL_BASE 0x5849E80ull
#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC8_RXE0_BASE 0x584A000ull
#define NIC8_RXE0_MAX_OFFSET 0x1000
#define NIC8_RXE0_SECTION 0x9000
#define mmNIC8_RXE0_WQE_ARUSER_BASE 0x584A900ull
#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC8_RXE0_SPECIAL_BASE 0x584AE80ull
#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC8_RXE1_BASE 0x584B000ull
#define NIC8_RXE1_MAX_OFFSET 0x1000
#define NIC8_RXE1_SECTION 0x9000
#define mmNIC8_RXE1_WQE_ARUSER_BASE 0x584B900ull
#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC8_RXE1_SPECIAL_BASE 0x584BE80ull
#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x584C000ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x584C050ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x584C0A0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x584C0F0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x584C140ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x584C190ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x584C1E0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x584C230ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x584C280ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x584C2D0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x584C320ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x584C370ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x584C3C0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x584C410ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x584C460ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x584C4B0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x584C500ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x584C550ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x584C5A0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x584C5F0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x584C640ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x584C690ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x584C6E0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x584C730ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x584C780ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x584C7D0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x584C820ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x584C870ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x584C8C0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x584C910ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x584C960ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x584C9B0ull
#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC8_RXE0_AXUSER_SPECIAL_BASE 0x584CE80ull
#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x584D000ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x584D050ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x584D0A0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x584D0F0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x584D140ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x584D190ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x584D1E0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x584D230ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x584D280ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x584D2D0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x584D320ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x584D370ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x584D3C0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x584D410ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x584D460ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x584D4B0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x584D500ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x584D550ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x584D5A0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x584D5F0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x584D640ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x584D690ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x584D6E0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x584D730ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x584D780ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x584D7D0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x584D820ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x584D870ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x584D8C0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x584D910ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x584D960ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x584D9B0ull
#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC8_RXE1_AXUSER_SPECIAL_BASE 0x584DE80ull
#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC8_TXS0_BASE 0x5850000ull
#define NIC8_TXS0_MAX_OFFSET 0x1000
#define NIC8_TXS0_SECTION 0xE800
#define mmNIC8_TXS0_SPECIAL_BASE 0x5850E80ull
#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC8_TXS1_BASE 0x5851000ull
#define NIC8_TXS1_MAX_OFFSET 0x1000
#define NIC8_TXS1_SECTION 0xE800
#define mmNIC8_TXS1_SPECIAL_BASE 0x5851E80ull
#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC8_TXE0_BASE 0x5852000ull
#define NIC8_TXE0_MAX_OFFSET 0x1000
#define NIC8_TXE0_SECTION 0xE800
#define mmNIC8_TXE0_SPECIAL_BASE 0x5852E80ull
#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC8_TXE1_BASE 0x5853000ull
#define NIC8_TXE1_MAX_OFFSET 0x1000
#define NIC8_TXE1_SECTION 0xE800
#define mmNIC8_TXE1_SPECIAL_BASE 0x5853E80ull
#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC8_TXB_BASE 0x5854000ull
#define NIC8_TXB_MAX_OFFSET 0x1000
#define NIC8_TXB_SECTION 0xE800
#define mmNIC8_TXB_SPECIAL_BASE 0x5854E80ull
#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_TXB_SPECIAL_SECTION 0x1800
#define mmNIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x5855000ull
#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x5855200ull
#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x5855400ull
#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x5855600ull
#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC8_MSTR_IF_E2E_CRDT_BASE 0x5855800ull
#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC8_MSTR_IF_AXUSER_BASE 0x5855A80ull
#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC8_MSTR_IF_DBG_HBW_BASE 0x5855B00ull
#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC8_MSTR_IF_DBG_LBW_BASE 0x5855B80ull
#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC8_MSTR_IF_CORE_HBW_BASE 0x5855C00ull
#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC8_MSTR_IF_CORE_LBW_BASE 0x5855D80ull
#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC8_MSTR_IF_SPECIAL_BASE 0x5855E80ull
#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC8_TX_AXUSER_BASE 0x5856000ull
#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC8_TX_AXUSER_SECTION 0x2000
#define mmNIC8_SERDES0_BASE 0x5858000ull
#define NIC8_SERDES0_MAX_OFFSET 0x3E40
#define NIC8_SERDES0_SECTION 0x4000
#define mmNIC8_SERDES1_BASE 0x585C000ull
#define NIC8_SERDES1_MAX_OFFSET 0x3E40
#define NIC8_SERDES1_SECTION 0x4000
#define mmNIC8_PHY_BASE 0x5860000ull
#define NIC8_PHY_MAX_OFFSET 0x1000
#define NIC8_PHY_SECTION 0xE800
#define mmNIC8_PHY_SPECIAL_BASE 0x5860E80ull
#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC8_PHY_SPECIAL_SECTION 0x7180
#define mmPRT8_MAC_AUX_BASE 0x5868000ull
#define PRT8_MAC_AUX_MAX_OFFSET 0x1000
#define PRT8_MAC_AUX_SECTION 0xE800
#define mmPRT8_MAC_AUX_SPECIAL_BASE 0x5868E80ull
#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT8_MAC_CORE_BASE 0x5869000ull
#define PRT8_MAC_CORE_MAX_OFFSET 0x1000
#define PRT8_MAC_CORE_SECTION 0xE800
#define mmPRT8_MAC_CORE_SPECIAL_BASE 0x5869E80ull
#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC8_MAC_RS_FEC_BASE 0x586A000ull
#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC8_MAC_RS_FEC_SECTION 0x1000
#define mmNIC8_MAC_GLOB_STAT_CONTROL_REG_BASE 0x586B000ull
#define NIC8_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC8_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC8_MAC_GLOB_STAT_RX0_BASE 0x586B100ull
#define NIC8_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC8_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC8_MAC_GLOB_STAT_RX1_BASE 0x586B18Cull
#define NIC8_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC8_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC8_MAC_GLOB_STAT_RX2_BASE 0x586B218ull
#define NIC8_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC8_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC8_MAC_GLOB_STAT_RX3_BASE 0x586B2A4ull
#define NIC8_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC8_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC8_MAC_GLOB_STAT_TX0_BASE 0x586B330ull
#define NIC8_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC8_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC8_MAC_GLOB_STAT_TX1_BASE 0x586B398ull
#define NIC8_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC8_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC8_MAC_GLOB_STAT_TX2_BASE 0x586B400ull
#define NIC8_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC8_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC8_MAC_GLOB_STAT_TX3_BASE 0x586B468ull
#define NIC8_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC8_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC8_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x586B800ull
#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC8_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC8_MAC_CH0_MAC_PCS_BASE 0x586C000ull
#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC8_MAC_CH0_MAC_128_BASE 0x586C400ull
#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC8_MAC_CH0_MAC_AN_BASE 0x586C800ull
#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC8_MAC_CH1_MAC_PCS_BASE 0x586D000ull
#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC8_MAC_CH1_MAC_128_BASE 0x586D400ull
#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC8_MAC_CH1_MAC_AN_BASE 0x586D800ull
#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC8_MAC_CH2_MAC_PCS_BASE 0x586E000ull
#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC8_MAC_CH2_MAC_128_BASE 0x586E400ull
#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC8_MAC_CH2_MAC_AN_BASE 0x586E800ull
#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC8_MAC_CH3_MAC_PCS_BASE 0x586F000ull
#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC8_MAC_CH3_MAC_128_BASE 0x586F400ull
#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC8_MAC_CH3_MAC_AN_BASE 0x586F800ull
#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5880000ull
#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5880080ull
#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5880100ull
#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5880180ull
#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_0_SPECIAL_BASE 0x5880E80ull
#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5881000ull
#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5881080ull
#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5881100ull
#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5881180ull
#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_1_SPECIAL_BASE 0x5881E80ull
#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5882000ull
#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5882080ull
#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5882100ull
#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5882180ull
#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_2_SPECIAL_BASE 0x5882E80ull
#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5883000ull
#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5883080ull
#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5883100ull
#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5883180ull
#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_3_SPECIAL_BASE 0x5883E80ull
#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5884000ull
#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5884080ull
#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5884100ull
#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5884180ull
#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_4_SPECIAL_BASE 0x5884E80ull
#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5885000ull
#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5885080ull
#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5885100ull
#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5885180ull
#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_5_SPECIAL_BASE 0x5885E80ull
#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5886000ull
#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5886080ull
#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5886100ull
#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5886180ull
#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_6_SPECIAL_BASE 0x5886E80ull
#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5887000ull
#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5887080ull
#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5887100ull
#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5887180ull
#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_7_SPECIAL_BASE 0x5887E80ull
#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5888000ull
#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5888080ull
#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5888100ull
#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5888180ull
#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_8_SPECIAL_BASE 0x5888E80ull
#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5889000ull
#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5889080ull
#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5889100ull
#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5889180ull
#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_9_SPECIAL_BASE 0x5889E80ull
#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x588A000ull
#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x588A080ull
#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x588A100ull
#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x588A180ull
#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_10_SPECIAL_BASE 0x588AE80ull
#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x588B000ull
#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x588B080ull
#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x588B100ull
#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x588B180ull
#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_11_SPECIAL_BASE 0x588BE80ull
#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x588C000ull
#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x588C080ull
#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x588C100ull
#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x588C180ull
#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_12_SPECIAL_BASE 0x588CE80ull
#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x588D000ull
#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x588D080ull
#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x588D100ull
#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x588D180ull
#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_13_SPECIAL_BASE 0x588DE80ull
#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x588E000ull
#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x588E080ull
#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x588E100ull
#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x588E180ull
#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR0_14_SPECIAL_BASE 0x588EE80ull
#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC9_QM_DCCM0_BASE 0x5890000ull
#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC9_QM_DCCM0_SECTION 0x8000
#define mmNIC9_QM_ARC_AUX0_BASE 0x5898000ull
#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC9_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC9_QM_ARC_AUX0_SPECIAL_BASE 0x5898E80ull
#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC9_QM0_BASE 0x589A000ull
#define NIC9_QM0_MAX_OFFSET 0x1000
#define NIC9_QM0_SECTION 0x9000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x589A900ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x589A908ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x589A910ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x589A918ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x589A920ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x589A928ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x589A930ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x589A938ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x589A940ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x589A948ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x589A950ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x589A958ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x589A960ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x589A968ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x589A970ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x589A978ull
#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC9_QM0_AXUSER_SECURED_BASE 0x589AB00ull
#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC9_QM0_AXUSER_NONSECURED_BASE 0x589AB80ull
#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC9_QM0_DBG_HBW_BASE 0x589AC00ull
#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC9_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC9_QM0_DBG_LBW_BASE 0x589AC80ull
#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC9_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC9_QM0_CGM_BASE 0x589AD80ull
#define NIC9_QM0_CGM_MAX_OFFSET 0xC000
#define NIC9_QM0_CGM_SECTION 0x1000
#define mmNIC9_QM0_SPECIAL_BASE 0x589AE80ull
#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QM0_SPECIAL_SECTION 0x4180
#define mmNIC9_QPC0_BASE 0x589F000ull
#define NIC9_QPC0_MAX_OFFSET 0x1000
#define NIC9_QPC0_SECTION 0x7200
#define mmNIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x589F720ull
#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x589F728ull
#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x589F730ull
#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x589F738ull
#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x589F740ull
#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x589F748ull
#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x589F750ull
#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x589F758ull
#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x589F760ull
#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x589F768ull
#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x589F770ull
#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x589F778ull
#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x589F780ull
#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x589F788ull
#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x589F790ull
#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x589F798ull
#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x589F7A0ull
#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x589F7A8ull
#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x589F7B0ull
#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x589F7B8ull
#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x589F7C0ull
#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x589F7C8ull
#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x589F7D0ull
#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x589F7D8ull
#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x589F7E0ull
#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x589F7E8ull
#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x589F7F0ull
#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x589F7F8ull
#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x589F800ull
#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x589F808ull
#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x589F810ull
#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x589F818ull
#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC9_QPC0_AXUSER_CONG_QUE_BASE 0x589FB80ull
#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_RXWQE_BASE 0x589FBE0ull
#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x589FC40ull
#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_DB_FIFO_BASE 0x589FCA0ull
#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x589FD00ull
#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x589FD60ull
#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_QPC_RESP_BASE 0x589FDC0ull
#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC9_QPC0_AXUSER_QPC_REQ_BASE 0x589FE20ull
#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC9_QPC0_SPECIAL_BASE 0x589FE80ull
#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x58A0000ull
#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x58A0080ull
#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x58A0100ull
#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x58A0180ull
#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_0_SPECIAL_BASE 0x58A0E80ull
#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x58A1000ull
#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x58A1080ull
#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x58A1100ull
#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x58A1180ull
#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_1_SPECIAL_BASE 0x58A1E80ull
#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x58A2000ull
#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x58A2080ull
#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x58A2100ull
#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x58A2180ull
#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_2_SPECIAL_BASE 0x58A2E80ull
#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x58A3000ull
#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x58A3080ull
#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x58A3100ull
#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x58A3180ull
#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_3_SPECIAL_BASE 0x58A3E80ull
#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x58A4000ull
#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x58A4080ull
#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x58A4100ull
#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x58A4180ull
#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_4_SPECIAL_BASE 0x58A4E80ull
#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x58A5000ull
#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x58A5080ull
#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x58A5100ull
#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x58A5180ull
#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_5_SPECIAL_BASE 0x58A5E80ull
#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x58A6000ull
#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x58A6080ull
#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x58A6100ull
#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x58A6180ull
#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_6_SPECIAL_BASE 0x58A6E80ull
#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x58A7000ull
#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x58A7080ull
#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x58A7100ull
#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x58A7180ull
#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_7_SPECIAL_BASE 0x58A7E80ull
#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x58A8000ull
#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x58A8080ull
#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x58A8100ull
#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x58A8180ull
#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_8_SPECIAL_BASE 0x58A8E80ull
#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x58A9000ull
#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x58A9080ull
#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x58A9100ull
#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x58A9180ull
#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_9_SPECIAL_BASE 0x58A9E80ull
#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x58AA000ull
#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x58AA080ull
#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x58AA100ull
#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x58AA180ull
#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_10_SPECIAL_BASE 0x58AAE80ull
#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x58AB000ull
#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x58AB080ull
#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x58AB100ull
#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x58AB180ull
#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_11_SPECIAL_BASE 0x58ABE80ull
#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x58AC000ull
#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x58AC080ull
#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x58AC100ull
#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x58AC180ull
#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_12_SPECIAL_BASE 0x58ACE80ull
#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x58AD000ull
#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x58AD080ull
#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x58AD100ull
#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x58AD180ull
#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_13_SPECIAL_BASE 0x58ADE80ull
#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x58AE000ull
#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x58AE080ull
#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x58AE100ull
#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x58AE180ull
#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC9_UMR1_14_SPECIAL_BASE 0x58AEE80ull
#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC9_QM_DCCM1_BASE 0x58B0000ull
#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC9_QM_DCCM1_SECTION 0x8000
#define mmNIC9_QM_ARC_AUX1_BASE 0x58B8000ull
#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC9_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC9_QM_ARC_AUX1_SPECIAL_BASE 0x58B8E80ull
#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC9_QM1_BASE 0x58BA000ull
#define NIC9_QM1_MAX_OFFSET 0x1000
#define NIC9_QM1_SECTION 0x9000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x58BA900ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x58BA908ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x58BA910ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x58BA918ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x58BA920ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x58BA928ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x58BA930ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x58BA938ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x58BA940ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x58BA948ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x58BA950ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x58BA958ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x58BA960ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x58BA968ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x58BA970ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x58BA978ull
#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC9_QM1_AXUSER_SECURED_BASE 0x58BAB00ull
#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC9_QM1_AXUSER_NONSECURED_BASE 0x58BAB80ull
#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC9_QM1_DBG_HBW_BASE 0x58BAC00ull
#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC9_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC9_QM1_DBG_LBW_BASE 0x58BAC80ull
#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC9_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC9_QM1_CGM_BASE 0x58BAD80ull
#define NIC9_QM1_CGM_MAX_OFFSET 0xC000
#define NIC9_QM1_CGM_SECTION 0x1000
#define mmNIC9_QM1_SPECIAL_BASE 0x58BAE80ull
#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QM1_SPECIAL_SECTION 0x4180
#define mmNIC9_QPC1_BASE 0x58BF000ull
#define NIC9_QPC1_MAX_OFFSET 0x1000
#define NIC9_QPC1_SECTION 0x7200
#define mmNIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x58BF720ull
#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x58BF728ull
#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x58BF730ull
#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x58BF738ull
#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x58BF740ull
#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x58BF748ull
#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x58BF750ull
#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x58BF758ull
#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x58BF760ull
#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x58BF768ull
#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x58BF770ull
#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x58BF778ull
#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x58BF780ull
#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x58BF788ull
#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x58BF790ull
#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x58BF798ull
#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x58BF7A0ull
#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x58BF7A8ull
#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x58BF7B0ull
#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x58BF7B8ull
#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x58BF7C0ull
#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x58BF7C8ull
#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x58BF7D0ull
#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x58BF7D8ull
#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x58BF7E0ull
#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x58BF7E8ull
#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x58BF7F0ull
#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x58BF7F8ull
#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x58BF800ull
#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x58BF808ull
#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x58BF810ull
#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x58BF818ull
#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC9_QPC1_AXUSER_CONG_QUE_BASE 0x58BFB80ull
#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_RXWQE_BASE 0x58BFBE0ull
#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x58BFC40ull
#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_DB_FIFO_BASE 0x58BFCA0ull
#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x58BFD00ull
#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x58BFD60ull
#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_QPC_RESP_BASE 0x58BFDC0ull
#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC9_QPC1_AXUSER_QPC_REQ_BASE 0x58BFE20ull
#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC9_QPC1_SPECIAL_BASE 0x58BFE80ull
#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC9_TMR_BASE 0x58C8000ull
#define NIC9_TMR_MAX_OFFSET 0x1000
#define NIC9_TMR_SECTION 0xD600
#define mmNIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x58C8D60ull
#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC9_TMR_AXUSER_TMR_FIFO_BASE 0x58C8DC0ull
#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC9_TMR_AXUSER_TMR_FSM_BASE 0x58C8E20ull
#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC9_TMR_SPECIAL_BASE 0x58C8E80ull
#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TMR_SPECIAL_SECTION 0x1800
#define mmNIC9_RXB_CORE_BASE 0x58C9000ull
#define NIC9_RXB_CORE_MAX_OFFSET 0x1000
#define NIC9_RXB_CORE_SECTION 0x6100
#define mmNIC9_RXB_CORE_SCT_AWUSER_BASE 0x58C9610ull
#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC9_RXB_CORE_SPECIAL_BASE 0x58C9E80ull
#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC9_RXE0_BASE 0x58CA000ull
#define NIC9_RXE0_MAX_OFFSET 0x1000
#define NIC9_RXE0_SECTION 0x9000
#define mmNIC9_RXE0_WQE_ARUSER_BASE 0x58CA900ull
#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC9_RXE0_SPECIAL_BASE 0x58CAE80ull
#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC9_RXE1_BASE 0x58CB000ull
#define NIC9_RXE1_MAX_OFFSET 0x1000
#define NIC9_RXE1_SECTION 0x9000
#define mmNIC9_RXE1_WQE_ARUSER_BASE 0x58CB900ull
#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC9_RXE1_SPECIAL_BASE 0x58CBE80ull
#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x58CC000ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x58CC050ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x58CC0A0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x58CC0F0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x58CC140ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x58CC190ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x58CC1E0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x58CC230ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x58CC280ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x58CC2D0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x58CC320ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x58CC370ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x58CC3C0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x58CC410ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x58CC460ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x58CC4B0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x58CC500ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x58CC550ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x58CC5A0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x58CC5F0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x58CC640ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x58CC690ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x58CC6E0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x58CC730ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x58CC780ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x58CC7D0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x58CC820ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x58CC870ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x58CC8C0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x58CC910ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x58CC960ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x58CC9B0ull
#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC9_RXE0_AXUSER_SPECIAL_BASE 0x58CCE80ull
#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x58CD000ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x58CD050ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x58CD0A0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x58CD0F0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x58CD140ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x58CD190ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x58CD1E0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x58CD230ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x58CD280ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x58CD2D0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x58CD320ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x58CD370ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x58CD3C0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x58CD410ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x58CD460ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x58CD4B0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x58CD500ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x58CD550ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x58CD5A0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x58CD5F0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x58CD640ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x58CD690ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x58CD6E0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x58CD730ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x58CD780ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x58CD7D0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x58CD820ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x58CD870ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x58CD8C0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x58CD910ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x58CD960ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x58CD9B0ull
#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC9_RXE1_AXUSER_SPECIAL_BASE 0x58CDE80ull
#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC9_TXS0_BASE 0x58D0000ull
#define NIC9_TXS0_MAX_OFFSET 0x1000
#define NIC9_TXS0_SECTION 0xE800
#define mmNIC9_TXS0_SPECIAL_BASE 0x58D0E80ull
#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC9_TXS1_BASE 0x58D1000ull
#define NIC9_TXS1_MAX_OFFSET 0x1000
#define NIC9_TXS1_SECTION 0xE800
#define mmNIC9_TXS1_SPECIAL_BASE 0x58D1E80ull
#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC9_TXE0_BASE 0x58D2000ull
#define NIC9_TXE0_MAX_OFFSET 0x1000
#define NIC9_TXE0_SECTION 0xE800
#define mmNIC9_TXE0_SPECIAL_BASE 0x58D2E80ull
#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC9_TXE1_BASE 0x58D3000ull
#define NIC9_TXE1_MAX_OFFSET 0x1000
#define NIC9_TXE1_SECTION 0xE800
#define mmNIC9_TXE1_SPECIAL_BASE 0x58D3E80ull
#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC9_TXB_BASE 0x58D4000ull
#define NIC9_TXB_MAX_OFFSET 0x1000
#define NIC9_TXB_SECTION 0xE800
#define mmNIC9_TXB_SPECIAL_BASE 0x58D4E80ull
#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_TXB_SPECIAL_SECTION 0x1800
#define mmNIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x58D5000ull
#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x58D5200ull
#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x58D5400ull
#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x58D5600ull
#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC9_MSTR_IF_E2E_CRDT_BASE 0x58D5800ull
#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC9_MSTR_IF_AXUSER_BASE 0x58D5A80ull
#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC9_MSTR_IF_DBG_HBW_BASE 0x58D5B00ull
#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC9_MSTR_IF_DBG_LBW_BASE 0x58D5B80ull
#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC9_MSTR_IF_CORE_HBW_BASE 0x58D5C00ull
#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC9_MSTR_IF_CORE_LBW_BASE 0x58D5D80ull
#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC9_MSTR_IF_SPECIAL_BASE 0x58D5E80ull
#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC9_TX_AXUSER_BASE 0x58D6000ull
#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC9_TX_AXUSER_SECTION 0x2000
#define mmNIC9_SERDES0_BASE 0x58D8000ull
#define NIC9_SERDES0_MAX_OFFSET 0x3E40
#define NIC9_SERDES0_SECTION 0x4000
#define mmNIC9_SERDES1_BASE 0x58DC000ull
#define NIC9_SERDES1_MAX_OFFSET 0x3E40
#define NIC9_SERDES1_SECTION 0x4000
#define mmNIC9_PHY_BASE 0x58E0000ull
#define NIC9_PHY_MAX_OFFSET 0x1000
#define NIC9_PHY_SECTION 0xE800
#define mmNIC9_PHY_SPECIAL_BASE 0x58E0E80ull
#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC9_PHY_SPECIAL_SECTION 0x7180
#define mmPRT9_MAC_AUX_BASE 0x58E8000ull
#define PRT9_MAC_AUX_MAX_OFFSET 0x1000
#define PRT9_MAC_AUX_SECTION 0xE800
#define mmPRT9_MAC_AUX_SPECIAL_BASE 0x58E8E80ull
#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT9_MAC_CORE_BASE 0x58E9000ull
#define PRT9_MAC_CORE_MAX_OFFSET 0x1000
#define PRT9_MAC_CORE_SECTION 0xE800
#define mmPRT9_MAC_CORE_SPECIAL_BASE 0x58E9E80ull
#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC9_MAC_RS_FEC_BASE 0x58EA000ull
#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC9_MAC_RS_FEC_SECTION 0x1000
#define mmNIC9_MAC_GLOB_STAT_CONTROL_REG_BASE 0x58EB000ull
#define NIC9_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC9_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC9_MAC_GLOB_STAT_RX0_BASE 0x58EB100ull
#define NIC9_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC9_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC9_MAC_GLOB_STAT_RX1_BASE 0x58EB18Cull
#define NIC9_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC9_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC9_MAC_GLOB_STAT_RX2_BASE 0x58EB218ull
#define NIC9_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC9_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC9_MAC_GLOB_STAT_RX3_BASE 0x58EB2A4ull
#define NIC9_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC9_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC9_MAC_GLOB_STAT_TX0_BASE 0x58EB330ull
#define NIC9_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC9_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC9_MAC_GLOB_STAT_TX1_BASE 0x58EB398ull
#define NIC9_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC9_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC9_MAC_GLOB_STAT_TX2_BASE 0x58EB400ull
#define NIC9_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC9_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC9_MAC_GLOB_STAT_TX3_BASE 0x58EB468ull
#define NIC9_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC9_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC9_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x58EB800ull
#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC9_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC9_MAC_CH0_MAC_PCS_BASE 0x58EC000ull
#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC9_MAC_CH0_MAC_128_BASE 0x58EC400ull
#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC9_MAC_CH0_MAC_AN_BASE 0x58EC800ull
#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC9_MAC_CH1_MAC_PCS_BASE 0x58ED000ull
#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC9_MAC_CH1_MAC_128_BASE 0x58ED400ull
#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC9_MAC_CH1_MAC_AN_BASE 0x58ED800ull
#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC9_MAC_CH2_MAC_PCS_BASE 0x58EE000ull
#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC9_MAC_CH2_MAC_128_BASE 0x58EE400ull
#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC9_MAC_CH2_MAC_AN_BASE 0x58EE800ull
#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC9_MAC_CH3_MAC_PCS_BASE 0x58EF000ull
#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC9_MAC_CH3_MAC_128_BASE 0x58EF400ull
#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC9_MAC_CH3_MAC_AN_BASE 0x58EF800ull
#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5900000ull
#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5900080ull
#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5900100ull
#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5900180ull
#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_0_SPECIAL_BASE 0x5900E80ull
#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5901000ull
#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5901080ull
#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5901100ull
#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5901180ull
#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_1_SPECIAL_BASE 0x5901E80ull
#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5902000ull
#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5902080ull
#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5902100ull
#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5902180ull
#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_2_SPECIAL_BASE 0x5902E80ull
#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5903000ull
#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5903080ull
#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5903100ull
#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5903180ull
#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_3_SPECIAL_BASE 0x5903E80ull
#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5904000ull
#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5904080ull
#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5904100ull
#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5904180ull
#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_4_SPECIAL_BASE 0x5904E80ull
#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5905000ull
#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5905080ull
#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5905100ull
#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5905180ull
#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_5_SPECIAL_BASE 0x5905E80ull
#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5906000ull
#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5906080ull
#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5906100ull
#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5906180ull
#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_6_SPECIAL_BASE 0x5906E80ull
#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5907000ull
#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5907080ull
#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5907100ull
#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5907180ull
#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_7_SPECIAL_BASE 0x5907E80ull
#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5908000ull
#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5908080ull
#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5908100ull
#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5908180ull
#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_8_SPECIAL_BASE 0x5908E80ull
#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5909000ull
#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5909080ull
#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5909100ull
#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5909180ull
#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_9_SPECIAL_BASE 0x5909E80ull
#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x590A000ull
#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x590A080ull
#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x590A100ull
#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x590A180ull
#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_10_SPECIAL_BASE 0x590AE80ull
#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x590B000ull
#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x590B080ull
#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x590B100ull
#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x590B180ull
#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_11_SPECIAL_BASE 0x590BE80ull
#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x590C000ull
#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x590C080ull
#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x590C100ull
#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x590C180ull
#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_12_SPECIAL_BASE 0x590CE80ull
#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x590D000ull
#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x590D080ull
#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x590D100ull
#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x590D180ull
#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_13_SPECIAL_BASE 0x590DE80ull
#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x590E000ull
#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x590E080ull
#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x590E100ull
#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x590E180ull
#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR0_14_SPECIAL_BASE 0x590EE80ull
#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC10_QM_DCCM0_BASE 0x5910000ull
#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC10_QM_DCCM0_SECTION 0x8000
#define mmNIC10_QM_ARC_AUX0_BASE 0x5918000ull
#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC10_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC10_QM_ARC_AUX0_SPECIAL_BASE 0x5918E80ull
#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC10_QM0_BASE 0x591A000ull
#define NIC10_QM0_MAX_OFFSET 0x1000
#define NIC10_QM0_SECTION 0x9000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x591A900ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x591A908ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x591A910ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x591A918ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x591A920ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x591A928ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x591A930ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x591A938ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x591A940ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x591A948ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x591A950ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x591A958ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x591A960ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x591A968ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x591A970ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x591A978ull
#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC10_QM0_AXUSER_SECURED_BASE 0x591AB00ull
#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC10_QM0_AXUSER_NONSECURED_BASE 0x591AB80ull
#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC10_QM0_DBG_HBW_BASE 0x591AC00ull
#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC10_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC10_QM0_DBG_LBW_BASE 0x591AC80ull
#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC10_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC10_QM0_CGM_BASE 0x591AD80ull
#define NIC10_QM0_CGM_MAX_OFFSET 0xC000
#define NIC10_QM0_CGM_SECTION 0x1000
#define mmNIC10_QM0_SPECIAL_BASE 0x591AE80ull
#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QM0_SPECIAL_SECTION 0x4180
#define mmNIC10_QPC0_BASE 0x591F000ull
#define NIC10_QPC0_MAX_OFFSET 0x1000
#define NIC10_QPC0_SECTION 0x7200
#define mmNIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x591F720ull
#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x591F728ull
#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x591F730ull
#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x591F738ull
#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x591F740ull
#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x591F748ull
#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x591F750ull
#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x591F758ull
#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x591F760ull
#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x591F768ull
#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x591F770ull
#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x591F778ull
#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x591F780ull
#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x591F788ull
#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x591F790ull
#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x591F798ull
#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x591F7A0ull
#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x591F7A8ull
#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x591F7B0ull
#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x591F7B8ull
#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x591F7C0ull
#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x591F7C8ull
#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x591F7D0ull
#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x591F7D8ull
#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x591F7E0ull
#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x591F7E8ull
#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x591F7F0ull
#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x591F7F8ull
#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x591F800ull
#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x591F808ull
#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x591F810ull
#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x591F818ull
#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC10_QPC0_AXUSER_CONG_QUE_BASE 0x591FB80ull
#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_RXWQE_BASE 0x591FBE0ull
#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x591FC40ull
#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_DB_FIFO_BASE 0x591FCA0ull
#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x591FD00ull
#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x591FD60ull
#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_QPC_RESP_BASE 0x591FDC0ull
#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC10_QPC0_AXUSER_QPC_REQ_BASE 0x591FE20ull
#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC10_QPC0_SPECIAL_BASE 0x591FE80ull
#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x5920000ull
#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x5920080ull
#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x5920100ull
#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x5920180ull
#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_0_SPECIAL_BASE 0x5920E80ull
#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x5921000ull
#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x5921080ull
#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x5921100ull
#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x5921180ull
#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_1_SPECIAL_BASE 0x5921E80ull
#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x5922000ull
#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x5922080ull
#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x5922100ull
#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x5922180ull
#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_2_SPECIAL_BASE 0x5922E80ull
#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x5923000ull
#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x5923080ull
#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x5923100ull
#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x5923180ull
#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_3_SPECIAL_BASE 0x5923E80ull
#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x5924000ull
#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x5924080ull
#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x5924100ull
#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x5924180ull
#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_4_SPECIAL_BASE 0x5924E80ull
#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x5925000ull
#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x5925080ull
#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x5925100ull
#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x5925180ull
#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_5_SPECIAL_BASE 0x5925E80ull
#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x5926000ull
#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x5926080ull
#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x5926100ull
#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x5926180ull
#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_6_SPECIAL_BASE 0x5926E80ull
#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x5927000ull
#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x5927080ull
#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x5927100ull
#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x5927180ull
#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_7_SPECIAL_BASE 0x5927E80ull
#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x5928000ull
#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x5928080ull
#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x5928100ull
#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x5928180ull
#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_8_SPECIAL_BASE 0x5928E80ull
#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x5929000ull
#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x5929080ull
#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x5929100ull
#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x5929180ull
#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_9_SPECIAL_BASE 0x5929E80ull
#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x592A000ull
#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x592A080ull
#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x592A100ull
#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x592A180ull
#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_10_SPECIAL_BASE 0x592AE80ull
#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x592B000ull
#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x592B080ull
#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x592B100ull
#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x592B180ull
#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_11_SPECIAL_BASE 0x592BE80ull
#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x592C000ull
#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x592C080ull
#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x592C100ull
#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x592C180ull
#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_12_SPECIAL_BASE 0x592CE80ull
#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x592D000ull
#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x592D080ull
#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x592D100ull
#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x592D180ull
#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_13_SPECIAL_BASE 0x592DE80ull
#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x592E000ull
#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x592E080ull
#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x592E100ull
#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x592E180ull
#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC10_UMR1_14_SPECIAL_BASE 0x592EE80ull
#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC10_QM_DCCM1_BASE 0x5930000ull
#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC10_QM_DCCM1_SECTION 0x8000
#define mmNIC10_QM_ARC_AUX1_BASE 0x5938000ull
#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC10_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC10_QM_ARC_AUX1_SPECIAL_BASE 0x5938E80ull
#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC10_QM1_BASE 0x593A000ull
#define NIC10_QM1_MAX_OFFSET 0x1000
#define NIC10_QM1_SECTION 0x9000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x593A900ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x593A908ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x593A910ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x593A918ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x593A920ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x593A928ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x593A930ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x593A938ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x593A940ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x593A948ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x593A950ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x593A958ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x593A960ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x593A968ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x593A970ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x593A978ull
#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC10_QM1_AXUSER_SECURED_BASE 0x593AB00ull
#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC10_QM1_AXUSER_NONSECURED_BASE 0x593AB80ull
#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC10_QM1_DBG_HBW_BASE 0x593AC00ull
#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC10_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC10_QM1_DBG_LBW_BASE 0x593AC80ull
#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC10_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC10_QM1_CGM_BASE 0x593AD80ull
#define NIC10_QM1_CGM_MAX_OFFSET 0xC000
#define NIC10_QM1_CGM_SECTION 0x1000
#define mmNIC10_QM1_SPECIAL_BASE 0x593AE80ull
#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QM1_SPECIAL_SECTION 0x4180
#define mmNIC10_QPC1_BASE 0x593F000ull
#define NIC10_QPC1_MAX_OFFSET 0x1000
#define NIC10_QPC1_SECTION 0x7200
#define mmNIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x593F720ull
#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x593F728ull
#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x593F730ull
#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x593F738ull
#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x593F740ull
#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x593F748ull
#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x593F750ull
#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x593F758ull
#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x593F760ull
#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x593F768ull
#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x593F770ull
#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x593F778ull
#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x593F780ull
#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x593F788ull
#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x593F790ull
#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x593F798ull
#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x593F7A0ull
#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x593F7A8ull
#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x593F7B0ull
#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x593F7B8ull
#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x593F7C0ull
#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x593F7C8ull
#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x593F7D0ull
#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x593F7D8ull
#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x593F7E0ull
#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x593F7E8ull
#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x593F7F0ull
#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x593F7F8ull
#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x593F800ull
#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x593F808ull
#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x593F810ull
#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x593F818ull
#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC10_QPC1_AXUSER_CONG_QUE_BASE 0x593FB80ull
#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_RXWQE_BASE 0x593FBE0ull
#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x593FC40ull
#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_DB_FIFO_BASE 0x593FCA0ull
#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x593FD00ull
#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x593FD60ull
#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_QPC_RESP_BASE 0x593FDC0ull
#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC10_QPC1_AXUSER_QPC_REQ_BASE 0x593FE20ull
#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC10_QPC1_SPECIAL_BASE 0x593FE80ull
#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC10_TMR_BASE 0x5948000ull
#define NIC10_TMR_MAX_OFFSET 0x1000
#define NIC10_TMR_SECTION 0xD600
#define mmNIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x5948D60ull
#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC10_TMR_AXUSER_TMR_FIFO_BASE 0x5948DC0ull
#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC10_TMR_AXUSER_TMR_FSM_BASE 0x5948E20ull
#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC10_TMR_SPECIAL_BASE 0x5948E80ull
#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TMR_SPECIAL_SECTION 0x1800
#define mmNIC10_RXB_CORE_BASE 0x5949000ull
#define NIC10_RXB_CORE_MAX_OFFSET 0x1000
#define NIC10_RXB_CORE_SECTION 0x6100
#define mmNIC10_RXB_CORE_SCT_AWUSER_BASE 0x5949610ull
#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC10_RXB_CORE_SPECIAL_BASE 0x5949E80ull
#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC10_RXE0_BASE 0x594A000ull
#define NIC10_RXE0_MAX_OFFSET 0x1000
#define NIC10_RXE0_SECTION 0x9000
#define mmNIC10_RXE0_WQE_ARUSER_BASE 0x594A900ull
#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC10_RXE0_SPECIAL_BASE 0x594AE80ull
#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC10_RXE1_BASE 0x594B000ull
#define NIC10_RXE1_MAX_OFFSET 0x1000
#define NIC10_RXE1_SECTION 0x9000
#define mmNIC10_RXE1_WQE_ARUSER_BASE 0x594B900ull
#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC10_RXE1_SPECIAL_BASE 0x594BE80ull
#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x594C000ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x594C050ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x594C0A0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x594C0F0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x594C140ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x594C190ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x594C1E0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x594C230ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x594C280ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x594C2D0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x594C320ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x594C370ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x594C3C0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x594C410ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x594C460ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x594C4B0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x594C500ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x594C550ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x594C5A0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x594C5F0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x594C640ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x594C690ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x594C6E0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x594C730ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x594C780ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x594C7D0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x594C820ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x594C870ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x594C8C0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x594C910ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x594C960ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x594C9B0ull
#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC10_RXE0_AXUSER_SPECIAL_BASE 0x594CE80ull
#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x594D000ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x594D050ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x594D0A0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x594D0F0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x594D140ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x594D190ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x594D1E0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x594D230ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x594D280ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x594D2D0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x594D320ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x594D370ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x594D3C0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x594D410ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x594D460ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x594D4B0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x594D500ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x594D550ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x594D5A0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x594D5F0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x594D640ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x594D690ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x594D6E0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x594D730ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x594D780ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x594D7D0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x594D820ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x594D870ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x594D8C0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x594D910ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x594D960ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x594D9B0ull
#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC10_RXE1_AXUSER_SPECIAL_BASE 0x594DE80ull
#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC10_TXS0_BASE 0x5950000ull
#define NIC10_TXS0_MAX_OFFSET 0x1000
#define NIC10_TXS0_SECTION 0xE800
#define mmNIC10_TXS0_SPECIAL_BASE 0x5950E80ull
#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC10_TXS1_BASE 0x5951000ull
#define NIC10_TXS1_MAX_OFFSET 0x1000
#define NIC10_TXS1_SECTION 0xE800
#define mmNIC10_TXS1_SPECIAL_BASE 0x5951E80ull
#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC10_TXE0_BASE 0x5952000ull
#define NIC10_TXE0_MAX_OFFSET 0x1000
#define NIC10_TXE0_SECTION 0xE800
#define mmNIC10_TXE0_SPECIAL_BASE 0x5952E80ull
#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC10_TXE1_BASE 0x5953000ull
#define NIC10_TXE1_MAX_OFFSET 0x1000
#define NIC10_TXE1_SECTION 0xE800
#define mmNIC10_TXE1_SPECIAL_BASE 0x5953E80ull
#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC10_TXB_BASE 0x5954000ull
#define NIC10_TXB_MAX_OFFSET 0x1000
#define NIC10_TXB_SECTION 0xE800
#define mmNIC10_TXB_SPECIAL_BASE 0x5954E80ull
#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_TXB_SPECIAL_SECTION 0x1800
#define mmNIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x5955000ull
#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x5955200ull
#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x5955400ull
#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x5955600ull
#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC10_MSTR_IF_E2E_CRDT_BASE 0x5955800ull
#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC10_MSTR_IF_AXUSER_BASE 0x5955A80ull
#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC10_MSTR_IF_DBG_HBW_BASE 0x5955B00ull
#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC10_MSTR_IF_DBG_LBW_BASE 0x5955B80ull
#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC10_MSTR_IF_CORE_HBW_BASE 0x5955C00ull
#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC10_MSTR_IF_CORE_LBW_BASE 0x5955D80ull
#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC10_MSTR_IF_SPECIAL_BASE 0x5955E80ull
#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC10_TX_AXUSER_BASE 0x5956000ull
#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC10_TX_AXUSER_SECTION 0x2000
#define mmNIC10_SERDES0_BASE 0x5958000ull
#define NIC10_SERDES0_MAX_OFFSET 0x3E40
#define NIC10_SERDES0_SECTION 0x4000
#define mmNIC10_SERDES1_BASE 0x595C000ull
#define NIC10_SERDES1_MAX_OFFSET 0x3E40
#define NIC10_SERDES1_SECTION 0x4000
#define mmNIC10_PHY_BASE 0x5960000ull
#define NIC10_PHY_MAX_OFFSET 0x1000
#define NIC10_PHY_SECTION 0xE800
#define mmNIC10_PHY_SPECIAL_BASE 0x5960E80ull
#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC10_PHY_SPECIAL_SECTION 0x7180
#define mmPRT10_MAC_AUX_BASE 0x5968000ull
#define PRT10_MAC_AUX_MAX_OFFSET 0x1000
#define PRT10_MAC_AUX_SECTION 0xE800
#define mmPRT10_MAC_AUX_SPECIAL_BASE 0x5968E80ull
#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT10_MAC_CORE_BASE 0x5969000ull
#define PRT10_MAC_CORE_MAX_OFFSET 0x1000
#define PRT10_MAC_CORE_SECTION 0xE800
#define mmPRT10_MAC_CORE_SPECIAL_BASE 0x5969E80ull
#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC10_MAC_RS_FEC_BASE 0x596A000ull
#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC10_MAC_RS_FEC_SECTION 0x1000
#define mmNIC10_MAC_GLOB_STAT_CONTROL_REG_BASE 0x596B000ull
#define NIC10_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC10_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC10_MAC_GLOB_STAT_RX0_BASE 0x596B100ull
#define NIC10_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC10_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC10_MAC_GLOB_STAT_RX1_BASE 0x596B18Cull
#define NIC10_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC10_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC10_MAC_GLOB_STAT_RX2_BASE 0x596B218ull
#define NIC10_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC10_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC10_MAC_GLOB_STAT_RX3_BASE 0x596B2A4ull
#define NIC10_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC10_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC10_MAC_GLOB_STAT_TX0_BASE 0x596B330ull
#define NIC10_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC10_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC10_MAC_GLOB_STAT_TX1_BASE 0x596B398ull
#define NIC10_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC10_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC10_MAC_GLOB_STAT_TX2_BASE 0x596B400ull
#define NIC10_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC10_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC10_MAC_GLOB_STAT_TX3_BASE 0x596B468ull
#define NIC10_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC10_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC10_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x596B800ull
#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC10_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC10_MAC_CH0_MAC_PCS_BASE 0x596C000ull
#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC10_MAC_CH0_MAC_128_BASE 0x596C400ull
#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC10_MAC_CH0_MAC_AN_BASE 0x596C800ull
#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC10_MAC_CH1_MAC_PCS_BASE 0x596D000ull
#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC10_MAC_CH1_MAC_128_BASE 0x596D400ull
#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC10_MAC_CH1_MAC_AN_BASE 0x596D800ull
#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC10_MAC_CH2_MAC_PCS_BASE 0x596E000ull
#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC10_MAC_CH2_MAC_128_BASE 0x596E400ull
#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC10_MAC_CH2_MAC_AN_BASE 0x596E800ull
#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC10_MAC_CH3_MAC_PCS_BASE 0x596F000ull
#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC10_MAC_CH3_MAC_128_BASE 0x596F400ull
#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC10_MAC_CH3_MAC_AN_BASE 0x596F800ull
#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800
#define mmNIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x5980000ull
#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x5980080ull
#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x5980100ull
#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x5980180ull
#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_0_SPECIAL_BASE 0x5980E80ull
#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x5981000ull
#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x5981080ull
#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x5981100ull
#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x5981180ull
#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_1_SPECIAL_BASE 0x5981E80ull
#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x5982000ull
#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x5982080ull
#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x5982100ull
#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x5982180ull
#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_2_SPECIAL_BASE 0x5982E80ull
#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x5983000ull
#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x5983080ull
#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x5983100ull
#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x5983180ull
#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_3_SPECIAL_BASE 0x5983E80ull
#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x5984000ull
#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x5984080ull
#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x5984100ull
#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x5984180ull
#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_4_SPECIAL_BASE 0x5984E80ull
#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x5985000ull
#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x5985080ull
#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x5985100ull
#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x5985180ull
#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_5_SPECIAL_BASE 0x5985E80ull
#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x5986000ull
#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x5986080ull
#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x5986100ull
#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x5986180ull
#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_6_SPECIAL_BASE 0x5986E80ull
#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x5987000ull
#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x5987080ull
#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x5987100ull
#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x5987180ull
#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_7_SPECIAL_BASE 0x5987E80ull
#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x5988000ull
#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x5988080ull
#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x5988100ull
#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x5988180ull
#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_8_SPECIAL_BASE 0x5988E80ull
#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x5989000ull
#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x5989080ull
#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x5989100ull
#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x5989180ull
#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_9_SPECIAL_BASE 0x5989E80ull
#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x598A000ull
#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x598A080ull
#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x598A100ull
#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x598A180ull
#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_10_SPECIAL_BASE 0x598AE80ull
#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x598B000ull
#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x598B080ull
#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x598B100ull
#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x598B180ull
#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_11_SPECIAL_BASE 0x598BE80ull
#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x598C000ull
#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x598C080ull
#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x598C100ull
#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x598C180ull
#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_12_SPECIAL_BASE 0x598CE80ull
#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x598D000ull
#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x598D080ull
#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x598D100ull
#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x598D180ull
#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_13_SPECIAL_BASE 0x598DE80ull
#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x598E000ull
#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x598E080ull
#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x598E100ull
#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x598E180ull
#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR0_14_SPECIAL_BASE 0x598EE80ull
#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180
#define mmNIC11_QM_DCCM0_BASE 0x5990000ull
#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000
#define NIC11_QM_DCCM0_SECTION 0x8000
#define mmNIC11_QM_ARC_AUX0_BASE 0x5998000ull
#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000
#define NIC11_QM_ARC_AUX0_SECTION 0xE800
#define mmNIC11_QM_ARC_AUX0_SPECIAL_BASE 0x5998E80ull
#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180
#define mmNIC11_QM0_BASE 0x599A000ull
#define NIC11_QM0_MAX_OFFSET 0x1000
#define NIC11_QM0_SECTION 0x9000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x599A900ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x599A908ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x599A910ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x599A918ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x599A920ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x599A928ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x599A930ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x599A938ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x599A940ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x599A948ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x599A950ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x599A958ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x599A960ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x599A968ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x599A970ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x599A978ull
#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC11_QM0_AXUSER_SECURED_BASE 0x599AB00ull
#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000
#define mmNIC11_QM0_AXUSER_NONSECURED_BASE 0x599AB80ull
#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC11_QM0_DBG_HBW_BASE 0x599AC00ull
#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800
#define NIC11_QM0_DBG_HBW_SECTION 0x8000
#define mmNIC11_QM0_DBG_LBW_BASE 0x599AC80ull
#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800
#define NIC11_QM0_DBG_LBW_SECTION 0x1000
#define mmNIC11_QM0_CGM_BASE 0x599AD80ull
#define NIC11_QM0_CGM_MAX_OFFSET 0xC000
#define NIC11_QM0_CGM_SECTION 0x1000
#define mmNIC11_QM0_SPECIAL_BASE 0x599AE80ull
#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QM0_SPECIAL_SECTION 0x4180
#define mmNIC11_QPC0_BASE 0x599F000ull
#define NIC11_QPC0_MAX_OFFSET 0x1000
#define NIC11_QPC0_SECTION 0x7200
#define mmNIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x599F720ull
#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x599F728ull
#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x599F730ull
#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x599F738ull
#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x599F740ull
#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x599F748ull
#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x599F750ull
#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x599F758ull
#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x599F760ull
#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x599F768ull
#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x599F770ull
#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x599F778ull
#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x599F780ull
#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x599F788ull
#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x599F790ull
#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x599F798ull
#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x599F7A0ull
#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x599F7A8ull
#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x599F7B0ull
#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x599F7B8ull
#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x599F7C0ull
#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x599F7C8ull
#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x599F7D0ull
#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x599F7D8ull
#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x599F7E0ull
#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x599F7E8ull
#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x599F7F0ull
#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x599F7F8ull
#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x599F800ull
#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x599F808ull
#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x599F810ull
#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x599F818ull
#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC11_QPC0_AXUSER_CONG_QUE_BASE 0x599FB80ull
#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_RXWQE_BASE 0x599FBE0ull
#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x599FC40ull
#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_DB_FIFO_BASE 0x599FCA0ull
#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x599FD00ull
#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x599FD60ull
#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_QPC_RESP_BASE 0x599FDC0ull
#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC11_QPC0_AXUSER_QPC_REQ_BASE 0x599FE20ull
#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC11_QPC0_SPECIAL_BASE 0x599FE80ull
#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QPC0_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x59A0000ull
#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x59A0080ull
#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x59A0100ull
#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x59A0180ull
#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_0_SPECIAL_BASE 0x59A0E80ull
#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x59A1000ull
#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x59A1080ull
#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x59A1100ull
#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x59A1180ull
#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_1_SPECIAL_BASE 0x59A1E80ull
#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x59A2000ull
#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x59A2080ull
#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x59A2100ull
#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x59A2180ull
#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_2_SPECIAL_BASE 0x59A2E80ull
#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x59A3000ull
#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x59A3080ull
#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x59A3100ull
#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x59A3180ull
#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_3_SPECIAL_BASE 0x59A3E80ull
#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x59A4000ull
#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x59A4080ull
#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x59A4100ull
#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x59A4180ull
#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_4_SPECIAL_BASE 0x59A4E80ull
#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x59A5000ull
#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x59A5080ull
#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x59A5100ull
#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x59A5180ull
#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_5_SPECIAL_BASE 0x59A5E80ull
#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x59A6000ull
#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x59A6080ull
#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x59A6100ull
#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x59A6180ull
#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_6_SPECIAL_BASE 0x59A6E80ull
#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x59A7000ull
#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x59A7080ull
#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x59A7100ull
#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x59A7180ull
#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_7_SPECIAL_BASE 0x59A7E80ull
#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x59A8000ull
#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x59A8080ull
#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x59A8100ull
#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x59A8180ull
#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_8_SPECIAL_BASE 0x59A8E80ull
#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x59A9000ull
#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x59A9080ull
#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x59A9100ull
#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x59A9180ull
#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_9_SPECIAL_BASE 0x59A9E80ull
#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x59AA000ull
#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x59AA080ull
#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x59AA100ull
#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x59AA180ull
#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_10_SPECIAL_BASE 0x59AAE80ull
#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x59AB000ull
#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x59AB080ull
#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x59AB100ull
#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x59AB180ull
#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_11_SPECIAL_BASE 0x59ABE80ull
#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x59AC000ull
#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x59AC080ull
#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x59AC100ull
#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x59AC180ull
#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_12_SPECIAL_BASE 0x59ACE80ull
#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x59AD000ull
#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x59AD080ull
#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x59AD100ull
#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x59AD180ull
#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_13_SPECIAL_BASE 0x59ADE80ull
#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800
#define mmNIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x59AE000ull
#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000
#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000
#define mmNIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x59AE080ull
#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000
#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000
#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x59AE100ull
#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000
#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000
#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x59AE180ull
#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000
#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000
#define mmNIC11_UMR1_14_SPECIAL_BASE 0x59AEE80ull
#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180
#define mmNIC11_QM_DCCM1_BASE 0x59B0000ull
#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000
#define NIC11_QM_DCCM1_SECTION 0x8000
#define mmNIC11_QM_ARC_AUX1_BASE 0x59B8000ull
#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000
#define NIC11_QM_ARC_AUX1_SECTION 0xE800
#define mmNIC11_QM_ARC_AUX1_SPECIAL_BASE 0x59B8E80ull
#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180
#define mmNIC11_QM1_BASE 0x59BA000ull
#define NIC11_QM1_MAX_OFFSET 0x1000
#define NIC11_QM1_SECTION 0x9000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x59BA900ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x59BA908ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x59BA910ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x59BA918ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x59BA920ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x59BA928ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x59BA930ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x59BA938ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x59BA940ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x59BA948ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x59BA950ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x59BA958ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x59BA960ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x59BA968ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x59BA970ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000
#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x59BA978ull
#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000
#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880
#define mmNIC11_QM1_AXUSER_SECURED_BASE 0x59BAB00ull
#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000
#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000
#define mmNIC11_QM1_AXUSER_NONSECURED_BASE 0x59BAB80ull
#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000
#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000
#define mmNIC11_QM1_DBG_HBW_BASE 0x59BAC00ull
#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800
#define NIC11_QM1_DBG_HBW_SECTION 0x8000
#define mmNIC11_QM1_DBG_LBW_BASE 0x59BAC80ull
#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800
#define NIC11_QM1_DBG_LBW_SECTION 0x1000
#define mmNIC11_QM1_CGM_BASE 0x59BAD80ull
#define NIC11_QM1_CGM_MAX_OFFSET 0xC000
#define NIC11_QM1_CGM_SECTION 0x1000
#define mmNIC11_QM1_SPECIAL_BASE 0x59BAE80ull
#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QM1_SPECIAL_SECTION 0x4180
#define mmNIC11_QPC1_BASE 0x59BF000ull
#define NIC11_QPC1_MAX_OFFSET 0x1000
#define NIC11_QPC1_SECTION 0x7200
#define mmNIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x59BF720ull
#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x59BF728ull
#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x59BF730ull
#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x59BF738ull
#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x59BF740ull
#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x59BF748ull
#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x59BF750ull
#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x59BF758ull
#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x59BF760ull
#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x59BF768ull
#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x59BF770ull
#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x59BF778ull
#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x59BF780ull
#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x59BF788ull
#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x59BF790ull
#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x59BF798ull
#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x59BF7A0ull
#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x59BF7A8ull
#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x59BF7B0ull
#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x59BF7B8ull
#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x59BF7C0ull
#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x59BF7C8ull
#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x59BF7D0ull
#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x59BF7D8ull
#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x59BF7E0ull
#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x59BF7E8ull
#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x59BF7F0ull
#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x59BF7F8ull
#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x59BF800ull
#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x59BF808ull
#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x59BF810ull
#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000
#define mmNIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x59BF818ull
#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000
#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680
#define mmNIC11_QPC1_AXUSER_CONG_QUE_BASE 0x59BFB80ull
#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_RXWQE_BASE 0x59BFBE0ull
#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x59BFC40ull
#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_DB_FIFO_BASE 0x59BFCA0ull
#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x59BFD00ull
#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x59BFD60ull
#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_QPC_RESP_BASE 0x59BFDC0ull
#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000
#define mmNIC11_QPC1_AXUSER_QPC_REQ_BASE 0x59BFE20ull
#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000
#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000
#define mmNIC11_QPC1_SPECIAL_BASE 0x59BFE80ull
#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_QPC1_SPECIAL_SECTION 0x8180
#define mmNIC11_TMR_BASE 0x59C8000ull
#define NIC11_TMR_MAX_OFFSET 0x1000
#define NIC11_TMR_SECTION 0xD600
#define mmNIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x59C8D60ull
#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000
#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000
#define mmNIC11_TMR_AXUSER_TMR_FIFO_BASE 0x59C8DC0ull
#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000
#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000
#define mmNIC11_TMR_AXUSER_TMR_FSM_BASE 0x59C8E20ull
#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000
#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000
#define mmNIC11_TMR_SPECIAL_BASE 0x59C8E80ull
#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TMR_SPECIAL_SECTION 0x1800
#define mmNIC11_RXB_CORE_BASE 0x59C9000ull
#define NIC11_RXB_CORE_MAX_OFFSET 0x1000
#define NIC11_RXB_CORE_SECTION 0x6100
#define mmNIC11_RXB_CORE_SCT_AWUSER_BASE 0x59C9610ull
#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000
#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700
#define mmNIC11_RXB_CORE_SPECIAL_BASE 0x59C9E80ull
#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800
#define mmNIC11_RXE0_BASE 0x59CA000ull
#define NIC11_RXE0_MAX_OFFSET 0x1000
#define NIC11_RXE0_SECTION 0x9000
#define mmNIC11_RXE0_WQE_ARUSER_BASE 0x59CA900ull
#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800
#define mmNIC11_RXE0_SPECIAL_BASE 0x59CAE80ull
#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_RXE0_SPECIAL_SECTION 0x1800
#define mmNIC11_RXE1_BASE 0x59CB000ull
#define NIC11_RXE1_MAX_OFFSET 0x1000
#define NIC11_RXE1_SECTION 0x9000
#define mmNIC11_RXE1_WQE_ARUSER_BASE 0x59CB900ull
#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000
#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800
#define mmNIC11_RXE1_SPECIAL_BASE 0x59CBE80ull
#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_RXE1_SPECIAL_SECTION 0x1800
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x59CC000ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x59CC050ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x59CC0A0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x59CC0F0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x59CC140ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x59CC190ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x59CC1E0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x59CC230ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x59CC280ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x59CC2D0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x59CC320ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x59CC370ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x59CC3C0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x59CC410ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x59CC460ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x59CC4B0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x59CC500ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x59CC550ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x59CC5A0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x59CC5F0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x59CC640ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x59CC690ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x59CC6E0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x59CC730ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x59CC780ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x59CC7D0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x59CC820ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x59CC870ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x59CC8C0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x59CC910ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x59CC960ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x59CC9B0ull
#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC11_RXE0_AXUSER_SPECIAL_BASE 0x59CCE80ull
#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x59CD000ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x59CD050ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x59CD0A0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x59CD0F0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x59CD140ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x59CD190ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x59CD1E0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x59CD230ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x59CD280ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x59CD2D0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x59CD320ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x59CD370ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x59CD3C0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x59CD410ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x59CD460ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x59CD4B0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x59CD500ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x59CD550ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x59CD5A0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x59CD5F0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x59CD640ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x59CD690ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x59CD6E0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x59CD730ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x59CD780ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x59CD7D0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x59CD820ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x59CD870ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x59CD8C0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x59CD910ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x59CD960ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000
#define mmNIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x59CD9B0ull
#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000
#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00
#define mmNIC11_RXE1_AXUSER_SPECIAL_BASE 0x59CDE80ull
#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180
#define mmNIC11_TXS0_BASE 0x59D0000ull
#define NIC11_TXS0_MAX_OFFSET 0x1000
#define NIC11_TXS0_SECTION 0xE800
#define mmNIC11_TXS0_SPECIAL_BASE 0x59D0E80ull
#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TXS0_SPECIAL_SECTION 0x1800
#define mmNIC11_TXS1_BASE 0x59D1000ull
#define NIC11_TXS1_MAX_OFFSET 0x1000
#define NIC11_TXS1_SECTION 0xE800
#define mmNIC11_TXS1_SPECIAL_BASE 0x59D1E80ull
#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TXS1_SPECIAL_SECTION 0x1800
#define mmNIC11_TXE0_BASE 0x59D2000ull
#define NIC11_TXE0_MAX_OFFSET 0x1000
#define NIC11_TXE0_SECTION 0xE800
#define mmNIC11_TXE0_SPECIAL_BASE 0x59D2E80ull
#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TXE0_SPECIAL_SECTION 0x1800
#define mmNIC11_TXE1_BASE 0x59D3000ull
#define NIC11_TXE1_MAX_OFFSET 0x1000
#define NIC11_TXE1_SECTION 0xE800
#define mmNIC11_TXE1_SPECIAL_BASE 0x59D3E80ull
#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TXE1_SPECIAL_SECTION 0x1800
#define mmNIC11_TXB_BASE 0x59D4000ull
#define NIC11_TXB_MAX_OFFSET 0x1000
#define NIC11_TXB_SECTION 0xE800
#define mmNIC11_TXB_SPECIAL_BASE 0x59D4E80ull
#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_TXB_SPECIAL_SECTION 0x1800
#define mmNIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x59D5000ull
#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0
#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000
#define mmNIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x59D5200ull
#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0
#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000
#define mmNIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x59D5400ull
#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0
#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000
#define mmNIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x59D5600ull
#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0
#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000
#define mmNIC11_MSTR_IF_E2E_CRDT_BASE 0x59D5800ull
#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400
#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800
#define mmNIC11_MSTR_IF_AXUSER_BASE 0x59D5A80ull
#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000
#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000
#define mmNIC11_MSTR_IF_DBG_HBW_BASE 0x59D5B00ull
#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800
#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000
#define mmNIC11_MSTR_IF_DBG_LBW_BASE 0x59D5B80ull
#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800
#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000
#define mmNIC11_MSTR_IF_CORE_HBW_BASE 0x59D5C00ull
#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200
#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800
#define mmNIC11_MSTR_IF_CORE_LBW_BASE 0x59D5D80ull
#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000
#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000
#define mmNIC11_MSTR_IF_SPECIAL_BASE 0x59D5E80ull
#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800
#define mmNIC11_TX_AXUSER_BASE 0x59D6000ull
#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000
#define NIC11_TX_AXUSER_SECTION 0x2000
#define mmNIC11_SERDES0_BASE 0x59D8000ull
#define NIC11_SERDES0_MAX_OFFSET 0x3E40
#define NIC11_SERDES0_SECTION 0x4000
#define mmNIC11_SERDES1_BASE 0x59DC000ull
#define NIC11_SERDES1_MAX_OFFSET 0x3E40
#define NIC11_SERDES1_SECTION 0x4000
#define mmNIC11_PHY_BASE 0x59E0000ull
#define NIC11_PHY_MAX_OFFSET 0x1000
#define NIC11_PHY_SECTION 0xE800
#define mmNIC11_PHY_SPECIAL_BASE 0x59E0E80ull
#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800
#define NIC11_PHY_SPECIAL_SECTION 0x7180
#define mmPRT11_MAC_AUX_BASE 0x59E8000ull
#define PRT11_MAC_AUX_MAX_OFFSET 0x1000
#define PRT11_MAC_AUX_SECTION 0xE800
#define mmPRT11_MAC_AUX_SPECIAL_BASE 0x59E8E80ull
#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800
#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800
#define mmPRT11_MAC_CORE_BASE 0x59E9000ull
#define PRT11_MAC_CORE_MAX_OFFSET 0x1000
#define PRT11_MAC_CORE_SECTION 0xE800
#define mmPRT11_MAC_CORE_SPECIAL_BASE 0x59E9E80ull
#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800
#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800
#define mmNIC11_MAC_RS_FEC_BASE 0x59EA000ull
#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0
#define NIC11_MAC_RS_FEC_SECTION 0x1000
#define mmNIC11_MAC_GLOB_STAT_CONTROL_REG_BASE 0x59EB000ull
#define NIC11_MAC_GLOB_STAT_CONTROL_REG_MAX_OFFSET 0x2000
#define NIC11_MAC_GLOB_STAT_CONTROL_REG_SECTION 0x1000
#define mmNIC11_MAC_GLOB_STAT_RX0_BASE 0x59EB100ull
#define NIC11_MAC_GLOB_STAT_RX0_MAX_OFFSET 0x8C00
#define NIC11_MAC_GLOB_STAT_RX0_SECTION 0x8C00
#define mmNIC11_MAC_GLOB_STAT_RX1_BASE 0x59EB18Cull
#define NIC11_MAC_GLOB_STAT_RX1_MAX_OFFSET 0x8C00
#define NIC11_MAC_GLOB_STAT_RX1_SECTION 0x8C00
#define mmNIC11_MAC_GLOB_STAT_RX2_BASE 0x59EB218ull
#define NIC11_MAC_GLOB_STAT_RX2_MAX_OFFSET 0x8C00
#define NIC11_MAC_GLOB_STAT_RX2_SECTION 0x8C00
#define mmNIC11_MAC_GLOB_STAT_RX3_BASE 0x59EB2A4ull
#define NIC11_MAC_GLOB_STAT_RX3_MAX_OFFSET 0x8C00
#define NIC11_MAC_GLOB_STAT_RX3_SECTION 0x8C00
#define mmNIC11_MAC_GLOB_STAT_TX0_BASE 0x59EB330ull
#define NIC11_MAC_GLOB_STAT_TX0_MAX_OFFSET 0x6800
#define NIC11_MAC_GLOB_STAT_TX0_SECTION 0x6800
#define mmNIC11_MAC_GLOB_STAT_TX1_BASE 0x59EB398ull
#define NIC11_MAC_GLOB_STAT_TX1_MAX_OFFSET 0x6800
#define NIC11_MAC_GLOB_STAT_TX1_SECTION 0x6800
#define mmNIC11_MAC_GLOB_STAT_TX2_BASE 0x59EB400ull
#define NIC11_MAC_GLOB_STAT_TX2_MAX_OFFSET 0x6800
#define NIC11_MAC_GLOB_STAT_TX2_SECTION 0x6800
#define mmNIC11_MAC_GLOB_STAT_TX3_BASE 0x59EB468ull
#define NIC11_MAC_GLOB_STAT_TX3_MAX_OFFSET 0x6800
#define NIC11_MAC_GLOB_STAT_TX3_SECTION 0x3980
#define mmNIC11_MAC_GLOB_STAT_RSFEC_STATS_BASE 0x59EB800ull
#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_MAX_OFFSET 0x1EC0
#define NIC11_MAC_GLOB_STAT_RSFEC_STATS_SECTION 0x8000
#define mmNIC11_MAC_CH0_MAC_PCS_BASE 0x59EC000ull
#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000
#define mmNIC11_MAC_CH0_MAC_128_BASE 0x59EC400ull
#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400
#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000
#define mmNIC11_MAC_CH0_MAC_AN_BASE 0x59EC800ull
#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400
#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000
#define mmNIC11_MAC_CH1_MAC_PCS_BASE 0x59ED000ull
#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000
#define mmNIC11_MAC_CH1_MAC_128_BASE 0x59ED400ull
#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400
#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000
#define mmNIC11_MAC_CH1_MAC_AN_BASE 0x59ED800ull
#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400
#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000
#define mmNIC11_MAC_CH2_MAC_PCS_BASE 0x59EE000ull
#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000
#define mmNIC11_MAC_CH2_MAC_128_BASE 0x59EE400ull
#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400
#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000
#define mmNIC11_MAC_CH2_MAC_AN_BASE 0x59EE800ull
#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400
#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000
#define mmNIC11_MAC_CH3_MAC_PCS_BASE 0x59EF000ull
#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0
#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000
#define mmNIC11_MAC_CH3_MAC_128_BASE 0x59EF400ull
#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400
#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000
#define mmNIC11_MAC_CH3_MAC_AN_BASE 0x59EF800ull
#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400
#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800
#define mmDCORE0_ROM_TABLE_L_BASE 0x6000000ull
#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000
#define DCORE0_ROM_TABLE_L_SECTION 0x80000
#define mmDCORE0_HMMU0_CS_ROM_TBL_BASE 0x6080000ull
#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_HMMU0_CS_STM_BASE 0x6081000ull
#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_CS_STM_SECTION 0x1000
#define mmDCORE0_HMMU0_CS_CTI_BASE 0x6082000ull
#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000
#define mmDCORE0_HMMU0_CS_ETF_BASE 0x6083000ull
#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000
#define mmDCORE0_HMMU0_CS_SPMU_BASE 0x6084000ull
#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_CTI_BASE 0x6085000ull
#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000
#define mmDCORE0_HMMU0_USER_CTI_BASE 0x6086000ull
#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_0_BASE 0x6087000ull
#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_0_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_1_BASE 0x6088000ull
#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_1_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_3_BASE 0x6089000ull
#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_3_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_2_BASE 0x608A000ull
#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_2_SECTION 0x1000
#define mmDCORE0_HMMU0_BMON_4_BASE 0x608B000ull
#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000
#define DCORE0_HMMU0_BMON_4_SECTION 0x5000
#define mmDCORE0_HMMU1_CS_ROM_TBL_BASE 0x6090000ull
#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_HMMU1_CS_STM_BASE 0x6091000ull
#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_CS_STM_SECTION 0x1000
#define mmDCORE0_HMMU1_CS_CTI_BASE 0x6092000ull
#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000
#define mmDCORE0_HMMU1_CS_ETF_BASE 0x6093000ull
#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000
#define mmDCORE0_HMMU1_CS_SPMU_BASE 0x6094000ull
#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_CTI_BASE 0x6095000ull
#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000
#define mmDCORE0_HMMU1_USER_CTI_BASE 0x6096000ull
#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_0_BASE 0x6097000ull
#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_0_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_1_BASE 0x6098000ull
#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_1_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_3_BASE 0x6099000ull
#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_3_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_2_BASE 0x609A000ull
#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_2_SECTION 0x1000
#define mmDCORE0_HMMU1_BMON_4_BASE 0x609B000ull
#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000
#define DCORE0_HMMU1_BMON_4_SECTION 0x5000
#define mmDCORE0_HMMU2_CS_ROM_TBL_BASE 0x60A0000ull
#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_HMMU2_CS_STM_BASE 0x60A1000ull
#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_CS_STM_SECTION 0x1000
#define mmDCORE0_HMMU2_CS_CTI_BASE 0x60A2000ull
#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000
#define mmDCORE0_HMMU2_CS_ETF_BASE 0x60A3000ull
#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000
#define mmDCORE0_HMMU2_CS_SPMU_BASE 0x60A4000ull
#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_CTI_BASE 0x60A5000ull
#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000
#define mmDCORE0_HMMU2_USER_CTI_BASE 0x60A6000ull
#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_0_BASE 0x60A7000ull
#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_0_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_1_BASE 0x60A8000ull
#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_1_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_3_BASE 0x60A9000ull
#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_3_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_2_BASE 0x60AA000ull
#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_2_SECTION 0x1000
#define mmDCORE0_HMMU2_BMON_4_BASE 0x60AB000ull
#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000
#define DCORE0_HMMU2_BMON_4_SECTION 0x5000
#define mmDCORE0_HMMU3_CS_ROM_TBL_BASE 0x60B0000ull
#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_HMMU3_CS_STM_BASE 0x60B1000ull
#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_CS_STM_SECTION 0x1000
#define mmDCORE0_HMMU3_CS_CTI_BASE 0x60B2000ull
#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000
#define mmDCORE0_HMMU3_CS_ETF_BASE 0x60B3000ull
#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000
#define mmDCORE0_HMMU3_CS_SPMU_BASE 0x60B4000ull
#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_CTI_BASE 0x60B5000ull
#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000
#define mmDCORE0_HMMU3_USER_CTI_BASE 0x60B6000ull
#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_0_BASE 0x60B7000ull
#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_0_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_1_BASE 0x60B8000ull
#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_1_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_3_BASE 0x60B9000ull
#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_3_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_2_BASE 0x60BA000ull
#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_2_SECTION 0x1000
#define mmDCORE0_HMMU3_BMON_4_BASE 0x60BB000ull
#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000
#define DCORE0_HMMU3_BMON_4_SECTION 0x5000
#define mmDCORE0_MME_CTRL_ROM_TABLE_BASE 0x60C0000ull
#define DCORE0_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_MME_CTRL_STM_BASE 0x60C1000ull
#define DCORE0_MME_CTRL_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_STM_SECTION 0x1000
#define mmDCORE0_MME_CTRL_CTI_BASE 0x60C2000ull
#define DCORE0_MME_CTRL_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_CTI_SECTION 0x1000
#define mmDCORE0_MME_CTRL_ETF_BASE 0x60C3000ull
#define DCORE0_MME_CTRL_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_ETF_SECTION 0x1000
#define mmDCORE0_MME_CTRL_SPMU_BASE 0x60C4000ull
#define DCORE0_MME_CTRL_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_SPMU_SECTION 0x1000
#define mmDCORE0_MME_CTRL_CTI0_BASE 0x60C5000ull
#define DCORE0_MME_CTRL_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_CTI0_SECTION 0x1000
#define mmDCORE0_MME_CTRL_CTI1_BASE 0x60C6000ull
#define DCORE0_MME_CTRL_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_CTI1_SECTION 0x1000
#define mmDCORE0_MME_CTRL_BMON0_BASE 0x60C7000ull
#define DCORE0_MME_CTRL_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_BMON0_SECTION 0x1000
#define mmDCORE0_MME_CTRL_BMON1_BASE 0x60C8000ull
#define DCORE0_MME_CTRL_BMON1_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_BMON1_SECTION 0x1000
#define mmDCORE0_MME_CTRL_BMON2_BASE 0x60C9000ull
#define DCORE0_MME_CTRL_BMON2_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_BMON2_SECTION 0x1000
#define mmDCORE0_MME_CTRL_BMON3_BASE 0x60CA000ull
#define DCORE0_MME_CTRL_BMON3_MAX_OFFSET 0x1000
#define DCORE0_MME_CTRL_BMON3_SECTION 0x1000
#define mmDCORE0_MME_CTRL_ARC_RTT_BASE 0x60CB000ull
#define DCORE0_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_MME_CTRL_ARC_RTT_SECTION 0x5000
#define mmDCORE0_MME_SBTE0_ROM_TBL_BASE 0x60D0000ull
#define DCORE0_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_STM_BASE 0x60D1000ull
#define DCORE0_MME_SBTE0_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_STM_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_CTI_BASE 0x60D2000ull
#define DCORE0_MME_SBTE0_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_CTI_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_ETF_BASE 0x60D3000ull
#define DCORE0_MME_SBTE0_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_ETF_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_SPMU_BASE 0x60D4000ull
#define DCORE0_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_SPMU_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_CTI0_BASE 0x60D5000ull
#define DCORE0_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_CTI0_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_CTI1_BASE 0x60D6000ull
#define DCORE0_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_CTI1_SECTION 0x1000
#define mmDCORE0_MME_SBTE0_BMON0_BASE 0x60D7000ull
#define DCORE0_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE0_BMON0_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_ROM_TBL_BASE 0x60D8000ull
#define DCORE0_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_STM_BASE 0x60D9000ull
#define DCORE0_MME_SBTE1_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_STM_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_CTI_BASE 0x60DA000ull
#define DCORE0_MME_SBTE1_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_CTI_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_ETF_BASE 0x60DB000ull
#define DCORE0_MME_SBTE1_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_ETF_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_SPMU_BASE 0x60DC000ull
#define DCORE0_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_SPMU_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_CTI0_BASE 0x60DD000ull
#define DCORE0_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_CTI0_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_CTI1_BASE 0x60DE000ull
#define DCORE0_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_CTI1_SECTION 0x1000
#define mmDCORE0_MME_SBTE1_BMON0_BASE 0x60DF000ull
#define DCORE0_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE1_BMON0_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_ROM_TBL_BASE 0x60E0000ull
#define DCORE0_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_STM_BASE 0x60E1000ull
#define DCORE0_MME_SBTE2_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_STM_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_CTI_BASE 0x60E2000ull
#define DCORE0_MME_SBTE2_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_CTI_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_ETF_BASE 0x60E3000ull
#define DCORE0_MME_SBTE2_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_ETF_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_SPMU_BASE 0x60E4000ull
#define DCORE0_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_SPMU_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_CTI0_BASE 0x60E5000ull
#define DCORE0_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_CTI0_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_CTI1_BASE 0x60E6000ull
#define DCORE0_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_CTI1_SECTION 0x1000
#define mmDCORE0_MME_SBTE2_BMON0_BASE 0x60E7000ull
#define DCORE0_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE2_BMON0_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_ROM_TBL_BASE 0x60E8000ull
#define DCORE0_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_STM_BASE 0x60E9000ull
#define DCORE0_MME_SBTE3_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_STM_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_CTI_BASE 0x60EA000ull
#define DCORE0_MME_SBTE3_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_CTI_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_ETF_BASE 0x60EB000ull
#define DCORE0_MME_SBTE3_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_ETF_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_SPMU_BASE 0x60EC000ull
#define DCORE0_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_SPMU_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_CTI0_BASE 0x60ED000ull
#define DCORE0_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_CTI0_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_CTI1_BASE 0x60EE000ull
#define DCORE0_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_CTI1_SECTION 0x1000
#define mmDCORE0_MME_SBTE3_BMON0_BASE 0x60EF000ull
#define DCORE0_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE3_BMON0_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_ROM_TBL_BASE 0x60F0000ull
#define DCORE0_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_STM_BASE 0x60F1000ull
#define DCORE0_MME_SBTE4_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_STM_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_CTI_BASE 0x60F2000ull
#define DCORE0_MME_SBTE4_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_CTI_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_ETF_BASE 0x60F3000ull
#define DCORE0_MME_SBTE4_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_ETF_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_SPMU_BASE 0x60F4000ull
#define DCORE0_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_SPMU_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_CTI0_BASE 0x60F5000ull
#define DCORE0_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_CTI0_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_CTI1_BASE 0x60F6000ull
#define DCORE0_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_CTI1_SECTION 0x1000
#define mmDCORE0_MME_SBTE4_BMON0_BASE 0x60F7000ull
#define DCORE0_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_SBTE4_BMON0_SECTION 0x9000
#define mmDCORE0_MME_ACC_CS_ROM_TBL_BASE 0x6100000ull
#define DCORE0_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_MME_ACC_STM_BASE 0x6101000ull
#define DCORE0_MME_ACC_STM_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_STM_SECTION 0x1000
#define mmDCORE0_MME_ACC_CTI_BASE 0x6102000ull
#define DCORE0_MME_ACC_CTI_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_CTI_SECTION 0x1000
#define mmDCORE0_MME_ACC_ETF_BASE 0x6103000ull
#define DCORE0_MME_ACC_ETF_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_ETF_SECTION 0x1000
#define mmDCORE0_MME_ACC_SPMU_BASE 0x6104000ull
#define DCORE0_MME_ACC_SPMU_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_SPMU_SECTION 0x1000
#define mmDCORE0_MME_ACC_CTI0_BASE 0x6105000ull
#define DCORE0_MME_ACC_CTI0_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_CTI0_SECTION 0x1000
#define mmDCORE0_MME_ACC_CTI1_BASE 0x6106000ull
#define DCORE0_MME_ACC_CTI1_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_CTI1_SECTION 0x1000
#define mmDCORE0_MME_ACC_BMON0_BASE 0x6107000ull
#define DCORE0_MME_ACC_BMON0_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_BMON0_SECTION 0x1000
#define mmDCORE0_MME_ACC_BMON1_BASE 0x6108000ull
#define DCORE0_MME_ACC_BMON1_MAX_OFFSET 0x1000
#define DCORE0_MME_ACC_BMON1_SECTION 0x8000
#define mmDCORE0_SM_CS_DBG_ROM_TBL_BASE 0x6110000ull
#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmDCORE0_SM_STM_BASE 0x6111000ull
#define DCORE0_SM_STM_MAX_OFFSET 0x1000
#define DCORE0_SM_STM_SECTION 0x1000
#define mmDCORE0_SM_CTI_BASE 0x6112000ull
#define DCORE0_SM_CTI_MAX_OFFSET 0x1000
#define DCORE0_SM_CTI_SECTION 0x1000
#define mmDCORE0_SM_ETF_BASE 0x6113000ull
#define DCORE0_SM_ETF_MAX_OFFSET 0x1000
#define DCORE0_SM_ETF_SECTION 0x1000
#define mmDCORE0_SM_SPMU_BASE 0x6114000ull
#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000
#define DCORE0_SM_SPMU_SECTION 0x1000
#define mmDCORE0_SM_BMON_CTI_BASE 0x6115000ull
#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_SM_BMON_CTI_SECTION 0x1000
#define mmDCORE0_SM_USER_CTI_BASE 0x6116000ull
#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_SM_USER_CTI_SECTION 0x1000
#define mmDCORE0_SM_BMON_BASE 0x6117000ull
#define DCORE0_SM_BMON_MAX_OFFSET 0x1000
#define DCORE0_SM_BMON_SECTION 0x1000
#define mmDCORE0_SM_BMON1_BASE 0x6118000ull
#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000
#define DCORE0_SM_BMON1_SECTION 0x18000
#define mmDCORE0_XFT_FUNNEL_BASE 0x6130000ull
#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_XFT_FUNNEL_SECTION 0x8000
#define mmDCORE0_TFT0_FUNNEL_BASE 0x6138000ull
#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TFT0_FUNNEL_SECTION 0x1000
#define mmDCORE0_TFT1_FUNNEL_BASE 0x6139000ull
#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TFT1_FUNNEL_SECTION 0x1000
#define mmDCORE0_TFT2_FUNNEL_BASE 0x613A000ull
#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TFT2_FUNNEL_SECTION 0x7000
#define mmDCORE0_RTR0_FUNNEL_BASE 0x6141000ull
#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR0_FUNNEL_SECTION 0x8000
#define mmDCORE0_RTR1_FUNNEL_BASE 0x6149000ull
#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR1_FUNNEL_SECTION 0x8000
#define mmDCORE0_RTR2_FUNNEL_BASE 0x6151000ull
#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR2_FUNNEL_SECTION 0x8000
#define mmDCORE0_RTR3_FUNNEL_BASE 0x6159000ull
#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR3_FUNNEL_SECTION 0x8000
#define mmDCORE0_RTR4_FUNNEL_BASE 0x6161000ull
#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR4_FUNNEL_SECTION 0x4000
#define mmDCORE0_MIF0_FUNNEL_BASE 0x6165000ull
#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_MIF0_FUNNEL_SECTION 0x4000
#define mmDCORE0_RTR5_FUNNEL_BASE 0x6169000ull
#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR5_FUNNEL_SECTION 0x4000
#define mmDCORE0_MIF1_FUNNEL_BASE 0x616D000ull
#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_MIF1_FUNNEL_SECTION 0x4000
#define mmDCORE0_RTR6_FUNNEL_BASE 0x6171000ull
#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR6_FUNNEL_SECTION 0x4000
#define mmDCORE0_MIF2_FUNNEL_BASE 0x6175000ull
#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_MIF2_FUNNEL_SECTION 0x4000
#define mmDCORE0_RTR7_FUNNEL_BASE 0x6179000ull
#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_RTR7_FUNNEL_SECTION 0x4000
#define mmDCORE0_MIF3_FUNNEL_BASE 0x617D000ull
#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_MIF3_FUNNEL_SECTION 0x43000
#define mmDCORE0_EDMA0_CS_ROM_TBL_BASE 0x61C0000ull
#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_EDMA0_CS_STM_BASE 0x61C1000ull
#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CS_STM_SECTION 0x1000
#define mmDCORE0_EDMA0_CS_CTI_BASE 0x61C2000ull
#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000
#define mmDCORE0_EDMA0_CS_ETF_BASE 0x61C3000ull
#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000
#define mmDCORE0_EDMA0_CS_SPMU_BASE 0x61C4000ull
#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000
#define mmDCORE0_EDMA0_BMON_CTI_BASE 0x61C5000ull
#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000
#define mmDCORE0_EDMA0_USER_CTI_BASE 0x61C6000ull
#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000
#define mmDCORE0_EDMA0_BMON_0_BASE 0x61C7000ull
#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_BMON_0_SECTION 0x1000
#define mmDCORE0_EDMA0_BMON_1_BASE 0x61C8000ull
#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_EDMA0_BMON_1_SECTION 0x1000
#define mmDCORE0_EDMA0_QM_ARC_RTT_BASE 0x61C9000ull
#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE0_EDMA1_CS_ROM_TBL_BASE 0x61D0000ull
#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_EDMA1_CS_STM_BASE 0x61D1000ull
#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CS_STM_SECTION 0x1000
#define mmDCORE0_EDMA1_CS_CTI_BASE 0x61D2000ull
#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000
#define mmDCORE0_EDMA1_CS_ETF_BASE 0x61D3000ull
#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000
#define mmDCORE0_EDMA1_CS_SPMU_BASE 0x61D4000ull
#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000
#define mmDCORE0_EDMA1_BMON_CTI_BASE 0x61D5000ull
#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000
#define mmDCORE0_EDMA1_USER_CTI_BASE 0x61D6000ull
#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000
#define mmDCORE0_EDMA1_BMON_0_BASE 0x61D7000ull
#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_BMON_0_SECTION 0x1000
#define mmDCORE0_EDMA1_BMON_1_BASE 0x61D8000ull
#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_EDMA1_BMON_1_SECTION 0x1000
#define mmDCORE0_EDMA1_QM_ARC_RTT_BASE 0x61D9000ull
#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE0_VDEC0_CS_ROM_TBL_BASE 0x61E0000ull
#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_VDEC0_CS_STM_BASE 0x61E1000ull
#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CS_STM_SECTION 0x1000
#define mmDCORE0_VDEC0_CS_CTI_BASE 0x61E2000ull
#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000
#define mmDCORE0_VDEC0_CS_ETF_BASE 0x61E3000ull
#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000
#define mmDCORE0_VDEC0_CS_SPMU_BASE 0x61E4000ull
#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000
#define mmDCORE0_VDEC0_BMON_CTI_BASE 0x61E5000ull
#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000
#define mmDCORE0_VDEC0_USER_CTI_BASE 0x61E6000ull
#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000
#define mmDCORE0_VDEC0_BMON_0_BASE 0x61E7000ull
#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_BMON_0_SECTION 0x1000
#define mmDCORE0_VDEC0_BMON_1_BASE 0x61E8000ull
#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_BMON_1_SECTION 0x1000
#define mmDCORE0_VDEC0_BMON_2_BASE 0x61E9000ull
#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_VDEC0_BMON_2_SECTION 0x7000
#define mmDCORE0_VDEC1_CS_ROM_TBL_BASE 0x61F0000ull
#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE0_VDEC1_CS_STM_BASE 0x61F1000ull
#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CS_STM_SECTION 0x1000
#define mmDCORE0_VDEC1_CS_CTI_BASE 0x61F2000ull
#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000
#define mmDCORE0_VDEC1_CS_ETF_BASE 0x61F3000ull
#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000
#define mmDCORE0_VDEC1_CS_SPMU_BASE 0x61F4000ull
#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000
#define mmDCORE0_VDEC1_BMON_CTI_BASE 0x61F5000ull
#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000
#define mmDCORE0_VDEC1_USER_CTI_BASE 0x61F6000ull
#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000
#define mmDCORE0_VDEC1_BMON_0_BASE 0x61F7000ull
#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_BMON_0_SECTION 0x1000
#define mmDCORE0_VDEC1_BMON_1_BASE 0x61F8000ull
#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_BMON_1_SECTION 0x1000
#define mmDCORE0_VDEC1_BMON_2_BASE 0x61F9000ull
#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000
#define DCORE0_VDEC1_BMON_2_SECTION 0x7000
#define mmDCORE1_ROM_TABLE_L_BASE 0x6200000ull
#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000
#define DCORE1_ROM_TABLE_L_SECTION 0x80000
#define mmDCORE1_HMMU0_CS_ROM_TBL_BASE 0x6280000ull
#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_HMMU0_CS_STM_BASE 0x6281000ull
#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_CS_STM_SECTION 0x1000
#define mmDCORE1_HMMU0_CS_CTI_BASE 0x6282000ull
#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000
#define mmDCORE1_HMMU0_CS_ETF_BASE 0x6283000ull
#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000
#define mmDCORE1_HMMU0_CS_SPMU_BASE 0x6284000ull
#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_CTI_BASE 0x6285000ull
#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000
#define mmDCORE1_HMMU0_USER_CTI_BASE 0x6286000ull
#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_0_BASE 0x6287000ull
#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_0_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_1_BASE 0x6288000ull
#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_1_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_3_BASE 0x6289000ull
#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_3_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_2_BASE 0x628A000ull
#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_2_SECTION 0x1000
#define mmDCORE1_HMMU0_BMON_4_BASE 0x628B000ull
#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000
#define DCORE1_HMMU0_BMON_4_SECTION 0x5000
#define mmDCORE1_HMMU1_CS_ROM_TBL_BASE 0x6290000ull
#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_HMMU1_CS_STM_BASE 0x6291000ull
#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_CS_STM_SECTION 0x1000
#define mmDCORE1_HMMU1_CS_CTI_BASE 0x6292000ull
#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000
#define mmDCORE1_HMMU1_CS_ETF_BASE 0x6293000ull
#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000
#define mmDCORE1_HMMU1_CS_SPMU_BASE 0x6294000ull
#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_CTI_BASE 0x6295000ull
#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000
#define mmDCORE1_HMMU1_USER_CTI_BASE 0x6296000ull
#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_0_BASE 0x6297000ull
#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_0_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_1_BASE 0x6298000ull
#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_1_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_3_BASE 0x6299000ull
#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_3_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_2_BASE 0x629A000ull
#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_2_SECTION 0x1000
#define mmDCORE1_HMMU1_BMON_4_BASE 0x629B000ull
#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000
#define DCORE1_HMMU1_BMON_4_SECTION 0x5000
#define mmDCORE1_HMMU2_CS_ROM_TBL_BASE 0x62A0000ull
#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_HMMU2_CS_STM_BASE 0x62A1000ull
#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_CS_STM_SECTION 0x1000
#define mmDCORE1_HMMU2_CS_CTI_BASE 0x62A2000ull
#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000
#define mmDCORE1_HMMU2_CS_ETF_BASE 0x62A3000ull
#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000
#define mmDCORE1_HMMU2_CS_SPMU_BASE 0x62A4000ull
#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_CTI_BASE 0x62A5000ull
#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000
#define mmDCORE1_HMMU2_USER_CTI_BASE 0x62A6000ull
#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_0_BASE 0x62A7000ull
#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_0_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_1_BASE 0x62A8000ull
#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_1_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_3_BASE 0x62A9000ull
#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_3_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_2_BASE 0x62AA000ull
#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_2_SECTION 0x1000
#define mmDCORE1_HMMU2_BMON_4_BASE 0x62AB000ull
#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000
#define DCORE1_HMMU2_BMON_4_SECTION 0x5000
#define mmDCORE1_HMMU3_CS_ROM_TBL_BASE 0x62B0000ull
#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_HMMU3_CS_STM_BASE 0x62B1000ull
#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_CS_STM_SECTION 0x1000
#define mmDCORE1_HMMU3_CS_CTI_BASE 0x62B2000ull
#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000
#define mmDCORE1_HMMU3_CS_ETF_BASE 0x62B3000ull
#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000
#define mmDCORE1_HMMU3_CS_SPMU_BASE 0x62B4000ull
#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_CTI_BASE 0x62B5000ull
#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000
#define mmDCORE1_HMMU3_USER_CTI_BASE 0x62B6000ull
#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_0_BASE 0x62B7000ull
#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_0_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_1_BASE 0x62B8000ull
#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_1_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_3_BASE 0x62B9000ull
#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_3_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_2_BASE 0x62BA000ull
#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_2_SECTION 0x1000
#define mmDCORE1_HMMU3_BMON_4_BASE 0x62BB000ull
#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000
#define DCORE1_HMMU3_BMON_4_SECTION 0x5000
#define mmDCORE1_MME_CTRL_ROM_TABLE_BASE 0x62C0000ull
#define DCORE1_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_ROM_TABLE_SECTION 0x1000
#define mmDCORE1_MME_CTRL_STM_BASE 0x62C1000ull
#define DCORE1_MME_CTRL_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_STM_SECTION 0x1000
#define mmDCORE1_MME_CTRL_CTI_BASE 0x62C2000ull
#define DCORE1_MME_CTRL_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_CTI_SECTION 0x1000
#define mmDCORE1_MME_CTRL_ETF_BASE 0x62C3000ull
#define DCORE1_MME_CTRL_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_ETF_SECTION 0x1000
#define mmDCORE1_MME_CTRL_SPMU_BASE 0x62C4000ull
#define DCORE1_MME_CTRL_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_SPMU_SECTION 0x1000
#define mmDCORE1_MME_CTRL_CTI0_BASE 0x62C5000ull
#define DCORE1_MME_CTRL_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_CTI0_SECTION 0x1000
#define mmDCORE1_MME_CTRL_CTI1_BASE 0x62C6000ull
#define DCORE1_MME_CTRL_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_CTI1_SECTION 0x1000
#define mmDCORE1_MME_CTRL_BMON0_BASE 0x62C7000ull
#define DCORE1_MME_CTRL_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_BMON0_SECTION 0x1000
#define mmDCORE1_MME_CTRL_BMON1_BASE 0x62C8000ull
#define DCORE1_MME_CTRL_BMON1_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_BMON1_SECTION 0x1000
#define mmDCORE1_MME_CTRL_BMON2_BASE 0x62C9000ull
#define DCORE1_MME_CTRL_BMON2_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_BMON2_SECTION 0x1000
#define mmDCORE1_MME_CTRL_BMON3_BASE 0x62CA000ull
#define DCORE1_MME_CTRL_BMON3_MAX_OFFSET 0x1000
#define DCORE1_MME_CTRL_BMON3_SECTION 0x1000
#define mmDCORE1_MME_CTRL_ARC_RTT_BASE 0x62CB000ull
#define DCORE1_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_MME_CTRL_ARC_RTT_SECTION 0x5000
#define mmDCORE1_MME_SBTE0_ROM_TBL_BASE 0x62D0000ull
#define DCORE1_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_STM_BASE 0x62D1000ull
#define DCORE1_MME_SBTE0_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_STM_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_CTI_BASE 0x62D2000ull
#define DCORE1_MME_SBTE0_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_CTI_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_ETF_BASE 0x62D3000ull
#define DCORE1_MME_SBTE0_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_ETF_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_SPMU_BASE 0x62D4000ull
#define DCORE1_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_SPMU_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_CTI0_BASE 0x62D5000ull
#define DCORE1_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_CTI0_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_CTI1_BASE 0x62D6000ull
#define DCORE1_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_CTI1_SECTION 0x1000
#define mmDCORE1_MME_SBTE0_BMON0_BASE 0x62D7000ull
#define DCORE1_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE0_BMON0_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_ROM_TBL_BASE 0x62D8000ull
#define DCORE1_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_STM_BASE 0x62D9000ull
#define DCORE1_MME_SBTE1_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_STM_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_CTI_BASE 0x62DA000ull
#define DCORE1_MME_SBTE1_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_CTI_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_ETF_BASE 0x62DB000ull
#define DCORE1_MME_SBTE1_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_ETF_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_SPMU_BASE 0x62DC000ull
#define DCORE1_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_SPMU_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_CTI0_BASE 0x62DD000ull
#define DCORE1_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_CTI0_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_CTI1_BASE 0x62DE000ull
#define DCORE1_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_CTI1_SECTION 0x1000
#define mmDCORE1_MME_SBTE1_BMON0_BASE 0x62DF000ull
#define DCORE1_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE1_BMON0_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_ROM_TBL_BASE 0x62E0000ull
#define DCORE1_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_STM_BASE 0x62E1000ull
#define DCORE1_MME_SBTE2_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_STM_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_CTI_BASE 0x62E2000ull
#define DCORE1_MME_SBTE2_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_CTI_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_ETF_BASE 0x62E3000ull
#define DCORE1_MME_SBTE2_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_ETF_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_SPMU_BASE 0x62E4000ull
#define DCORE1_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_SPMU_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_CTI0_BASE 0x62E5000ull
#define DCORE1_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_CTI0_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_CTI1_BASE 0x62E6000ull
#define DCORE1_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_CTI1_SECTION 0x1000
#define mmDCORE1_MME_SBTE2_BMON0_BASE 0x62E7000ull
#define DCORE1_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE2_BMON0_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_ROM_TBL_BASE 0x62E8000ull
#define DCORE1_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_STM_BASE 0x62E9000ull
#define DCORE1_MME_SBTE3_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_STM_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_CTI_BASE 0x62EA000ull
#define DCORE1_MME_SBTE3_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_CTI_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_ETF_BASE 0x62EB000ull
#define DCORE1_MME_SBTE3_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_ETF_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_SPMU_BASE 0x62EC000ull
#define DCORE1_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_SPMU_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_CTI0_BASE 0x62ED000ull
#define DCORE1_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_CTI0_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_CTI1_BASE 0x62EE000ull
#define DCORE1_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_CTI1_SECTION 0x1000
#define mmDCORE1_MME_SBTE3_BMON0_BASE 0x62EF000ull
#define DCORE1_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE3_BMON0_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_ROM_TBL_BASE 0x62F0000ull
#define DCORE1_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_STM_BASE 0x62F1000ull
#define DCORE1_MME_SBTE4_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_STM_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_CTI_BASE 0x62F2000ull
#define DCORE1_MME_SBTE4_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_CTI_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_ETF_BASE 0x62F3000ull
#define DCORE1_MME_SBTE4_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_ETF_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_SPMU_BASE 0x62F4000ull
#define DCORE1_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_SPMU_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_CTI0_BASE 0x62F5000ull
#define DCORE1_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_CTI0_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_CTI1_BASE 0x62F6000ull
#define DCORE1_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_CTI1_SECTION 0x1000
#define mmDCORE1_MME_SBTE4_BMON0_BASE 0x62F7000ull
#define DCORE1_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_SBTE4_BMON0_SECTION 0x9000
#define mmDCORE1_MME_ACC_CS_ROM_TBL_BASE 0x6300000ull
#define DCORE1_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_MME_ACC_STM_BASE 0x6301000ull
#define DCORE1_MME_ACC_STM_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_STM_SECTION 0x1000
#define mmDCORE1_MME_ACC_CTI_BASE 0x6302000ull
#define DCORE1_MME_ACC_CTI_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_CTI_SECTION 0x1000
#define mmDCORE1_MME_ACC_ETF_BASE 0x6303000ull
#define DCORE1_MME_ACC_ETF_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_ETF_SECTION 0x1000
#define mmDCORE1_MME_ACC_SPMU_BASE 0x6304000ull
#define DCORE1_MME_ACC_SPMU_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_SPMU_SECTION 0x1000
#define mmDCORE1_MME_ACC_CTI0_BASE 0x6305000ull
#define DCORE1_MME_ACC_CTI0_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_CTI0_SECTION 0x1000
#define mmDCORE1_MME_ACC_CTI1_BASE 0x6306000ull
#define DCORE1_MME_ACC_CTI1_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_CTI1_SECTION 0x1000
#define mmDCORE1_MME_ACC_BMON0_BASE 0x6307000ull
#define DCORE1_MME_ACC_BMON0_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_BMON0_SECTION 0x1000
#define mmDCORE1_MME_ACC_BMON1_BASE 0x6308000ull
#define DCORE1_MME_ACC_BMON1_MAX_OFFSET 0x1000
#define DCORE1_MME_ACC_BMON1_SECTION 0x8000
#define mmDCORE1_SM_CS_DBG_ROM_TBL_BASE 0x6310000ull
#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmDCORE1_SM_STM_BASE 0x6311000ull
#define DCORE1_SM_STM_MAX_OFFSET 0x1000
#define DCORE1_SM_STM_SECTION 0x1000
#define mmDCORE1_SM_CTI_BASE 0x6312000ull
#define DCORE1_SM_CTI_MAX_OFFSET 0x1000
#define DCORE1_SM_CTI_SECTION 0x1000
#define mmDCORE1_SM_ETF_BASE 0x6313000ull
#define DCORE1_SM_ETF_MAX_OFFSET 0x1000
#define DCORE1_SM_ETF_SECTION 0x1000
#define mmDCORE1_SM_SPMU_BASE 0x6314000ull
#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000
#define DCORE1_SM_SPMU_SECTION 0x1000
#define mmDCORE1_SM_BMON_CTI_BASE 0x6315000ull
#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_SM_BMON_CTI_SECTION 0x1000
#define mmDCORE1_SM_USER_CTI_BASE 0x6316000ull
#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_SM_USER_CTI_SECTION 0x1000
#define mmDCORE1_SM_BMON_BASE 0x6317000ull
#define DCORE1_SM_BMON_MAX_OFFSET 0x1000
#define DCORE1_SM_BMON_SECTION 0x1000
#define mmDCORE1_SM_BMON1_BASE 0x6318000ull
#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000
#define DCORE1_SM_BMON1_SECTION 0x18000
#define mmDCORE1_XFT_FUNNEL_BASE 0x6330000ull
#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_XFT_FUNNEL_SECTION 0x8000
#define mmDCORE1_TFT0_FUNNEL_BASE 0x6338000ull
#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TFT0_FUNNEL_SECTION 0x1000
#define mmDCORE1_TFT1_FUNNEL_BASE 0x6339000ull
#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TFT1_FUNNEL_SECTION 0x1000
#define mmDCORE1_TFT2_FUNNEL_BASE 0x633A000ull
#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_TFT2_FUNNEL_SECTION 0x7000
#define mmDCORE1_RTR0_FUNNEL_BASE 0x6341000ull
#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR0_FUNNEL_SECTION 0x4000
#define mmDCORE1_MIF0_FUNNEL_BASE 0x6345000ull
#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_MIF0_FUNNEL_SECTION 0x4000
#define mmDCORE1_RTR1_FUNNEL_BASE 0x6349000ull
#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR1_FUNNEL_SECTION 0x4000
#define mmDCORE1_MIF1_FUNNEL_BASE 0x634D000ull
#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_MIF1_FUNNEL_SECTION 0x4000
#define mmDCORE1_RTR2_FUNNEL_BASE 0x6351000ull
#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR2_FUNNEL_SECTION 0x4000
#define mmDCORE1_MIF2_FUNNEL_BASE 0x6355000ull
#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_MIF2_FUNNEL_SECTION 0x4000
#define mmDCORE1_RTR3_FUNNEL_BASE 0x6359000ull
#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR3_FUNNEL_SECTION 0x4000
#define mmDCORE1_MIF3_FUNNEL_BASE 0x635D000ull
#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_MIF3_FUNNEL_SECTION 0x4000
#define mmDCORE1_RTR4_FUNNEL_BASE 0x6361000ull
#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR4_FUNNEL_SECTION 0x8000
#define mmDCORE1_RTR5_FUNNEL_BASE 0x6369000ull
#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR5_FUNNEL_SECTION 0x8000
#define mmDCORE1_RTR6_FUNNEL_BASE 0x6371000ull
#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR6_FUNNEL_SECTION 0x8000
#define mmDCORE1_RTR7_FUNNEL_BASE 0x6379000ull
#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_RTR7_FUNNEL_SECTION 0x47000
#define mmDCORE1_EDMA0_CS_ROM_TBL_BASE 0x63C0000ull
#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_EDMA0_CS_STM_BASE 0x63C1000ull
#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CS_STM_SECTION 0x1000
#define mmDCORE1_EDMA0_CS_CTI_BASE 0x63C2000ull
#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000
#define mmDCORE1_EDMA0_CS_ETF_BASE 0x63C3000ull
#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000
#define mmDCORE1_EDMA0_CS_SPMU_BASE 0x63C4000ull
#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000
#define mmDCORE1_EDMA0_BMON_CTI_BASE 0x63C5000ull
#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000
#define mmDCORE1_EDMA0_USER_CTI_BASE 0x63C6000ull
#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000
#define mmDCORE1_EDMA0_BMON_0_BASE 0x63C7000ull
#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_BMON_0_SECTION 0x1000
#define mmDCORE1_EDMA0_BMON_1_BASE 0x63C8000ull
#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_EDMA0_BMON_1_SECTION 0x1000
#define mmDCORE1_EDMA0_QM_ARC_RTT_BASE 0x63C9000ull
#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE1_EDMA1_CS_ROM_TBL_BASE 0x63D0000ull
#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_EDMA1_CS_STM_BASE 0x63D1000ull
#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CS_STM_SECTION 0x1000
#define mmDCORE1_EDMA1_CS_CTI_BASE 0x63D2000ull
#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000
#define mmDCORE1_EDMA1_CS_ETF_BASE 0x63D3000ull
#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000
#define mmDCORE1_EDMA1_CS_SPMU_BASE 0x63D4000ull
#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000
#define mmDCORE1_EDMA1_BMON_CTI_BASE 0x63D5000ull
#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000
#define mmDCORE1_EDMA1_USER_CTI_BASE 0x63D6000ull
#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000
#define mmDCORE1_EDMA1_BMON_0_BASE 0x63D7000ull
#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_BMON_0_SECTION 0x1000
#define mmDCORE1_EDMA1_BMON_1_BASE 0x63D8000ull
#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_EDMA1_BMON_1_SECTION 0x1000
#define mmDCORE1_EDMA1_QM_ARC_RTT_BASE 0x63D9000ull
#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE1_VDEC0_CS_ROM_TBL_BASE 0x63E0000ull
#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_VDEC0_CS_STM_BASE 0x63E1000ull
#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CS_STM_SECTION 0x1000
#define mmDCORE1_VDEC0_CS_CTI_BASE 0x63E2000ull
#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000
#define mmDCORE1_VDEC0_CS_ETF_BASE 0x63E3000ull
#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000
#define mmDCORE1_VDEC0_CS_SPMU_BASE 0x63E4000ull
#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000
#define mmDCORE1_VDEC0_BMON_CTI_BASE 0x63E5000ull
#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000
#define mmDCORE1_VDEC0_USER_CTI_BASE 0x63E6000ull
#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000
#define mmDCORE1_VDEC0_BMON_0_BASE 0x63E7000ull
#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_BMON_0_SECTION 0x1000
#define mmDCORE1_VDEC0_BMON_1_BASE 0x63E8000ull
#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_BMON_1_SECTION 0x1000
#define mmDCORE1_VDEC0_BMON_2_BASE 0x63E9000ull
#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_VDEC0_BMON_2_SECTION 0x7000
#define mmDCORE1_VDEC1_CS_ROM_TBL_BASE 0x63F0000ull
#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE1_VDEC1_CS_STM_BASE 0x63F1000ull
#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CS_STM_SECTION 0x1000
#define mmDCORE1_VDEC1_CS_CTI_BASE 0x63F2000ull
#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000
#define mmDCORE1_VDEC1_CS_ETF_BASE 0x63F3000ull
#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000
#define mmDCORE1_VDEC1_CS_SPMU_BASE 0x63F4000ull
#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000
#define mmDCORE1_VDEC1_BMON_CTI_BASE 0x63F5000ull
#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000
#define mmDCORE1_VDEC1_USER_CTI_BASE 0x63F6000ull
#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000
#define mmDCORE1_VDEC1_BMON_0_BASE 0x63F7000ull
#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_BMON_0_SECTION 0x1000
#define mmDCORE1_VDEC1_BMON_1_BASE 0x63F8000ull
#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_BMON_1_SECTION 0x1000
#define mmDCORE1_VDEC1_BMON_2_BASE 0x63F9000ull
#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000
#define DCORE1_VDEC1_BMON_2_SECTION 0x7000
#define mmDCORE2_ROM_TABLE_L_BASE 0x6400000ull
#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000
#define DCORE2_ROM_TABLE_L_SECTION 0x80000
#define mmDCORE2_HMMU0_CS_ROM_TBL_BASE 0x6480000ull
#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_HMMU0_CS_STM_BASE 0x6481000ull
#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_CS_STM_SECTION 0x1000
#define mmDCORE2_HMMU0_CS_CTI_BASE 0x6482000ull
#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000
#define mmDCORE2_HMMU0_CS_ETF_BASE 0x6483000ull
#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000
#define mmDCORE2_HMMU0_CS_SPMU_BASE 0x6484000ull
#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_CTI_BASE 0x6485000ull
#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000
#define mmDCORE2_HMMU0_USER_CTI_BASE 0x6486000ull
#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_0_BASE 0x6487000ull
#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_0_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_1_BASE 0x6488000ull
#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_1_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_3_BASE 0x6489000ull
#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_3_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_2_BASE 0x648A000ull
#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_2_SECTION 0x1000
#define mmDCORE2_HMMU0_BMON_4_BASE 0x648B000ull
#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000
#define DCORE2_HMMU0_BMON_4_SECTION 0x5000
#define mmDCORE2_HMMU1_CS_ROM_TBL_BASE 0x6490000ull
#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_HMMU1_CS_STM_BASE 0x6491000ull
#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_CS_STM_SECTION 0x1000
#define mmDCORE2_HMMU1_CS_CTI_BASE 0x6492000ull
#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000
#define mmDCORE2_HMMU1_CS_ETF_BASE 0x6493000ull
#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000
#define mmDCORE2_HMMU1_CS_SPMU_BASE 0x6494000ull
#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_CTI_BASE 0x6495000ull
#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000
#define mmDCORE2_HMMU1_USER_CTI_BASE 0x6496000ull
#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_0_BASE 0x6497000ull
#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_0_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_1_BASE 0x6498000ull
#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_1_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_3_BASE 0x6499000ull
#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_3_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_2_BASE 0x649A000ull
#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_2_SECTION 0x1000
#define mmDCORE2_HMMU1_BMON_4_BASE 0x649B000ull
#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000
#define DCORE2_HMMU1_BMON_4_SECTION 0x5000
#define mmDCORE2_HMMU2_CS_ROM_TBL_BASE 0x64A0000ull
#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_HMMU2_CS_STM_BASE 0x64A1000ull
#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_CS_STM_SECTION 0x1000
#define mmDCORE2_HMMU2_CS_CTI_BASE 0x64A2000ull
#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000
#define mmDCORE2_HMMU2_CS_ETF_BASE 0x64A3000ull
#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000
#define mmDCORE2_HMMU2_CS_SPMU_BASE 0x64A4000ull
#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_CTI_BASE 0x64A5000ull
#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000
#define mmDCORE2_HMMU2_USER_CTI_BASE 0x64A6000ull
#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_0_BASE 0x64A7000ull
#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_0_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_1_BASE 0x64A8000ull
#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_1_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_3_BASE 0x64A9000ull
#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_3_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_2_BASE 0x64AA000ull
#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_2_SECTION 0x1000
#define mmDCORE2_HMMU2_BMON_4_BASE 0x64AB000ull
#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000
#define DCORE2_HMMU2_BMON_4_SECTION 0x5000
#define mmDCORE2_HMMU3_CS_ROM_TBL_BASE 0x64B0000ull
#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_HMMU3_CS_STM_BASE 0x64B1000ull
#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_CS_STM_SECTION 0x1000
#define mmDCORE2_HMMU3_CS_CTI_BASE 0x64B2000ull
#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000
#define mmDCORE2_HMMU3_CS_ETF_BASE 0x64B3000ull
#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000
#define mmDCORE2_HMMU3_CS_SPMU_BASE 0x64B4000ull
#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_CTI_BASE 0x64B5000ull
#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000
#define mmDCORE2_HMMU3_USER_CTI_BASE 0x64B6000ull
#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_0_BASE 0x64B7000ull
#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_0_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_1_BASE 0x64B8000ull
#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_1_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_3_BASE 0x64B9000ull
#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_3_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_2_BASE 0x64BA000ull
#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_2_SECTION 0x1000
#define mmDCORE2_HMMU3_BMON_4_BASE 0x64BB000ull
#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000
#define DCORE2_HMMU3_BMON_4_SECTION 0x5000
#define mmDCORE2_MME_CTRL_ROM_TABLE_BASE 0x64C0000ull
#define DCORE2_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_ROM_TABLE_SECTION 0x1000
#define mmDCORE2_MME_CTRL_STM_BASE 0x64C1000ull
#define DCORE2_MME_CTRL_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_STM_SECTION 0x1000
#define mmDCORE2_MME_CTRL_CTI_BASE 0x64C2000ull
#define DCORE2_MME_CTRL_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_CTI_SECTION 0x1000
#define mmDCORE2_MME_CTRL_ETF_BASE 0x64C3000ull
#define DCORE2_MME_CTRL_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_ETF_SECTION 0x1000
#define mmDCORE2_MME_CTRL_SPMU_BASE 0x64C4000ull
#define DCORE2_MME_CTRL_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_SPMU_SECTION 0x1000
#define mmDCORE2_MME_CTRL_CTI0_BASE 0x64C5000ull
#define DCORE2_MME_CTRL_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_CTI0_SECTION 0x1000
#define mmDCORE2_MME_CTRL_CTI1_BASE 0x64C6000ull
#define DCORE2_MME_CTRL_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_CTI1_SECTION 0x1000
#define mmDCORE2_MME_CTRL_BMON0_BASE 0x64C7000ull
#define DCORE2_MME_CTRL_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_BMON0_SECTION 0x1000
#define mmDCORE2_MME_CTRL_BMON1_BASE 0x64C8000ull
#define DCORE2_MME_CTRL_BMON1_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_BMON1_SECTION 0x1000
#define mmDCORE2_MME_CTRL_BMON2_BASE 0x64C9000ull
#define DCORE2_MME_CTRL_BMON2_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_BMON2_SECTION 0x1000
#define mmDCORE2_MME_CTRL_BMON3_BASE 0x64CA000ull
#define DCORE2_MME_CTRL_BMON3_MAX_OFFSET 0x1000
#define DCORE2_MME_CTRL_BMON3_SECTION 0x1000
#define mmDCORE2_MME_CTRL_ARC_RTT_BASE 0x64CB000ull
#define DCORE2_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_MME_CTRL_ARC_RTT_SECTION 0x5000
#define mmDCORE2_MME_SBTE0_ROM_TBL_BASE 0x64D0000ull
#define DCORE2_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_STM_BASE 0x64D1000ull
#define DCORE2_MME_SBTE0_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_STM_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_CTI_BASE 0x64D2000ull
#define DCORE2_MME_SBTE0_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_CTI_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_ETF_BASE 0x64D3000ull
#define DCORE2_MME_SBTE0_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_ETF_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_SPMU_BASE 0x64D4000ull
#define DCORE2_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_SPMU_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_CTI0_BASE 0x64D5000ull
#define DCORE2_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_CTI0_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_CTI1_BASE 0x64D6000ull
#define DCORE2_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_CTI1_SECTION 0x1000
#define mmDCORE2_MME_SBTE0_BMON0_BASE 0x64D7000ull
#define DCORE2_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE0_BMON0_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_ROM_TBL_BASE 0x64D8000ull
#define DCORE2_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_STM_BASE 0x64D9000ull
#define DCORE2_MME_SBTE1_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_STM_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_CTI_BASE 0x64DA000ull
#define DCORE2_MME_SBTE1_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_CTI_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_ETF_BASE 0x64DB000ull
#define DCORE2_MME_SBTE1_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_ETF_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_SPMU_BASE 0x64DC000ull
#define DCORE2_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_SPMU_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_CTI0_BASE 0x64DD000ull
#define DCORE2_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_CTI0_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_CTI1_BASE 0x64DE000ull
#define DCORE2_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_CTI1_SECTION 0x1000
#define mmDCORE2_MME_SBTE1_BMON0_BASE 0x64DF000ull
#define DCORE2_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE1_BMON0_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_ROM_TBL_BASE 0x64E0000ull
#define DCORE2_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_STM_BASE 0x64E1000ull
#define DCORE2_MME_SBTE2_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_STM_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_CTI_BASE 0x64E2000ull
#define DCORE2_MME_SBTE2_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_CTI_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_ETF_BASE 0x64E3000ull
#define DCORE2_MME_SBTE2_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_ETF_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_SPMU_BASE 0x64E4000ull
#define DCORE2_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_SPMU_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_CTI0_BASE 0x64E5000ull
#define DCORE2_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_CTI0_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_CTI1_BASE 0x64E6000ull
#define DCORE2_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_CTI1_SECTION 0x1000
#define mmDCORE2_MME_SBTE2_BMON0_BASE 0x64E7000ull
#define DCORE2_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE2_BMON0_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_ROM_TBL_BASE 0x64E8000ull
#define DCORE2_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_STM_BASE 0x64E9000ull
#define DCORE2_MME_SBTE3_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_STM_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_CTI_BASE 0x64EA000ull
#define DCORE2_MME_SBTE3_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_CTI_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_ETF_BASE 0x64EB000ull
#define DCORE2_MME_SBTE3_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_ETF_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_SPMU_BASE 0x64EC000ull
#define DCORE2_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_SPMU_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_CTI0_BASE 0x64ED000ull
#define DCORE2_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_CTI0_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_CTI1_BASE 0x64EE000ull
#define DCORE2_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_CTI1_SECTION 0x1000
#define mmDCORE2_MME_SBTE3_BMON0_BASE 0x64EF000ull
#define DCORE2_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE3_BMON0_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_ROM_TBL_BASE 0x64F0000ull
#define DCORE2_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_STM_BASE 0x64F1000ull
#define DCORE2_MME_SBTE4_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_STM_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_CTI_BASE 0x64F2000ull
#define DCORE2_MME_SBTE4_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_CTI_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_ETF_BASE 0x64F3000ull
#define DCORE2_MME_SBTE4_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_ETF_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_SPMU_BASE 0x64F4000ull
#define DCORE2_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_SPMU_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_CTI0_BASE 0x64F5000ull
#define DCORE2_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_CTI0_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_CTI1_BASE 0x64F6000ull
#define DCORE2_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_CTI1_SECTION 0x1000
#define mmDCORE2_MME_SBTE4_BMON0_BASE 0x64F7000ull
#define DCORE2_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_SBTE4_BMON0_SECTION 0x9000
#define mmDCORE2_MME_ACC_CS_ROM_TBL_BASE 0x6500000ull
#define DCORE2_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_MME_ACC_STM_BASE 0x6501000ull
#define DCORE2_MME_ACC_STM_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_STM_SECTION 0x1000
#define mmDCORE2_MME_ACC_CTI_BASE 0x6502000ull
#define DCORE2_MME_ACC_CTI_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_CTI_SECTION 0x1000
#define mmDCORE2_MME_ACC_ETF_BASE 0x6503000ull
#define DCORE2_MME_ACC_ETF_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_ETF_SECTION 0x1000
#define mmDCORE2_MME_ACC_SPMU_BASE 0x6504000ull
#define DCORE2_MME_ACC_SPMU_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_SPMU_SECTION 0x1000
#define mmDCORE2_MME_ACC_CTI0_BASE 0x6505000ull
#define DCORE2_MME_ACC_CTI0_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_CTI0_SECTION 0x1000
#define mmDCORE2_MME_ACC_CTI1_BASE 0x6506000ull
#define DCORE2_MME_ACC_CTI1_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_CTI1_SECTION 0x1000
#define mmDCORE2_MME_ACC_BMON0_BASE 0x6507000ull
#define DCORE2_MME_ACC_BMON0_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_BMON0_SECTION 0x1000
#define mmDCORE2_MME_ACC_BMON1_BASE 0x6508000ull
#define DCORE2_MME_ACC_BMON1_MAX_OFFSET 0x1000
#define DCORE2_MME_ACC_BMON1_SECTION 0x8000
#define mmDCORE2_SM_CS_DBG_ROM_TBL_BASE 0x6510000ull
#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmDCORE2_SM_STM_BASE 0x6511000ull
#define DCORE2_SM_STM_MAX_OFFSET 0x1000
#define DCORE2_SM_STM_SECTION 0x1000
#define mmDCORE2_SM_CTI_BASE 0x6512000ull
#define DCORE2_SM_CTI_MAX_OFFSET 0x1000
#define DCORE2_SM_CTI_SECTION 0x1000
#define mmDCORE2_SM_ETF_BASE 0x6513000ull
#define DCORE2_SM_ETF_MAX_OFFSET 0x1000
#define DCORE2_SM_ETF_SECTION 0x1000
#define mmDCORE2_SM_SPMU_BASE 0x6514000ull
#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000
#define DCORE2_SM_SPMU_SECTION 0x1000
#define mmDCORE2_SM_BMON_CTI_BASE 0x6515000ull
#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_SM_BMON_CTI_SECTION 0x1000
#define mmDCORE2_SM_USER_CTI_BASE 0x6516000ull
#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_SM_USER_CTI_SECTION 0x1000
#define mmDCORE2_SM_BMON_BASE 0x6517000ull
#define DCORE2_SM_BMON_MAX_OFFSET 0x1000
#define DCORE2_SM_BMON_SECTION 0x1000
#define mmDCORE2_SM_BMON1_BASE 0x6518000ull
#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000
#define DCORE2_SM_BMON1_SECTION 0x18000
#define mmDCORE2_XFT_FUNNEL_BASE 0x6530000ull
#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_XFT_FUNNEL_SECTION 0x8000
#define mmDCORE2_TFT0_FUNNEL_BASE 0x6538000ull
#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TFT0_FUNNEL_SECTION 0x1000
#define mmDCORE2_TFT1_FUNNEL_BASE 0x6539000ull
#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TFT1_FUNNEL_SECTION 0x1000
#define mmDCORE2_TFT2_FUNNEL_BASE 0x653A000ull
#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_TFT2_FUNNEL_SECTION 0x7000
#define mmDCORE2_RTR0_FUNNEL_BASE 0x6541000ull
#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR0_FUNNEL_SECTION 0x8000
#define mmDCORE2_RTR1_FUNNEL_BASE 0x6549000ull
#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR1_FUNNEL_SECTION 0x8000
#define mmDCORE2_RTR2_FUNNEL_BASE 0x6551000ull
#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR2_FUNNEL_SECTION 0x8000
#define mmDCORE2_RTR3_FUNNEL_BASE 0x6559000ull
#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR3_FUNNEL_SECTION 0x8000
#define mmDCORE2_RTR4_FUNNEL_BASE 0x6561000ull
#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR4_FUNNEL_SECTION 0x4000
#define mmDCORE2_MIF0_FUNNEL_BASE 0x6565000ull
#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_MIF0_FUNNEL_SECTION 0x4000
#define mmDCORE2_RTR5_FUNNEL_BASE 0x6569000ull
#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR5_FUNNEL_SECTION 0x4000
#define mmDCORE2_MIF1_FUNNEL_BASE 0x656D000ull
#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_MIF1_FUNNEL_SECTION 0x4000
#define mmDCORE2_RTR6_FUNNEL_BASE 0x6571000ull
#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR6_FUNNEL_SECTION 0x4000
#define mmDCORE2_MIF2_FUNNEL_BASE 0x6575000ull
#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_MIF2_FUNNEL_SECTION 0x4000
#define mmDCORE2_RTR7_FUNNEL_BASE 0x6579000ull
#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_RTR7_FUNNEL_SECTION 0x4000
#define mmDCORE2_MIF3_FUNNEL_BASE 0x657D000ull
#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_MIF3_FUNNEL_SECTION 0x43000
#define mmDCORE2_EDMA0_CS_ROM_TBL_BASE 0x65C0000ull
#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_EDMA0_CS_STM_BASE 0x65C1000ull
#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CS_STM_SECTION 0x1000
#define mmDCORE2_EDMA0_CS_CTI_BASE 0x65C2000ull
#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000
#define mmDCORE2_EDMA0_CS_ETF_BASE 0x65C3000ull
#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000
#define mmDCORE2_EDMA0_CS_SPMU_BASE 0x65C4000ull
#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000
#define mmDCORE2_EDMA0_BMON_CTI_BASE 0x65C5000ull
#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000
#define mmDCORE2_EDMA0_USER_CTI_BASE 0x65C6000ull
#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000
#define mmDCORE2_EDMA0_BMON_0_BASE 0x65C7000ull
#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_BMON_0_SECTION 0x1000
#define mmDCORE2_EDMA0_BMON_1_BASE 0x65C8000ull
#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_EDMA0_BMON_1_SECTION 0x1000
#define mmDCORE2_EDMA0_QM_ARC_RTT_BASE 0x65C9000ull
#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE2_EDMA1_CS_ROM_TBL_BASE 0x65D0000ull
#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_EDMA1_CS_STM_BASE 0x65D1000ull
#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CS_STM_SECTION 0x1000
#define mmDCORE2_EDMA1_CS_CTI_BASE 0x65D2000ull
#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000
#define mmDCORE2_EDMA1_CS_ETF_BASE 0x65D3000ull
#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000
#define mmDCORE2_EDMA1_CS_SPMU_BASE 0x65D4000ull
#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000
#define mmDCORE2_EDMA1_BMON_CTI_BASE 0x65D5000ull
#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000
#define mmDCORE2_EDMA1_USER_CTI_BASE 0x65D6000ull
#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000
#define mmDCORE2_EDMA1_BMON_0_BASE 0x65D7000ull
#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_BMON_0_SECTION 0x1000
#define mmDCORE2_EDMA1_BMON_1_BASE 0x65D8000ull
#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_EDMA1_BMON_1_SECTION 0x1000
#define mmDCORE2_EDMA1_QM_ARC_RTT_BASE 0x65D9000ull
#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE2_VDEC0_CS_ROM_TBL_BASE 0x65E0000ull
#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_VDEC0_CS_STM_BASE 0x65E1000ull
#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CS_STM_SECTION 0x1000
#define mmDCORE2_VDEC0_CS_CTI_BASE 0x65E2000ull
#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000
#define mmDCORE2_VDEC0_CS_ETF_BASE 0x65E3000ull
#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000
#define mmDCORE2_VDEC0_CS_SPMU_BASE 0x65E4000ull
#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000
#define mmDCORE2_VDEC0_BMON_CTI_BASE 0x65E5000ull
#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000
#define mmDCORE2_VDEC0_USER_CTI_BASE 0x65E6000ull
#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000
#define mmDCORE2_VDEC0_BMON_0_BASE 0x65E7000ull
#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_BMON_0_SECTION 0x1000
#define mmDCORE2_VDEC0_BMON_1_BASE 0x65E8000ull
#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_BMON_1_SECTION 0x1000
#define mmDCORE2_VDEC0_BMON_2_BASE 0x65E9000ull
#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_VDEC0_BMON_2_SECTION 0x7000
#define mmDCORE2_VDEC1_CS_ROM_TBL_BASE 0x65F0000ull
#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE2_VDEC1_CS_STM_BASE 0x65F1000ull
#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CS_STM_SECTION 0x1000
#define mmDCORE2_VDEC1_CS_CTI_BASE 0x65F2000ull
#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000
#define mmDCORE2_VDEC1_CS_ETF_BASE 0x65F3000ull
#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000
#define mmDCORE2_VDEC1_CS_SPMU_BASE 0x65F4000ull
#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000
#define mmDCORE2_VDEC1_BMON_CTI_BASE 0x65F5000ull
#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000
#define mmDCORE2_VDEC1_USER_CTI_BASE 0x65F6000ull
#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000
#define mmDCORE2_VDEC1_BMON_0_BASE 0x65F7000ull
#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_BMON_0_SECTION 0x1000
#define mmDCORE2_VDEC1_BMON_1_BASE 0x65F8000ull
#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_BMON_1_SECTION 0x1000
#define mmDCORE2_VDEC1_BMON_2_BASE 0x65F9000ull
#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000
#define DCORE2_VDEC1_BMON_2_SECTION 0x7000
#define mmDCORE3_ROM_TABLE_L_BASE 0x6600000ull
#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000
#define DCORE3_ROM_TABLE_L_SECTION 0x80000
#define mmDCORE3_HMMU0_CS_ROM_TBL_BASE 0x6680000ull
#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_HMMU0_CS_STM_BASE 0x6681000ull
#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_CS_STM_SECTION 0x1000
#define mmDCORE3_HMMU0_CS_CTI_BASE 0x6682000ull
#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000
#define mmDCORE3_HMMU0_CS_ETF_BASE 0x6683000ull
#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000
#define mmDCORE3_HMMU0_CS_SPMU_BASE 0x6684000ull
#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_CTI_BASE 0x6685000ull
#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000
#define mmDCORE3_HMMU0_USER_CTI_BASE 0x6686000ull
#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_0_BASE 0x6687000ull
#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_0_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_1_BASE 0x6688000ull
#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_1_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_3_BASE 0x6689000ull
#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_3_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_2_BASE 0x668A000ull
#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_2_SECTION 0x1000
#define mmDCORE3_HMMU0_BMON_4_BASE 0x668B000ull
#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000
#define DCORE3_HMMU0_BMON_4_SECTION 0x5000
#define mmDCORE3_HMMU1_CS_ROM_TBL_BASE 0x6690000ull
#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_HMMU1_CS_STM_BASE 0x6691000ull
#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_CS_STM_SECTION 0x1000
#define mmDCORE3_HMMU1_CS_CTI_BASE 0x6692000ull
#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000
#define mmDCORE3_HMMU1_CS_ETF_BASE 0x6693000ull
#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000
#define mmDCORE3_HMMU1_CS_SPMU_BASE 0x6694000ull
#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_CTI_BASE 0x6695000ull
#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000
#define mmDCORE3_HMMU1_USER_CTI_BASE 0x6696000ull
#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_0_BASE 0x6697000ull
#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_0_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_1_BASE 0x6698000ull
#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_1_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_3_BASE 0x6699000ull
#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_3_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_2_BASE 0x669A000ull
#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_2_SECTION 0x1000
#define mmDCORE3_HMMU1_BMON_4_BASE 0x669B000ull
#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000
#define DCORE3_HMMU1_BMON_4_SECTION 0x5000
#define mmDCORE3_HMMU2_CS_ROM_TBL_BASE 0x66A0000ull
#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_HMMU2_CS_STM_BASE 0x66A1000ull
#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_CS_STM_SECTION 0x1000
#define mmDCORE3_HMMU2_CS_CTI_BASE 0x66A2000ull
#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000
#define mmDCORE3_HMMU2_CS_ETF_BASE 0x66A3000ull
#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000
#define mmDCORE3_HMMU2_CS_SPMU_BASE 0x66A4000ull
#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_CTI_BASE 0x66A5000ull
#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000
#define mmDCORE3_HMMU2_USER_CTI_BASE 0x66A6000ull
#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_0_BASE 0x66A7000ull
#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_0_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_1_BASE 0x66A8000ull
#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_1_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_3_BASE 0x66A9000ull
#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_3_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_2_BASE 0x66AA000ull
#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_2_SECTION 0x1000
#define mmDCORE3_HMMU2_BMON_4_BASE 0x66AB000ull
#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000
#define DCORE3_HMMU2_BMON_4_SECTION 0x5000
#define mmDCORE3_HMMU3_CS_ROM_TBL_BASE 0x66B0000ull
#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_HMMU3_CS_STM_BASE 0x66B1000ull
#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_CS_STM_SECTION 0x1000
#define mmDCORE3_HMMU3_CS_CTI_BASE 0x66B2000ull
#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000
#define mmDCORE3_HMMU3_CS_ETF_BASE 0x66B3000ull
#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000
#define mmDCORE3_HMMU3_CS_SPMU_BASE 0x66B4000ull
#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_CTI_BASE 0x66B5000ull
#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000
#define mmDCORE3_HMMU3_USER_CTI_BASE 0x66B6000ull
#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_0_BASE 0x66B7000ull
#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_0_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_1_BASE 0x66B8000ull
#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_1_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_3_BASE 0x66B9000ull
#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_3_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_2_BASE 0x66BA000ull
#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_2_SECTION 0x1000
#define mmDCORE3_HMMU3_BMON_4_BASE 0x66BB000ull
#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000
#define DCORE3_HMMU3_BMON_4_SECTION 0x5000
#define mmDCORE3_MME_CTRL_ROM_TABLE_BASE 0x66C0000ull
#define DCORE3_MME_CTRL_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_ROM_TABLE_SECTION 0x1000
#define mmDCORE3_MME_CTRL_STM_BASE 0x66C1000ull
#define DCORE3_MME_CTRL_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_STM_SECTION 0x1000
#define mmDCORE3_MME_CTRL_CTI_BASE 0x66C2000ull
#define DCORE3_MME_CTRL_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_CTI_SECTION 0x1000
#define mmDCORE3_MME_CTRL_ETF_BASE 0x66C3000ull
#define DCORE3_MME_CTRL_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_ETF_SECTION 0x1000
#define mmDCORE3_MME_CTRL_SPMU_BASE 0x66C4000ull
#define DCORE3_MME_CTRL_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_SPMU_SECTION 0x1000
#define mmDCORE3_MME_CTRL_CTI0_BASE 0x66C5000ull
#define DCORE3_MME_CTRL_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_CTI0_SECTION 0x1000
#define mmDCORE3_MME_CTRL_CTI1_BASE 0x66C6000ull
#define DCORE3_MME_CTRL_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_CTI1_SECTION 0x1000
#define mmDCORE3_MME_CTRL_BMON0_BASE 0x66C7000ull
#define DCORE3_MME_CTRL_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_BMON0_SECTION 0x1000
#define mmDCORE3_MME_CTRL_BMON1_BASE 0x66C8000ull
#define DCORE3_MME_CTRL_BMON1_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_BMON1_SECTION 0x1000
#define mmDCORE3_MME_CTRL_BMON2_BASE 0x66C9000ull
#define DCORE3_MME_CTRL_BMON2_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_BMON2_SECTION 0x1000
#define mmDCORE3_MME_CTRL_BMON3_BASE 0x66CA000ull
#define DCORE3_MME_CTRL_BMON3_MAX_OFFSET 0x1000
#define DCORE3_MME_CTRL_BMON3_SECTION 0x1000
#define mmDCORE3_MME_CTRL_ARC_RTT_BASE 0x66CB000ull
#define DCORE3_MME_CTRL_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_MME_CTRL_ARC_RTT_SECTION 0x5000
#define mmDCORE3_MME_SBTE0_ROM_TBL_BASE 0x66D0000ull
#define DCORE3_MME_SBTE0_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_STM_BASE 0x66D1000ull
#define DCORE3_MME_SBTE0_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_STM_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_CTI_BASE 0x66D2000ull
#define DCORE3_MME_SBTE0_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_CTI_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_ETF_BASE 0x66D3000ull
#define DCORE3_MME_SBTE0_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_ETF_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_SPMU_BASE 0x66D4000ull
#define DCORE3_MME_SBTE0_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_SPMU_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_CTI0_BASE 0x66D5000ull
#define DCORE3_MME_SBTE0_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_CTI0_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_CTI1_BASE 0x66D6000ull
#define DCORE3_MME_SBTE0_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_CTI1_SECTION 0x1000
#define mmDCORE3_MME_SBTE0_BMON0_BASE 0x66D7000ull
#define DCORE3_MME_SBTE0_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE0_BMON0_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_ROM_TBL_BASE 0x66D8000ull
#define DCORE3_MME_SBTE1_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_STM_BASE 0x66D9000ull
#define DCORE3_MME_SBTE1_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_STM_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_CTI_BASE 0x66DA000ull
#define DCORE3_MME_SBTE1_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_CTI_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_ETF_BASE 0x66DB000ull
#define DCORE3_MME_SBTE1_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_ETF_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_SPMU_BASE 0x66DC000ull
#define DCORE3_MME_SBTE1_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_SPMU_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_CTI0_BASE 0x66DD000ull
#define DCORE3_MME_SBTE1_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_CTI0_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_CTI1_BASE 0x66DE000ull
#define DCORE3_MME_SBTE1_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_CTI1_SECTION 0x1000
#define mmDCORE3_MME_SBTE1_BMON0_BASE 0x66DF000ull
#define DCORE3_MME_SBTE1_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE1_BMON0_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_ROM_TBL_BASE 0x66E0000ull
#define DCORE3_MME_SBTE2_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_STM_BASE 0x66E1000ull
#define DCORE3_MME_SBTE2_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_STM_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_CTI_BASE 0x66E2000ull
#define DCORE3_MME_SBTE2_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_CTI_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_ETF_BASE 0x66E3000ull
#define DCORE3_MME_SBTE2_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_ETF_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_SPMU_BASE 0x66E4000ull
#define DCORE3_MME_SBTE2_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_SPMU_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_CTI0_BASE 0x66E5000ull
#define DCORE3_MME_SBTE2_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_CTI0_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_CTI1_BASE 0x66E6000ull
#define DCORE3_MME_SBTE2_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_CTI1_SECTION 0x1000
#define mmDCORE3_MME_SBTE2_BMON0_BASE 0x66E7000ull
#define DCORE3_MME_SBTE2_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE2_BMON0_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_ROM_TBL_BASE 0x66E8000ull
#define DCORE3_MME_SBTE3_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_STM_BASE 0x66E9000ull
#define DCORE3_MME_SBTE3_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_STM_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_CTI_BASE 0x66EA000ull
#define DCORE3_MME_SBTE3_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_CTI_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_ETF_BASE 0x66EB000ull
#define DCORE3_MME_SBTE3_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_ETF_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_SPMU_BASE 0x66EC000ull
#define DCORE3_MME_SBTE3_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_SPMU_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_CTI0_BASE 0x66ED000ull
#define DCORE3_MME_SBTE3_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_CTI0_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_CTI1_BASE 0x66EE000ull
#define DCORE3_MME_SBTE3_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_CTI1_SECTION 0x1000
#define mmDCORE3_MME_SBTE3_BMON0_BASE 0x66EF000ull
#define DCORE3_MME_SBTE3_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE3_BMON0_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_ROM_TBL_BASE 0x66F0000ull
#define DCORE3_MME_SBTE4_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_STM_BASE 0x66F1000ull
#define DCORE3_MME_SBTE4_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_STM_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_CTI_BASE 0x66F2000ull
#define DCORE3_MME_SBTE4_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_CTI_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_ETF_BASE 0x66F3000ull
#define DCORE3_MME_SBTE4_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_ETF_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_SPMU_BASE 0x66F4000ull
#define DCORE3_MME_SBTE4_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_SPMU_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_CTI0_BASE 0x66F5000ull
#define DCORE3_MME_SBTE4_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_CTI0_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_CTI1_BASE 0x66F6000ull
#define DCORE3_MME_SBTE4_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_CTI1_SECTION 0x1000
#define mmDCORE3_MME_SBTE4_BMON0_BASE 0x66F7000ull
#define DCORE3_MME_SBTE4_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_SBTE4_BMON0_SECTION 0x9000
#define mmDCORE3_MME_ACC_CS_ROM_TBL_BASE 0x6700000ull
#define DCORE3_MME_ACC_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_MME_ACC_STM_BASE 0x6701000ull
#define DCORE3_MME_ACC_STM_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_STM_SECTION 0x1000
#define mmDCORE3_MME_ACC_CTI_BASE 0x6702000ull
#define DCORE3_MME_ACC_CTI_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_CTI_SECTION 0x1000
#define mmDCORE3_MME_ACC_ETF_BASE 0x6703000ull
#define DCORE3_MME_ACC_ETF_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_ETF_SECTION 0x1000
#define mmDCORE3_MME_ACC_SPMU_BASE 0x6704000ull
#define DCORE3_MME_ACC_SPMU_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_SPMU_SECTION 0x1000
#define mmDCORE3_MME_ACC_CTI0_BASE 0x6705000ull
#define DCORE3_MME_ACC_CTI0_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_CTI0_SECTION 0x1000
#define mmDCORE3_MME_ACC_CTI1_BASE 0x6706000ull
#define DCORE3_MME_ACC_CTI1_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_CTI1_SECTION 0x1000
#define mmDCORE3_MME_ACC_BMON0_BASE 0x6707000ull
#define DCORE3_MME_ACC_BMON0_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_BMON0_SECTION 0x1000
#define mmDCORE3_MME_ACC_BMON1_BASE 0x6708000ull
#define DCORE3_MME_ACC_BMON1_MAX_OFFSET 0x1000
#define DCORE3_MME_ACC_BMON1_SECTION 0x8000
#define mmDCORE3_SM_CS_DBG_ROM_TBL_BASE 0x6710000ull
#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmDCORE3_SM_STM_BASE 0x6711000ull
#define DCORE3_SM_STM_MAX_OFFSET 0x1000
#define DCORE3_SM_STM_SECTION 0x1000
#define mmDCORE3_SM_CTI_BASE 0x6712000ull
#define DCORE3_SM_CTI_MAX_OFFSET 0x1000
#define DCORE3_SM_CTI_SECTION 0x1000
#define mmDCORE3_SM_ETF_BASE 0x6713000ull
#define DCORE3_SM_ETF_MAX_OFFSET 0x1000
#define DCORE3_SM_ETF_SECTION 0x1000
#define mmDCORE3_SM_SPMU_BASE 0x6714000ull
#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000
#define DCORE3_SM_SPMU_SECTION 0x1000
#define mmDCORE3_SM_BMON_CTI_BASE 0x6715000ull
#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_SM_BMON_CTI_SECTION 0x1000
#define mmDCORE3_SM_USER_CTI_BASE 0x6716000ull
#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_SM_USER_CTI_SECTION 0x1000
#define mmDCORE3_SM_BMON_BASE 0x6717000ull
#define DCORE3_SM_BMON_MAX_OFFSET 0x1000
#define DCORE3_SM_BMON_SECTION 0x1000
#define mmDCORE3_SM_BMON1_BASE 0x6718000ull
#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000
#define DCORE3_SM_BMON1_SECTION 0x18000
#define mmDCORE3_XFT_FUNNEL_BASE 0x6730000ull
#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_XFT_FUNNEL_SECTION 0x8000
#define mmDCORE3_TFT0_FUNNEL_BASE 0x6738000ull
#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TFT0_FUNNEL_SECTION 0x1000
#define mmDCORE3_TFT1_FUNNEL_BASE 0x6739000ull
#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TFT1_FUNNEL_SECTION 0x1000
#define mmDCORE3_TFT2_FUNNEL_BASE 0x673A000ull
#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_TFT2_FUNNEL_SECTION 0x7000
#define mmDCORE3_RTR0_FUNNEL_BASE 0x6741000ull
#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR0_FUNNEL_SECTION 0x4000
#define mmDCORE3_MIF0_FUNNEL_BASE 0x6745000ull
#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_MIF0_FUNNEL_SECTION 0x4000
#define mmDCORE3_RTR1_FUNNEL_BASE 0x6749000ull
#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR1_FUNNEL_SECTION 0x4000
#define mmDCORE3_MIF1_FUNNEL_BASE 0x674D000ull
#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_MIF1_FUNNEL_SECTION 0x4000
#define mmDCORE3_RTR2_FUNNEL_BASE 0x6751000ull
#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR2_FUNNEL_SECTION 0x4000
#define mmDCORE3_MIF2_FUNNEL_BASE 0x6755000ull
#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_MIF2_FUNNEL_SECTION 0x4000
#define mmDCORE3_RTR3_FUNNEL_BASE 0x6759000ull
#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR3_FUNNEL_SECTION 0x4000
#define mmDCORE3_MIF3_FUNNEL_BASE 0x675D000ull
#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_MIF3_FUNNEL_SECTION 0x4000
#define mmDCORE3_RTR4_FUNNEL_BASE 0x6761000ull
#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR4_FUNNEL_SECTION 0x8000
#define mmDCORE3_RTR5_FUNNEL_BASE 0x6769000ull
#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR5_FUNNEL_SECTION 0x8000
#define mmDCORE3_RTR6_FUNNEL_BASE 0x6771000ull
#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR6_FUNNEL_SECTION 0x8000
#define mmDCORE3_RTR7_FUNNEL_BASE 0x6779000ull
#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_RTR7_FUNNEL_SECTION 0x47000
#define mmDCORE3_EDMA0_CS_ROM_TBL_BASE 0x67C0000ull
#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_EDMA0_CS_STM_BASE 0x67C1000ull
#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CS_STM_SECTION 0x1000
#define mmDCORE3_EDMA0_CS_CTI_BASE 0x67C2000ull
#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000
#define mmDCORE3_EDMA0_CS_ETF_BASE 0x67C3000ull
#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000
#define mmDCORE3_EDMA0_CS_SPMU_BASE 0x67C4000ull
#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000
#define mmDCORE3_EDMA0_BMON_CTI_BASE 0x67C5000ull
#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000
#define mmDCORE3_EDMA0_USER_CTI_BASE 0x67C6000ull
#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000
#define mmDCORE3_EDMA0_BMON_0_BASE 0x67C7000ull
#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_BMON_0_SECTION 0x1000
#define mmDCORE3_EDMA0_BMON_1_BASE 0x67C8000ull
#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_EDMA0_BMON_1_SECTION 0x1000
#define mmDCORE3_EDMA0_QM_ARC_RTT_BASE 0x67C9000ull
#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE3_EDMA1_CS_ROM_TBL_BASE 0x67D0000ull
#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_EDMA1_CS_STM_BASE 0x67D1000ull
#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CS_STM_SECTION 0x1000
#define mmDCORE3_EDMA1_CS_CTI_BASE 0x67D2000ull
#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000
#define mmDCORE3_EDMA1_CS_ETF_BASE 0x67D3000ull
#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000
#define mmDCORE3_EDMA1_CS_SPMU_BASE 0x67D4000ull
#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000
#define mmDCORE3_EDMA1_BMON_CTI_BASE 0x67D5000ull
#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000
#define mmDCORE3_EDMA1_USER_CTI_BASE 0x67D6000ull
#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000
#define mmDCORE3_EDMA1_BMON_0_BASE 0x67D7000ull
#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_BMON_0_SECTION 0x1000
#define mmDCORE3_EDMA1_BMON_1_BASE 0x67D8000ull
#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_EDMA1_BMON_1_SECTION 0x1000
#define mmDCORE3_EDMA1_QM_ARC_RTT_BASE 0x67D9000ull
#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000
#define mmDCORE3_VDEC0_CS_ROM_TBL_BASE 0x67E0000ull
#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_VDEC0_CS_STM_BASE 0x67E1000ull
#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CS_STM_SECTION 0x1000
#define mmDCORE3_VDEC0_CS_CTI_BASE 0x67E2000ull
#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000
#define mmDCORE3_VDEC0_CS_ETF_BASE 0x67E3000ull
#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000
#define mmDCORE3_VDEC0_CS_SPMU_BASE 0x67E4000ull
#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000
#define mmDCORE3_VDEC0_BMON_CTI_BASE 0x67E5000ull
#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000
#define mmDCORE3_VDEC0_USER_CTI_BASE 0x67E6000ull
#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000
#define mmDCORE3_VDEC0_BMON_0_BASE 0x67E7000ull
#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_BMON_0_SECTION 0x1000
#define mmDCORE3_VDEC0_BMON_1_BASE 0x67E8000ull
#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_BMON_1_SECTION 0x1000
#define mmDCORE3_VDEC0_BMON_2_BASE 0x67E9000ull
#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_VDEC0_BMON_2_SECTION 0x7000
#define mmDCORE3_VDEC1_CS_ROM_TBL_BASE 0x67F0000ull
#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000
#define mmDCORE3_VDEC1_CS_STM_BASE 0x67F1000ull
#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CS_STM_SECTION 0x1000
#define mmDCORE3_VDEC1_CS_CTI_BASE 0x67F2000ull
#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000
#define mmDCORE3_VDEC1_CS_ETF_BASE 0x67F3000ull
#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000
#define mmDCORE3_VDEC1_CS_SPMU_BASE 0x67F4000ull
#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000
#define mmDCORE3_VDEC1_BMON_CTI_BASE 0x67F5000ull
#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000
#define mmDCORE3_VDEC1_USER_CTI_BASE 0x67F6000ull
#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000
#define mmDCORE3_VDEC1_BMON_0_BASE 0x67F7000ull
#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_BMON_0_SECTION 0x1000
#define mmDCORE3_VDEC1_BMON_1_BASE 0x67F8000ull
#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_BMON_1_SECTION 0x1000
#define mmDCORE3_VDEC1_BMON_2_BASE 0x67F9000ull
#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000
#define DCORE3_VDEC1_BMON_2_SECTION 0x7000
#define mmCA53_BASE 0x6800000ull
#define CA53_MAX_OFFSET 0x141000
#define CA53_SECTION 0x400000
#define mmPCI_ROM_TABLE_BASE 0x6C00000ull
#define PCI_ROM_TABLE_MAX_OFFSET 0x1000
#define PCI_ROM_TABLE_SECTION 0x1000
#define mmPCIE_STM_BASE 0x6C01000ull
#define PCIE_STM_MAX_OFFSET 0x1000
#define PCIE_STM_SECTION 0x1000
#define mmPCIE_ETF_BASE 0x6C02000ull
#define PCIE_ETF_MAX_OFFSET 0x1000
#define PCIE_ETF_SECTION 0x1000
#define mmPCIE_CTI_0_BASE 0x6C03000ull
#define PCIE_CTI_0_MAX_OFFSET 0x1000
#define PCIE_CTI_0_SECTION 0x1000
#define mmPCIE_SPMU_BASE 0x6C04000ull
#define PCIE_SPMU_MAX_OFFSET 0x1000
#define PCIE_SPMU_SECTION 0x1000
#define mmPCIE_CTI_1_BASE 0x6C05000ull
#define PCIE_CTI_1_MAX_OFFSET 0x1000
#define PCIE_CTI_1_SECTION 0x2000
#define mmPCIE_BMON_MSTR_WR_BASE 0x6C07000ull
#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000
#define PCIE_BMON_MSTR_WR_SECTION 0x1000
#define mmPCIE_BMON_MSTR_RD_BASE 0x6C08000ull
#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000
#define PCIE_BMON_MSTR_RD_SECTION 0x1000
#define mmPCIE_BMON_SLV_WR_BASE 0x6C09000ull
#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000
#define PCIE_BMON_SLV_WR_SECTION 0x1000
#define mmPCIE_BMON_SLV_RD_BASE 0x6C0A000ull
#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000
#define PCIE_BMON_SLV_RD_SECTION 0x36000
#define mmTOP_ROM_TABLE_BASE 0x6C40000ull
#define TOP_ROM_TABLE_MAX_OFFSET 0x1000
#define TOP_ROM_TABLE_SECTION 0x1000
#define mmPSOC_CTI_BASE 0x6C41000ull
#define PSOC_CTI_MAX_OFFSET 0x1000
#define PSOC_CTI_SECTION 0x1000
#define mmPSOC_STM_BASE 0x6C42000ull
#define PSOC_STM_MAX_OFFSET 0x1000
#define PSOC_STM_SECTION 0x1000
#define mmPSOC_FUNNEL_BASE 0x6C43000ull
#define PSOC_FUNNEL_MAX_OFFSET 0x1000
#define PSOC_FUNNEL_SECTION 0x1000
#define mmPSOC_ETR_BASE 0x6C44000ull
#define PSOC_ETR_MAX_OFFSET 0x1000
#define PSOC_ETR_SECTION 0x1000
#define mmPSOC_ETF_BASE 0x6C45000ull
#define PSOC_ETF_MAX_OFFSET 0x1000
#define PSOC_ETF_SECTION 0x1000
#define mmPSOC_TS_CTI_BASE 0x6C46000ull
#define PSOC_TS_CTI_MAX_OFFSET 0x1000
#define PSOC_TS_CTI_SECTION 0xA000
#define mmPSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x6C50000ull
#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmPSOC_ARC0_CS_STM_BASE 0x6C51000ull
#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000
#define PSOC_ARC0_CS_STM_SECTION 0x1000
#define mmPSOC_ARC0_CS_CTI_BASE 0x6C52000ull
#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC0_CS_CTI_SECTION 0x1000
#define mmPSOC_ARC0_CS_ETF_BASE 0x6C53000ull
#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000
#define PSOC_ARC0_CS_ETF_SECTION 0x1000
#define mmPSOC_ARC0_CS_SPMU_BASE 0x6C54000ull
#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000
#define PSOC_ARC0_CS_SPMU_SECTION 0x1000
#define mmPSOC_ARC0_BMON_CTI_BASE 0x6C55000ull
#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC0_BMON_CTI_SECTION 0x1000
#define mmPSOC_ARC0_USER_CTI_BASE 0x6C56000ull
#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC0_USER_CTI_SECTION 0x1000
#define mmPSOC_ARC0_BMON_0_BASE 0x6C57000ull
#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000
#define PSOC_ARC0_BMON_0_SECTION 0x1000
#define mmPSOC_ARC0_BMON_1_BASE 0x6C58000ull
#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000
#define PSOC_ARC0_BMON_1_SECTION 0x6000
#define mmPSOC_ARC0_RTT_BASE 0x6C5E000ull
#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400
#define PSOC_ARC0_RTT_SECTION 0x1000
#define mmPSOC_ARC0_FUNNEL_BASE 0x6C5F000ull
#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000
#define PSOC_ARC0_FUNNEL_SECTION 0x1000
#define mmPSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x6C60000ull
#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmPSOC_ARC1_CS_STM_BASE 0x6C61000ull
#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000
#define PSOC_ARC1_CS_STM_SECTION 0x1000
#define mmPSOC_ARC1_CS_CTI_BASE 0x6C62000ull
#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC1_CS_CTI_SECTION 0x1000
#define mmPSOC_ARC1_CS_ETF_BASE 0x6C63000ull
#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000
#define PSOC_ARC1_CS_ETF_SECTION 0x1000
#define mmPSOC_ARC1_CS_SPMU_BASE 0x6C64000ull
#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000
#define PSOC_ARC1_CS_SPMU_SECTION 0x1000
#define mmPSOC_ARC1_BMON_CTI_BASE 0x6C65000ull
#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC1_BMON_CTI_SECTION 0x1000
#define mmPSOC_ARC1_USER_CTI_BASE 0x6C66000ull
#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000
#define PSOC_ARC1_USER_CTI_SECTION 0x1000
#define mmPSOC_ARC1_BMON_0_BASE 0x6C67000ull
#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000
#define PSOC_ARC1_BMON_0_SECTION 0x1000
#define mmPSOC_ARC1_BMON_1_BASE 0x6C68000ull
#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000
#define PSOC_ARC1_BMON_1_SECTION 0x6000
#define mmPSOC_ARC1_RTT_BASE 0x6C6E000ull
#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400
#define PSOC_ARC1_RTT_SECTION 0x1000
#define mmPSOC_ARC1_FUNNEL_BASE 0x6C6F000ull
#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000
#define PSOC_ARC1_FUNNEL_SECTION 0x1000
#define mmPSOC_ARC0_CTI0_BASE 0x6C70000ull
#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000
#define PSOC_ARC0_CTI0_SECTION 0x1000
#define mmPSOC_ARC0_CTI1_BASE 0x6C71000ull
#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000
#define PSOC_ARC0_CTI1_SECTION 0x1000
#define mmPSOC_ARC0_CTI2_BASE 0x6C72000ull
#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000
#define PSOC_ARC0_CTI2_SECTION 0x1000
#define mmPSOC_ARC0_CTI3_BASE 0x6C73000ull
#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000
#define PSOC_ARC0_CTI3_SECTION 0x1000
#define mmPSOC_ARC1_CTI0_BASE 0x6C74000ull
#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000
#define PSOC_ARC1_CTI0_SECTION 0x1000
#define mmPSOC_ARC1_CTI1_BASE 0x6C75000ull
#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000
#define PSOC_ARC1_CTI1_SECTION 0x1000
#define mmPSOC_ARC1_CTI2_BASE 0x6C76000ull
#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000
#define PSOC_ARC1_CTI2_SECTION 0x1000
#define mmPSOC_ARC1_CTI3_BASE 0x6C77000ull
#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000
#define PSOC_ARC1_CTI3_SECTION 0x9000
#define mmPDMA0_CS_ROM_TBL_BASE 0x6C80000ull
#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define PDMA0_CS_ROM_TBL_SECTION 0x1000
#define mmPDMA0_CS_STM_BASE 0x6C81000ull
#define PDMA0_CS_STM_MAX_OFFSET 0x1000
#define PDMA0_CS_STM_SECTION 0x1000
#define mmPDMA0_CS_CTI_BASE 0x6C82000ull
#define PDMA0_CS_CTI_MAX_OFFSET 0x1000
#define PDMA0_CS_CTI_SECTION 0x1000
#define mmPDMA0_CS_ETF_BASE 0x6C83000ull
#define PDMA0_CS_ETF_MAX_OFFSET 0x1000
#define PDMA0_CS_ETF_SECTION 0x1000
#define mmPDMA0_CS_SPMU_BASE 0x6C84000ull
#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000
#define PDMA0_CS_SPMU_SECTION 0x1000
#define mmPDMA0_BMON_CTI_BASE 0x6C85000ull
#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000
#define PDMA0_BMON_CTI_SECTION 0x1000
#define mmPDMA0_USER_CTI_BASE 0x6C86000ull
#define PDMA0_USER_CTI_MAX_OFFSET 0x1000
#define PDMA0_USER_CTI_SECTION 0x1000
#define mmPDMA0_BMON_0_BASE 0x6C87000ull
#define PDMA0_BMON_0_MAX_OFFSET 0x1000
#define PDMA0_BMON_0_SECTION 0x1000
#define mmPDMA0_BMON_1_BASE 0x6C88000ull
#define PDMA0_BMON_1_MAX_OFFSET 0x1000
#define PDMA0_BMON_1_SECTION 0x1000
#define mmPDMA0_QM_ARC_RTT_BASE 0x6C89000ull
#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define PDMA0_QM_ARC_RTT_SECTION 0x7000
#define mmPDMA1_CS_ROM_TBL_BASE 0x6C90000ull
#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define PDMA1_CS_ROM_TBL_SECTION 0x1000
#define mmPDMA1_CS_STM_BASE 0x6C91000ull
#define PDMA1_CS_STM_MAX_OFFSET 0x1000
#define PDMA1_CS_STM_SECTION 0x1000
#define mmPDMA1_CS_CTI_BASE 0x6C92000ull
#define PDMA1_CS_CTI_MAX_OFFSET 0x1000
#define PDMA1_CS_CTI_SECTION 0x1000
#define mmPDMA1_CS_ETF_BASE 0x6C93000ull
#define PDMA1_CS_ETF_MAX_OFFSET 0x1000
#define PDMA1_CS_ETF_SECTION 0x1000
#define mmPDMA1_CS_SPMU_BASE 0x6C94000ull
#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000
#define PDMA1_CS_SPMU_SECTION 0x1000
#define mmPDMA1_BMON_CTI_BASE 0x6C95000ull
#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000
#define PDMA1_BMON_CTI_SECTION 0x1000
#define mmPDMA1_USER_CTI_BASE 0x6C96000ull
#define PDMA1_USER_CTI_MAX_OFFSET 0x1000
#define PDMA1_USER_CTI_SECTION 0x1000
#define mmPDMA1_BMON_0_BASE 0x6C97000ull
#define PDMA1_BMON_0_MAX_OFFSET 0x1000
#define PDMA1_BMON_0_SECTION 0x1000
#define mmPDMA1_BMON_1_BASE 0x6C98000ull
#define PDMA1_BMON_1_MAX_OFFSET 0x1000
#define PDMA1_BMON_1_SECTION 0x1000
#define mmPDMA1_QM_ARC_RTT_BASE 0x6C99000ull
#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400
#define PDMA1_QM_ARC_RTT_SECTION 0x7000
#define mmXDMA_FUNNEL_BASE 0x6CA0000ull
#define XDMA_FUNNEL_MAX_OFFSET 0x1000
#define XDMA_FUNNEL_SECTION 0x21000
#define mmCPU_ETF_0_BASE 0x6CC1000ull
#define CPU_ETF_0_MAX_OFFSET 0x1000
#define CPU_ETF_0_SECTION 0x1000
#define mmCPU_ETF_1_BASE 0x6CC2000ull
#define CPU_ETF_1_MAX_OFFSET 0x1000
#define CPU_ETF_1_SECTION 0x2000
#define mmCPU_CTI_BASE 0x6CC4000ull
#define CPU_CTI_MAX_OFFSET 0x1000
#define CPU_CTI_SECTION 0x1000
#define mmCPU_FUNNEL_BASE 0x6CC5000ull
#define CPU_FUNNEL_MAX_OFFSET 0x1000
#define CPU_FUNNEL_SECTION 0x1000
#define mmCPU_STM_BASE 0x6CC6000ull
#define CPU_STM_MAX_OFFSET 0x1000
#define CPU_STM_SECTION 0x1000
#define mmCPU_CTI_TRACE_BASE 0x6CC7000ull
#define CPU_CTI_TRACE_MAX_OFFSET 0x1000
#define CPU_CTI_TRACE_SECTION 0x1000
#define mmCPU_ETF_TRACE_BASE 0x6CC8000ull
#define CPU_ETF_TRACE_MAX_OFFSET 0x1000
#define CPU_ETF_TRACE_SECTION 0x1000
#define mmCPU_WR_BMON_BASE 0x6CC9000ull
#define CPU_WR_BMON_MAX_OFFSET 0x1000
#define CPU_WR_BMON_SECTION 0x1000
#define mmCPU_RD_BMON_BASE 0x6CCA000ull
#define CPU_RD_BMON_MAX_OFFSET 0x1000
#define CPU_RD_BMON_SECTION 0x36000
#define mmPMMU_CS_DBG_ROM_TBL_BASE 0x6D00000ull
#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmPMMU_CS_STM_BASE 0x6D01000ull
#define PMMU_CS_STM_MAX_OFFSET 0x1000
#define PMMU_CS_STM_SECTION 0x1000
#define mmPMMU_CS_CTI_BASE 0x6D02000ull
#define PMMU_CS_CTI_MAX_OFFSET 0x1000
#define PMMU_CS_CTI_SECTION 0x1000
#define mmPMMU_CS_ETF_BASE 0x6D03000ull
#define PMMU_CS_ETF_MAX_OFFSET 0x1000
#define PMMU_CS_ETF_SECTION 0x1000
#define mmPMMU_CS_SPMU_BASE 0x6D04000ull
#define PMMU_CS_SPMU_MAX_OFFSET 0x1000
#define PMMU_CS_SPMU_SECTION 0x1000
#define mmPMMU_BMON_CTI_BASE 0x6D05000ull
#define PMMU_BMON_CTI_MAX_OFFSET 0x1000
#define PMMU_BMON_CTI_SECTION 0x1000
#define mmPMMU_USER_CTI_BASE 0x6D06000ull
#define PMMU_USER_CTI_MAX_OFFSET 0x1000
#define PMMU_USER_CTI_SECTION 0x1000
#define mmPMMU_BMON_0_BASE 0x6D07000ull
#define PMMU_BMON_0_MAX_OFFSET 0x1000
#define PMMU_BMON_0_SECTION 0x1000
#define mmPMMU_BMON_1_BASE 0x6D08000ull
#define PMMU_BMON_1_MAX_OFFSET 0x1000
#define PMMU_BMON_1_SECTION 0x1000
#define mmPMMU_BMON_2_BASE 0x6D09000ull
#define PMMU_BMON_2_MAX_OFFSET 0x1000
#define PMMU_BMON_2_SECTION 0x1000
#define mmPMMU_BMON_3_BASE 0x6D0A000ull
#define PMMU_BMON_3_MAX_OFFSET 0x1000
#define PMMU_BMON_3_SECTION 0x1000
#define mmPMMU_BMON_4_BASE 0x6D0B000ull
#define PMMU_BMON_4_MAX_OFFSET 0x1000
#define PMMU_BMON_4_SECTION 0x1000
#define mmPMMU_FUNNEL_BASE 0x6D0C000ull
#define PMMU_FUNNEL_MAX_OFFSET 0x1000
#define PMMU_FUNNEL_SECTION 0x1000
#define mmPMMU_FUNNEL_DEC_BASE 0x6D0D000ull
#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000
#define PMMU_FUNNEL_DEC_SECTION 0x33000
#define mmDCORE0_XBAR_MID_FUNNEL_BASE 0x6D40000ull
#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000
#define mmDCORE0_XBAR_EDGE_FUNNEL_BASE 0x6D48000ull
#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000
#define mmDCORE1_XBAR_MID_FUNNEL_BASE 0x6D50000ull
#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000
#define mmDCORE1_XBAR_EDGE_FUNNEL_BASE 0x6D58000ull
#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000
#define mmDCORE2_XBAR_MID_FUNNEL_BASE 0x6D60000ull
#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000
#define mmDCORE2_XBAR_EDGE_FUNNEL_BASE 0x6D68000ull
#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000
#define mmDCORE3_XBAR_MID_FUNNEL_BASE 0x6D70000ull
#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000
#define mmDCORE3_XBAR_EDGE_FUNNEL_BASE 0x6D78000ull
#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000
#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000
#define mmROT0_CS_ROM_TBL_BASE 0x6E00000ull
#define ROT0_CS_ROM_TBL_MAX_OFFSET 0x1000
#define ROT0_CS_ROM_TBL_SECTION 0x1000
#define mmROT0_CS_STM_BASE 0x6E01000ull
#define ROT0_CS_STM_MAX_OFFSET 0x1000
#define ROT0_CS_STM_SECTION 0x1000
#define mmROT0_CS_CTI_BASE 0x6E02000ull
#define ROT0_CS_CTI_MAX_OFFSET 0x1000
#define ROT0_CS_CTI_SECTION 0x1000
#define mmROT0_CS_ETF_BASE 0x6E03000ull
#define ROT0_CS_ETF_MAX_OFFSET 0x1000
#define ROT0_CS_ETF_SECTION 0x1000
#define mmROT0_CS_SPMU_BASE 0x6E04000ull
#define ROT0_CS_SPMU_MAX_OFFSET 0x1000
#define ROT0_CS_SPMU_SECTION 0x1000
#define mmROT0_BMON_CTI_BASE 0x6E05000ull
#define ROT0_BMON_CTI_MAX_OFFSET 0x1000
#define ROT0_BMON_CTI_SECTION 0x1000
#define mmROT0_USER_CTI_BASE 0x6E06000ull
#define ROT0_USER_CTI_MAX_OFFSET 0x1000
#define ROT0_USER_CTI_SECTION 0x1000
#define mmROT0_BMON_0_BASE 0x6E07000ull
#define ROT0_BMON_0_MAX_OFFSET 0x1000
#define ROT0_BMON_0_SECTION 0x1000
#define mmROT0_BMON_1_BASE 0x6E08000ull
#define ROT0_BMON_1_MAX_OFFSET 0x1000
#define ROT0_BMON_1_SECTION 0x1000
#define mmROT0_BMON_2_BASE 0x6E09000ull
#define ROT0_BMON_2_MAX_OFFSET 0x1000
#define ROT0_BMON_2_SECTION 0x1000
#define mmROT0_BMON_3_BASE 0x6E0A000ull
#define ROT0_BMON_3_MAX_OFFSET 0x1000
#define ROT0_BMON_3_SECTION 0x1000
#define mmROT0_ARC_RTT_BASE 0x6E0B000ull
#define ROT0_ARC_RTT_MAX_OFFSET 0x1400
#define ROT0_ARC_RTT_SECTION 0x5000
#define mmROT1_CS_ROM_TBL_BASE 0x6E10000ull
#define ROT1_CS_ROM_TBL_MAX_OFFSET 0x1000
#define ROT1_CS_ROM_TBL_SECTION 0x1000
#define mmROT1_CS_STM_BASE 0x6E11000ull
#define ROT1_CS_STM_MAX_OFFSET 0x1000
#define ROT1_CS_STM_SECTION 0x1000
#define mmROT1_CS_CTI_BASE 0x6E12000ull
#define ROT1_CS_CTI_MAX_OFFSET 0x1000
#define ROT1_CS_CTI_SECTION 0x1000
#define mmROT1_CS_ETF_BASE 0x6E13000ull
#define ROT1_CS_ETF_MAX_OFFSET 0x1000
#define ROT1_CS_ETF_SECTION 0x1000
#define mmROT1_CS_SPMU_BASE 0x6E14000ull
#define ROT1_CS_SPMU_MAX_OFFSET 0x1000
#define ROT1_CS_SPMU_SECTION 0x1000
#define mmROT1_BMON_CTI_BASE 0x6E15000ull
#define ROT1_BMON_CTI_MAX_OFFSET 0x1000
#define ROT1_BMON_CTI_SECTION 0x1000
#define mmROT1_USER_CTI_BASE 0x6E16000ull
#define ROT1_USER_CTI_MAX_OFFSET 0x1000
#define ROT1_USER_CTI_SECTION 0x1000
#define mmROT1_BMON_0_BASE 0x6E17000ull
#define ROT1_BMON_0_MAX_OFFSET 0x1000
#define ROT1_BMON_0_SECTION 0x1000
#define mmROT1_BMON_1_BASE 0x6E18000ull
#define ROT1_BMON_1_MAX_OFFSET 0x1000
#define ROT1_BMON_1_SECTION 0x1000
#define mmROT1_BMON_2_BASE 0x6E19000ull
#define ROT1_BMON_2_MAX_OFFSET 0x1000
#define ROT1_BMON_2_SECTION 0x1000
#define mmROT1_BMON_3_BASE 0x6E1A000ull
#define ROT1_BMON_3_MAX_OFFSET 0x1000
#define ROT1_BMON_3_SECTION 0x1000
#define mmROT1_ARC_RTT_BASE 0x6E1B000ull
#define ROT1_ARC_RTT_MAX_OFFSET 0x1400
#define ROT1_ARC_RTT_SECTION 0x65000
#define mmARC_FARM_ARC0_RTT_BASE 0x6E80000ull
#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400
#define ARC_FARM_ARC0_RTT_SECTION 0x1000
#define mmARC_FARM_ARC1_RTT_BASE 0x6E81000ull
#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400
#define ARC_FARM_ARC1_RTT_SECTION 0x1000
#define mmARC_FARM_ARC2_RTT_BASE 0x6E82000ull
#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400
#define ARC_FARM_ARC2_RTT_SECTION 0x1000
#define mmARC_FARM_ARC3_RTT_BASE 0x6E83000ull
#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400
#define ARC_FARM_ARC3_RTT_SECTION 0xD000
#define mmARC_FARM_CS_ROM_TBL_BASE 0x6E90000ull
#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000
#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000
#define mmARC_FARM_CS_STM_BASE 0x6E91000ull
#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000
#define ARC_FARM_CS_STM_SECTION 0x1000
#define mmARC_FARM_CS_CTI_BASE 0x6E92000ull
#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000
#define ARC_FARM_CS_CTI_SECTION 0x1000
#define mmARC_FARM_CS_ETF_BASE 0x6E93000ull
#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000
#define ARC_FARM_CS_ETF_SECTION 0x1000
#define mmARC_FARM_CS_SPMU_BASE 0x6E94000ull
#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000
#define ARC_FARM_CS_SPMU_SECTION 0x1000
#define mmARC_FARM_BMON_CTI_BASE 0x6E95000ull
#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000
#define ARC_FARM_BMON_CTI_SECTION 0x1000
#define mmARC_FARM_USER_CTI_BASE 0x6E96000ull
#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000
#define ARC_FARM_USER_CTI_SECTION 0x1000
#define mmARC_FARM_BMON_0_BASE 0x6E97000ull
#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000
#define ARC_FARM_BMON_0_SECTION 0x1000
#define mmARC_FARM_BMON_1_BASE 0x6E98000ull
#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000
#define ARC_FARM_BMON_1_SECTION 0x1000
#define mmARC_FARM_BMON_2_BASE 0x6E99000ull
#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000
#define ARC_FARM_BMON_2_SECTION 0x1000
#define mmARC_FARM_BMON_3_BASE 0x6E9A000ull
#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000
#define ARC_FARM_BMON_3_SECTION 0x1000
#define mmARC_FARM_CTI_BASE 0x6E9B000ull
#define ARC_FARM_CTI_MAX_OFFSET 0x1000
#define ARC_FARM_CTI_SECTION 0x1000
#define mmARC_FARM_FUNNEL_BASE 0x6E9C000ull
#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000
#define ARC_FARM_FUNNEL_SECTION 0x4000
#define mmKDMA_CS_ROM_TBL_BASE 0x6EA0000ull
#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000
#define KDMA_CS_ROM_TBL_SECTION 0x1000
#define mmKDMA_CS_STM_BASE 0x6EA1000ull
#define KDMA_CS_STM_MAX_OFFSET 0x1000
#define KDMA_CS_STM_SECTION 0x1000
#define mmKDMA_CS_CTI_BASE 0x6EA2000ull
#define KDMA_CS_CTI_MAX_OFFSET 0x1000
#define KDMA_CS_CTI_SECTION 0x1000
#define mmKDMA_CS_ETF_BASE 0x6EA3000ull
#define KDMA_CS_ETF_MAX_OFFSET 0x1000
#define KDMA_CS_ETF_SECTION 0x1000
#define mmKDMA_CS_SPMU_BASE 0x6EA4000ull
#define KDMA_CS_SPMU_MAX_OFFSET 0x1000
#define KDMA_CS_SPMU_SECTION 0x1000
#define mmKDMA_BMON_CTI_BASE 0x6EA5000ull
#define KDMA_BMON_CTI_MAX_OFFSET 0x1000
#define KDMA_BMON_CTI_SECTION 0x1000
#define mmKDMA_USER_CTI_BASE 0x6EA6000ull
#define KDMA_USER_CTI_MAX_OFFSET 0x1000
#define KDMA_USER_CTI_SECTION 0x1000
#define mmKDMA_BMON_0_BASE 0x6EA7000ull
#define KDMA_BMON_0_MAX_OFFSET 0x1000
#define KDMA_BMON_0_SECTION 0x1000
#define mmKDMA_BMON_1_BASE 0x6EA8000ull
#define KDMA_BMON_1_MAX_OFFSET 0x1000
#define KDMA_BMON_1_SECTION 0x1000
#define mmKDMA_BMON_2_BASE 0x6EA9000ull
#define KDMA_BMON_2_MAX_OFFSET 0x1000
#define KDMA_BMON_2_SECTION 0x1000
#define mmKDMA_BMON_3_BASE 0x6EAA000ull
#define KDMA_BMON_3_MAX_OFFSET 0x1000
#define KDMA_BMON_3_SECTION 0x56000
#define mmPCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x6F00000ull
#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmPCIE_VDEC0_CS_STM_BASE 0x6F01000ull
#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CS_STM_SECTION 0x1000
#define mmPCIE_VDEC0_CS_CTI_BASE 0x6F02000ull
#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CS_CTI_SECTION 0x1000
#define mmPCIE_VDEC0_CS_ETF_BASE 0x6F03000ull
#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CS_ETF_SECTION 0x1000
#define mmPCIE_VDEC0_CS_SPMU_BASE 0x6F04000ull
#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000
#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000
#define mmPCIE_VDEC0_BMON_CTI_BASE 0x6F05000ull
#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000
#define mmPCIE_VDEC0_USER_CTI_BASE 0x6F06000ull
#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC0_USER_CTI_SECTION 0x1000
#define mmPCIE_VDEC0_BMON_0_BASE 0x6F07000ull
#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000
#define PCIE_VDEC0_BMON_0_SECTION 0x1000
#define mmPCIE_VDEC0_BMON_1_BASE 0x6F08000ull
#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000
#define PCIE_VDEC0_BMON_1_SECTION 0x1000
#define mmPCIE_VDEC0_BMON_2_BASE 0x6F09000ull
#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000
#define PCIE_VDEC0_BMON_2_SECTION 0x7000
#define mmPCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x6F10000ull
#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmPCIE_VDEC1_CS_STM_BASE 0x6F11000ull
#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CS_STM_SECTION 0x1000
#define mmPCIE_VDEC1_CS_CTI_BASE 0x6F12000ull
#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CS_CTI_SECTION 0x1000
#define mmPCIE_VDEC1_CS_ETF_BASE 0x6F13000ull
#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CS_ETF_SECTION 0x1000
#define mmPCIE_VDEC1_CS_SPMU_BASE 0x6F14000ull
#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000
#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000
#define mmPCIE_VDEC1_BMON_CTI_BASE 0x6F15000ull
#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000
#define mmPCIE_VDEC1_USER_CTI_BASE 0x6F16000ull
#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000
#define PCIE_VDEC1_USER_CTI_SECTION 0x1000
#define mmPCIE_VDEC1_BMON_0_BASE 0x6F17000ull
#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000
#define PCIE_VDEC1_BMON_0_SECTION 0x1000
#define mmPCIE_VDEC1_BMON_1_BASE 0x6F18000ull
#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000
#define PCIE_VDEC1_BMON_1_SECTION 0x1000
#define mmPCIE_VDEC1_BMON_2_BASE 0x6F19000ull
#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000
#define PCIE_VDEC1_BMON_2_SECTION 0xF7000
#define mmHBM0_MC0_CS_DBG_ROM_TBL_BASE 0x7010000ull
#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM0_MC0_CS_STM_BASE 0x7011000ull
#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM0_MC0_CS_STM_SECTION 0x1000
#define mmHBM0_MC0_CS_CTI_BASE 0x7012000ull
#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM0_MC0_CS_CTI_SECTION 0x1000
#define mmHBM0_MC0_CS_ETF_BASE 0x7013000ull
#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM0_MC0_CS_ETF_SECTION 0x1000
#define mmHBM0_MC0_CS_SPMU_BASE 0x7014000ull
#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM0_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM0_MC0_BMON_CTI_BASE 0x7015000ull
#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM0_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM0_MC0_USER_CTI_BASE 0x7016000ull
#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM0_MC0_USER_CTI_SECTION 0xA000
#define mmHBM0_MC0_FUNNEL_BASE 0x7020000ull
#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM0_MC0_FUNNEL_SECTION 0x30000
#define mmHBM0_MC1_CS_DBG_ROM_TBL_BASE 0x7050000ull
#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM0_MC1_CS_STM_BASE 0x7051000ull
#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM0_MC1_CS_STM_SECTION 0x1000
#define mmHBM0_MC1_CS_CTI_BASE 0x7052000ull
#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM0_MC1_CS_CTI_SECTION 0x1000
#define mmHBM0_MC1_CS_ETF_BASE 0x7053000ull
#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM0_MC1_CS_ETF_SECTION 0x1000
#define mmHBM0_MC1_CS_SPMU_BASE 0x7054000ull
#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM0_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM0_MC1_BMON_CTI_BASE 0x7055000ull
#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM0_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM0_MC1_USER_CTI_BASE 0x7056000ull
#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM0_MC1_USER_CTI_SECTION 0xA000
#define mmHBM0_MC1_FUNNEL_BASE 0x7060000ull
#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM0_MC1_FUNNEL_SECTION 0x30000
#define mmHBM1_MC0_CS_DBG_ROM_TBL_BASE 0x7090000ull
#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM1_MC0_CS_STM_BASE 0x7091000ull
#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM1_MC0_CS_STM_SECTION 0x1000
#define mmHBM1_MC0_CS_CTI_BASE 0x7092000ull
#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM1_MC0_CS_CTI_SECTION 0x1000
#define mmHBM1_MC0_CS_ETF_BASE 0x7093000ull
#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM1_MC0_CS_ETF_SECTION 0x1000
#define mmHBM1_MC0_CS_SPMU_BASE 0x7094000ull
#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM1_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM1_MC0_BMON_CTI_BASE 0x7095000ull
#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM1_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM1_MC0_USER_CTI_BASE 0x7096000ull
#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM1_MC0_USER_CTI_SECTION 0xA000
#define mmHBM1_MC0_FUNNEL_BASE 0x70A0000ull
#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM1_MC0_FUNNEL_SECTION 0x30000
#define mmHBM1_MC1_CS_DBG_ROM_TBL_BASE 0x70D0000ull
#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM1_MC1_CS_STM_BASE 0x70D1000ull
#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM1_MC1_CS_STM_SECTION 0x1000
#define mmHBM1_MC1_CS_CTI_BASE 0x70D2000ull
#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM1_MC1_CS_CTI_SECTION 0x1000
#define mmHBM1_MC1_CS_ETF_BASE 0x70D3000ull
#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM1_MC1_CS_ETF_SECTION 0x1000
#define mmHBM1_MC1_CS_SPMU_BASE 0x70D4000ull
#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM1_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM1_MC1_BMON_CTI_BASE 0x70D5000ull
#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM1_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM1_MC1_USER_CTI_BASE 0x70D6000ull
#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM1_MC1_USER_CTI_SECTION 0xA000
#define mmHBM1_MC1_FUNNEL_BASE 0x70E0000ull
#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM1_MC1_FUNNEL_SECTION 0x30000
#define mmHBM2_MC0_CS_DBG_ROM_TBL_BASE 0x7110000ull
#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM2_MC0_CS_STM_BASE 0x7111000ull
#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM2_MC0_CS_STM_SECTION 0x1000
#define mmHBM2_MC0_CS_CTI_BASE 0x7112000ull
#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM2_MC0_CS_CTI_SECTION 0x1000
#define mmHBM2_MC0_CS_ETF_BASE 0x7113000ull
#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM2_MC0_CS_ETF_SECTION 0x1000
#define mmHBM2_MC0_CS_SPMU_BASE 0x7114000ull
#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM2_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM2_MC0_BMON_CTI_BASE 0x7115000ull
#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM2_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM2_MC0_USER_CTI_BASE 0x7116000ull
#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM2_MC0_USER_CTI_SECTION 0xA000
#define mmHBM2_MC0_FUNNEL_BASE 0x7120000ull
#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM2_MC0_FUNNEL_SECTION 0x30000
#define mmHBM2_MC1_CS_DBG_ROM_TBL_BASE 0x7150000ull
#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM2_MC1_CS_STM_BASE 0x7151000ull
#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM2_MC1_CS_STM_SECTION 0x1000
#define mmHBM2_MC1_CS_CTI_BASE 0x7152000ull
#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM2_MC1_CS_CTI_SECTION 0x1000
#define mmHBM2_MC1_CS_ETF_BASE 0x7153000ull
#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM2_MC1_CS_ETF_SECTION 0x1000
#define mmHBM2_MC1_CS_SPMU_BASE 0x7154000ull
#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM2_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM2_MC1_BMON_CTI_BASE 0x7155000ull
#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM2_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM2_MC1_USER_CTI_BASE 0x7156000ull
#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM2_MC1_USER_CTI_SECTION 0xA000
#define mmHBM2_MC1_FUNNEL_BASE 0x7160000ull
#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM2_MC1_FUNNEL_SECTION 0x30000
#define mmHBM3_MC0_CS_DBG_ROM_TBL_BASE 0x7190000ull
#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM3_MC0_CS_STM_BASE 0x7191000ull
#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM3_MC0_CS_STM_SECTION 0x1000
#define mmHBM3_MC0_CS_CTI_BASE 0x7192000ull
#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM3_MC0_CS_CTI_SECTION 0x1000
#define mmHBM3_MC0_CS_ETF_BASE 0x7193000ull
#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM3_MC0_CS_ETF_SECTION 0x1000
#define mmHBM3_MC0_CS_SPMU_BASE 0x7194000ull
#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM3_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM3_MC0_BMON_CTI_BASE 0x7195000ull
#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM3_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM3_MC0_USER_CTI_BASE 0x7196000ull
#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM3_MC0_USER_CTI_SECTION 0xA000
#define mmHBM3_MC0_FUNNEL_BASE 0x71A0000ull
#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM3_MC0_FUNNEL_SECTION 0x30000
#define mmHBM3_MC1_CS_DBG_ROM_TBL_BASE 0x71D0000ull
#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM3_MC1_CS_STM_BASE 0x71D1000ull
#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM3_MC1_CS_STM_SECTION 0x1000
#define mmHBM3_MC1_CS_CTI_BASE 0x71D2000ull
#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM3_MC1_CS_CTI_SECTION 0x1000
#define mmHBM3_MC1_CS_ETF_BASE 0x71D3000ull
#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM3_MC1_CS_ETF_SECTION 0x1000
#define mmHBM3_MC1_CS_SPMU_BASE 0x71D4000ull
#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM3_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM3_MC1_BMON_CTI_BASE 0x71D5000ull
#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM3_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM3_MC1_USER_CTI_BASE 0x71D6000ull
#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM3_MC1_USER_CTI_SECTION 0xA000
#define mmHBM3_MC1_FUNNEL_BASE 0x71E0000ull
#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM3_MC1_FUNNEL_SECTION 0x30000
#define mmHBM4_MC0_CS_DBG_ROM_TBL_BASE 0x7210000ull
#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM4_MC0_CS_STM_BASE 0x7211000ull
#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM4_MC0_CS_STM_SECTION 0x1000
#define mmHBM4_MC0_CS_CTI_BASE 0x7212000ull
#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM4_MC0_CS_CTI_SECTION 0x1000
#define mmHBM4_MC0_CS_ETF_BASE 0x7213000ull
#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM4_MC0_CS_ETF_SECTION 0x1000
#define mmHBM4_MC0_CS_SPMU_BASE 0x7214000ull
#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM4_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM4_MC0_BMON_CTI_BASE 0x7215000ull
#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM4_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM4_MC0_USER_CTI_BASE 0x7216000ull
#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM4_MC0_USER_CTI_SECTION 0xA000
#define mmHBM4_MC0_FUNNEL_BASE 0x7220000ull
#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM4_MC0_FUNNEL_SECTION 0x30000
#define mmHBM4_MC1_CS_DBG_ROM_TBL_BASE 0x7250000ull
#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM4_MC1_CS_STM_BASE 0x7251000ull
#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM4_MC1_CS_STM_SECTION 0x1000
#define mmHBM4_MC1_CS_CTI_BASE 0x7252000ull
#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM4_MC1_CS_CTI_SECTION 0x1000
#define mmHBM4_MC1_CS_ETF_BASE 0x7253000ull
#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM4_MC1_CS_ETF_SECTION 0x1000
#define mmHBM4_MC1_CS_SPMU_BASE 0x7254000ull
#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM4_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM4_MC1_BMON_CTI_BASE 0x7255000ull
#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM4_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM4_MC1_USER_CTI_BASE 0x7256000ull
#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM4_MC1_USER_CTI_SECTION 0xA000
#define mmHBM4_MC1_FUNNEL_BASE 0x7260000ull
#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM4_MC1_FUNNEL_SECTION 0x30000
#define mmHBM5_MC0_CS_DBG_ROM_TBL_BASE 0x7290000ull
#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM5_MC0_CS_STM_BASE 0x7291000ull
#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000
#define HBM5_MC0_CS_STM_SECTION 0x1000
#define mmHBM5_MC0_CS_CTI_BASE 0x7292000ull
#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000
#define HBM5_MC0_CS_CTI_SECTION 0x1000
#define mmHBM5_MC0_CS_ETF_BASE 0x7293000ull
#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000
#define HBM5_MC0_CS_ETF_SECTION 0x1000
#define mmHBM5_MC0_CS_SPMU_BASE 0x7294000ull
#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000
#define HBM5_MC0_CS_SPMU_SECTION 0x1000
#define mmHBM5_MC0_BMON_CTI_BASE 0x7295000ull
#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000
#define HBM5_MC0_BMON_CTI_SECTION 0x1000
#define mmHBM5_MC0_USER_CTI_BASE 0x7296000ull
#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000
#define HBM5_MC0_USER_CTI_SECTION 0xA000
#define mmHBM5_MC0_FUNNEL_BASE 0x72A0000ull
#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000
#define HBM5_MC0_FUNNEL_SECTION 0x30000
#define mmHBM5_MC1_CS_DBG_ROM_TBL_BASE 0x72D0000ull
#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000
#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000
#define mmHBM5_MC1_CS_STM_BASE 0x72D1000ull
#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000
#define HBM5_MC1_CS_STM_SECTION 0x1000
#define mmHBM5_MC1_CS_CTI_BASE 0x72D2000ull
#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000
#define HBM5_MC1_CS_CTI_SECTION 0x1000
#define mmHBM5_MC1_CS_ETF_BASE 0x72D3000ull
#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000
#define HBM5_MC1_CS_ETF_SECTION 0x1000
#define mmHBM5_MC1_CS_SPMU_BASE 0x72D4000ull
#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000
#define HBM5_MC1_CS_SPMU_SECTION 0x1000
#define mmHBM5_MC1_BMON_CTI_BASE 0x72D5000ull
#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000
#define HBM5_MC1_BMON_CTI_SECTION 0x1000
#define mmHBM5_MC1_USER_CTI_BASE 0x72D6000ull
#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000
#define HBM5_MC1_USER_CTI_SECTION 0xA000
#define mmHBM5_MC1_FUNNEL_BASE 0x72E0000ull
#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000
#define HBM5_MC1_FUNNEL_SECTION 0x20000
#define mmNIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7300000ull
#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC0_DBG_STM_0_BASE 0x7301000ull
#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC0_DBG_STM_0_SECTION 0x1000
#define mmNIC0_DBG_CTI_0_BASE 0x7302000ull
#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC0_DBG_CTI_0_SECTION 0x1000
#define mmNIC0_DBG_ETF_0_BASE 0x7303000ull
#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC0_DBG_ETF_0_SECTION 0x1000
#define mmNIC0_DBG_SPMU_0_BASE 0x7304000ull
#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC0_DBG_SPMU_0_SECTION 0x1000
#define mmNIC0_DBG_USER_CTI_0_BASE 0x7305000ull
#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC0_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC0_DBG_BMON_CTI_0_BASE 0x7306000ull
#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC0_DBG_BMON0_0_BASE 0x7307000ull
#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON0_0_SECTION 0x1000
#define mmNIC0_DBG_BMON1_0_BASE 0x7308000ull
#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON1_0_SECTION 0x1000
#define mmNIC0_DBG_BMON2_0_BASE 0x7309000ull
#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON2_0_SECTION 0x7000
#define mmNIC0_DBG_ARC_RTT0_BASE 0x7310000ull
#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC0_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7320000ull
#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC0_DBG_STM_1_BASE 0x7321000ull
#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC0_DBG_STM_1_SECTION 0x1000
#define mmNIC0_DBG_CTI_1_BASE 0x7322000ull
#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC0_DBG_CTI_1_SECTION 0x1000
#define mmNIC0_DBG_ETF_1_BASE 0x7323000ull
#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC0_DBG_ETF_1_SECTION 0x1000
#define mmNIC0_DBG_SPMU_1_BASE 0x7324000ull
#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC0_DBG_SPMU_1_SECTION 0x1000
#define mmNIC0_DBG_USER_CTI_1_BASE 0x7325000ull
#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC0_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC0_DBG_BMON_CTI_1_BASE 0x7326000ull
#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC0_DBG_BMON0_1_BASE 0x7327000ull
#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON0_1_SECTION 0x1000
#define mmNIC0_DBG_BMON1_1_BASE 0x7328000ull
#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON1_1_SECTION 0x1000
#define mmNIC0_DBG_BMON2_1_BASE 0x7329000ull
#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC0_DBG_BMON2_1_SECTION 0x7000
#define mmNIC0_DBG_ARC_RTT1_BASE 0x7330000ull
#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC0_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC0_DBG_FUNNEL_TX_BASE 0x7338000ull
#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC0_DBG_FUNNEL_NCH_BASE 0x7339000ull
#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7340000ull
#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC1_DBG_STM_0_BASE 0x7341000ull
#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC1_DBG_STM_0_SECTION 0x1000
#define mmNIC1_DBG_CTI_0_BASE 0x7342000ull
#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC1_DBG_CTI_0_SECTION 0x1000
#define mmNIC1_DBG_ETF_0_BASE 0x7343000ull
#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC1_DBG_ETF_0_SECTION 0x1000
#define mmNIC1_DBG_SPMU_0_BASE 0x7344000ull
#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC1_DBG_SPMU_0_SECTION 0x1000
#define mmNIC1_DBG_USER_CTI_0_BASE 0x7345000ull
#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC1_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC1_DBG_BMON_CTI_0_BASE 0x7346000ull
#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC1_DBG_BMON0_0_BASE 0x7347000ull
#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON0_0_SECTION 0x1000
#define mmNIC1_DBG_BMON1_0_BASE 0x7348000ull
#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON1_0_SECTION 0x1000
#define mmNIC1_DBG_BMON2_0_BASE 0x7349000ull
#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON2_0_SECTION 0x7000
#define mmNIC1_DBG_ARC_RTT0_BASE 0x7350000ull
#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC1_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7360000ull
#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC1_DBG_STM_1_BASE 0x7361000ull
#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC1_DBG_STM_1_SECTION 0x1000
#define mmNIC1_DBG_CTI_1_BASE 0x7362000ull
#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC1_DBG_CTI_1_SECTION 0x1000
#define mmNIC1_DBG_ETF_1_BASE 0x7363000ull
#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC1_DBG_ETF_1_SECTION 0x1000
#define mmNIC1_DBG_SPMU_1_BASE 0x7364000ull
#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC1_DBG_SPMU_1_SECTION 0x1000
#define mmNIC1_DBG_USER_CTI_1_BASE 0x7365000ull
#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC1_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC1_DBG_BMON_CTI_1_BASE 0x7366000ull
#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC1_DBG_BMON0_1_BASE 0x7367000ull
#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON0_1_SECTION 0x1000
#define mmNIC1_DBG_BMON1_1_BASE 0x7368000ull
#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON1_1_SECTION 0x1000
#define mmNIC1_DBG_BMON2_1_BASE 0x7369000ull
#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC1_DBG_BMON2_1_SECTION 0x7000
#define mmNIC1_DBG_ARC_RTT1_BASE 0x7370000ull
#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC1_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC1_DBG_FUNNEL_TX_BASE 0x7378000ull
#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC1_DBG_FUNNEL_NCH_BASE 0x7379000ull
#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7380000ull
#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC2_DBG_STM_0_BASE 0x7381000ull
#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC2_DBG_STM_0_SECTION 0x1000
#define mmNIC2_DBG_CTI_0_BASE 0x7382000ull
#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC2_DBG_CTI_0_SECTION 0x1000
#define mmNIC2_DBG_ETF_0_BASE 0x7383000ull
#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC2_DBG_ETF_0_SECTION 0x1000
#define mmNIC2_DBG_SPMU_0_BASE 0x7384000ull
#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC2_DBG_SPMU_0_SECTION 0x1000
#define mmNIC2_DBG_USER_CTI_0_BASE 0x7385000ull
#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC2_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC2_DBG_BMON_CTI_0_BASE 0x7386000ull
#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC2_DBG_BMON0_0_BASE 0x7387000ull
#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON0_0_SECTION 0x1000
#define mmNIC2_DBG_BMON1_0_BASE 0x7388000ull
#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON1_0_SECTION 0x1000
#define mmNIC2_DBG_BMON2_0_BASE 0x7389000ull
#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON2_0_SECTION 0x7000
#define mmNIC2_DBG_ARC_RTT0_BASE 0x7390000ull
#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC2_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73A0000ull
#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC2_DBG_STM_1_BASE 0x73A1000ull
#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC2_DBG_STM_1_SECTION 0x1000
#define mmNIC2_DBG_CTI_1_BASE 0x73A2000ull
#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC2_DBG_CTI_1_SECTION 0x1000
#define mmNIC2_DBG_ETF_1_BASE 0x73A3000ull
#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC2_DBG_ETF_1_SECTION 0x1000
#define mmNIC2_DBG_SPMU_1_BASE 0x73A4000ull
#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC2_DBG_SPMU_1_SECTION 0x1000
#define mmNIC2_DBG_USER_CTI_1_BASE 0x73A5000ull
#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC2_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC2_DBG_BMON_CTI_1_BASE 0x73A6000ull
#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC2_DBG_BMON0_1_BASE 0x73A7000ull
#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON0_1_SECTION 0x1000
#define mmNIC2_DBG_BMON1_1_BASE 0x73A8000ull
#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON1_1_SECTION 0x1000
#define mmNIC2_DBG_BMON2_1_BASE 0x73A9000ull
#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC2_DBG_BMON2_1_SECTION 0x7000
#define mmNIC2_DBG_ARC_RTT1_BASE 0x73B0000ull
#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC2_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC2_DBG_FUNNEL_TX_BASE 0x73B8000ull
#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC2_DBG_FUNNEL_NCH_BASE 0x73B9000ull
#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x73C0000ull
#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC3_DBG_STM_0_BASE 0x73C1000ull
#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC3_DBG_STM_0_SECTION 0x1000
#define mmNIC3_DBG_CTI_0_BASE 0x73C2000ull
#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC3_DBG_CTI_0_SECTION 0x1000
#define mmNIC3_DBG_ETF_0_BASE 0x73C3000ull
#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC3_DBG_ETF_0_SECTION 0x1000
#define mmNIC3_DBG_SPMU_0_BASE 0x73C4000ull
#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC3_DBG_SPMU_0_SECTION 0x1000
#define mmNIC3_DBG_USER_CTI_0_BASE 0x73C5000ull
#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC3_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC3_DBG_BMON_CTI_0_BASE 0x73C6000ull
#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC3_DBG_BMON0_0_BASE 0x73C7000ull
#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON0_0_SECTION 0x1000
#define mmNIC3_DBG_BMON1_0_BASE 0x73C8000ull
#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON1_0_SECTION 0x1000
#define mmNIC3_DBG_BMON2_0_BASE 0x73C9000ull
#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON2_0_SECTION 0x7000
#define mmNIC3_DBG_ARC_RTT0_BASE 0x73D0000ull
#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC3_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x73E0000ull
#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC3_DBG_STM_1_BASE 0x73E1000ull
#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC3_DBG_STM_1_SECTION 0x1000
#define mmNIC3_DBG_CTI_1_BASE 0x73E2000ull
#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC3_DBG_CTI_1_SECTION 0x1000
#define mmNIC3_DBG_ETF_1_BASE 0x73E3000ull
#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC3_DBG_ETF_1_SECTION 0x1000
#define mmNIC3_DBG_SPMU_1_BASE 0x73E4000ull
#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC3_DBG_SPMU_1_SECTION 0x1000
#define mmNIC3_DBG_USER_CTI_1_BASE 0x73E5000ull
#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC3_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC3_DBG_BMON_CTI_1_BASE 0x73E6000ull
#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC3_DBG_BMON0_1_BASE 0x73E7000ull
#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON0_1_SECTION 0x1000
#define mmNIC3_DBG_BMON1_1_BASE 0x73E8000ull
#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON1_1_SECTION 0x1000
#define mmNIC3_DBG_BMON2_1_BASE 0x73E9000ull
#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC3_DBG_BMON2_1_SECTION 0x7000
#define mmNIC3_DBG_ARC_RTT1_BASE 0x73F0000ull
#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC3_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC3_DBG_FUNNEL_TX_BASE 0x73F8000ull
#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC3_DBG_FUNNEL_NCH_BASE 0x73F9000ull
#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7400000ull
#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC4_DBG_STM_0_BASE 0x7401000ull
#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC4_DBG_STM_0_SECTION 0x1000
#define mmNIC4_DBG_CTI_0_BASE 0x7402000ull
#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC4_DBG_CTI_0_SECTION 0x1000
#define mmNIC4_DBG_ETF_0_BASE 0x7403000ull
#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC4_DBG_ETF_0_SECTION 0x1000
#define mmNIC4_DBG_SPMU_0_BASE 0x7404000ull
#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC4_DBG_SPMU_0_SECTION 0x1000
#define mmNIC4_DBG_USER_CTI_0_BASE 0x7405000ull
#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC4_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC4_DBG_BMON_CTI_0_BASE 0x7406000ull
#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC4_DBG_BMON0_0_BASE 0x7407000ull
#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON0_0_SECTION 0x1000
#define mmNIC4_DBG_BMON1_0_BASE 0x7408000ull
#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON1_0_SECTION 0x1000
#define mmNIC4_DBG_BMON2_0_BASE 0x7409000ull
#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON2_0_SECTION 0x7000
#define mmNIC4_DBG_ARC_RTT0_BASE 0x7410000ull
#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC4_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7420000ull
#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC4_DBG_STM_1_BASE 0x7421000ull
#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC4_DBG_STM_1_SECTION 0x1000
#define mmNIC4_DBG_CTI_1_BASE 0x7422000ull
#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC4_DBG_CTI_1_SECTION 0x1000
#define mmNIC4_DBG_ETF_1_BASE 0x7423000ull
#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC4_DBG_ETF_1_SECTION 0x1000
#define mmNIC4_DBG_SPMU_1_BASE 0x7424000ull
#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC4_DBG_SPMU_1_SECTION 0x1000
#define mmNIC4_DBG_USER_CTI_1_BASE 0x7425000ull
#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC4_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC4_DBG_BMON_CTI_1_BASE 0x7426000ull
#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC4_DBG_BMON0_1_BASE 0x7427000ull
#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON0_1_SECTION 0x1000
#define mmNIC4_DBG_BMON1_1_BASE 0x7428000ull
#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON1_1_SECTION 0x1000
#define mmNIC4_DBG_BMON2_1_BASE 0x7429000ull
#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC4_DBG_BMON2_1_SECTION 0x7000
#define mmNIC4_DBG_ARC_RTT1_BASE 0x7430000ull
#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC4_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC4_DBG_FUNNEL_TX_BASE 0x7438000ull
#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC4_DBG_FUNNEL_NCH_BASE 0x7439000ull
#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7440000ull
#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC5_DBG_STM_0_BASE 0x7441000ull
#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC5_DBG_STM_0_SECTION 0x1000
#define mmNIC5_DBG_CTI_0_BASE 0x7442000ull
#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC5_DBG_CTI_0_SECTION 0x1000
#define mmNIC5_DBG_ETF_0_BASE 0x7443000ull
#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC5_DBG_ETF_0_SECTION 0x1000
#define mmNIC5_DBG_SPMU_0_BASE 0x7444000ull
#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC5_DBG_SPMU_0_SECTION 0x1000
#define mmNIC5_DBG_USER_CTI_0_BASE 0x7445000ull
#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC5_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC5_DBG_BMON_CTI_0_BASE 0x7446000ull
#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC5_DBG_BMON0_0_BASE 0x7447000ull
#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON0_0_SECTION 0x1000
#define mmNIC5_DBG_BMON1_0_BASE 0x7448000ull
#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON1_0_SECTION 0x1000
#define mmNIC5_DBG_BMON2_0_BASE 0x7449000ull
#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON2_0_SECTION 0x7000
#define mmNIC5_DBG_ARC_RTT0_BASE 0x7450000ull
#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC5_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7460000ull
#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC5_DBG_STM_1_BASE 0x7461000ull
#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC5_DBG_STM_1_SECTION 0x1000
#define mmNIC5_DBG_CTI_1_BASE 0x7462000ull
#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC5_DBG_CTI_1_SECTION 0x1000
#define mmNIC5_DBG_ETF_1_BASE 0x7463000ull
#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC5_DBG_ETF_1_SECTION 0x1000
#define mmNIC5_DBG_SPMU_1_BASE 0x7464000ull
#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC5_DBG_SPMU_1_SECTION 0x1000
#define mmNIC5_DBG_USER_CTI_1_BASE 0x7465000ull
#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC5_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC5_DBG_BMON_CTI_1_BASE 0x7466000ull
#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC5_DBG_BMON0_1_BASE 0x7467000ull
#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON0_1_SECTION 0x1000
#define mmNIC5_DBG_BMON1_1_BASE 0x7468000ull
#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON1_1_SECTION 0x1000
#define mmNIC5_DBG_BMON2_1_BASE 0x7469000ull
#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC5_DBG_BMON2_1_SECTION 0x7000
#define mmNIC5_DBG_ARC_RTT1_BASE 0x7470000ull
#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC5_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC5_DBG_FUNNEL_TX_BASE 0x7478000ull
#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC5_DBG_FUNNEL_NCH_BASE 0x7479000ull
#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7480000ull
#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC6_DBG_STM_0_BASE 0x7481000ull
#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC6_DBG_STM_0_SECTION 0x1000
#define mmNIC6_DBG_CTI_0_BASE 0x7482000ull
#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC6_DBG_CTI_0_SECTION 0x1000
#define mmNIC6_DBG_ETF_0_BASE 0x7483000ull
#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC6_DBG_ETF_0_SECTION 0x1000
#define mmNIC6_DBG_SPMU_0_BASE 0x7484000ull
#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC6_DBG_SPMU_0_SECTION 0x1000
#define mmNIC6_DBG_USER_CTI_0_BASE 0x7485000ull
#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC6_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC6_DBG_BMON_CTI_0_BASE 0x7486000ull
#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC6_DBG_BMON0_0_BASE 0x7487000ull
#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON0_0_SECTION 0x1000
#define mmNIC6_DBG_BMON1_0_BASE 0x7488000ull
#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON1_0_SECTION 0x1000
#define mmNIC6_DBG_BMON2_0_BASE 0x7489000ull
#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON2_0_SECTION 0x7000
#define mmNIC6_DBG_ARC_RTT0_BASE 0x7490000ull
#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC6_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74A0000ull
#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC6_DBG_STM_1_BASE 0x74A1000ull
#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC6_DBG_STM_1_SECTION 0x1000
#define mmNIC6_DBG_CTI_1_BASE 0x74A2000ull
#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC6_DBG_CTI_1_SECTION 0x1000
#define mmNIC6_DBG_ETF_1_BASE 0x74A3000ull
#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC6_DBG_ETF_1_SECTION 0x1000
#define mmNIC6_DBG_SPMU_1_BASE 0x74A4000ull
#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC6_DBG_SPMU_1_SECTION 0x1000
#define mmNIC6_DBG_USER_CTI_1_BASE 0x74A5000ull
#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC6_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC6_DBG_BMON_CTI_1_BASE 0x74A6000ull
#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC6_DBG_BMON0_1_BASE 0x74A7000ull
#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON0_1_SECTION 0x1000
#define mmNIC6_DBG_BMON1_1_BASE 0x74A8000ull
#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON1_1_SECTION 0x1000
#define mmNIC6_DBG_BMON2_1_BASE 0x74A9000ull
#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC6_DBG_BMON2_1_SECTION 0x7000
#define mmNIC6_DBG_ARC_RTT1_BASE 0x74B0000ull
#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC6_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC6_DBG_FUNNEL_TX_BASE 0x74B8000ull
#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC6_DBG_FUNNEL_NCH_BASE 0x74B9000ull
#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x74C0000ull
#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC7_DBG_STM_0_BASE 0x74C1000ull
#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC7_DBG_STM_0_SECTION 0x1000
#define mmNIC7_DBG_CTI_0_BASE 0x74C2000ull
#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC7_DBG_CTI_0_SECTION 0x1000
#define mmNIC7_DBG_ETF_0_BASE 0x74C3000ull
#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC7_DBG_ETF_0_SECTION 0x1000
#define mmNIC7_DBG_SPMU_0_BASE 0x74C4000ull
#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC7_DBG_SPMU_0_SECTION 0x1000
#define mmNIC7_DBG_USER_CTI_0_BASE 0x74C5000ull
#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC7_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC7_DBG_BMON_CTI_0_BASE 0x74C6000ull
#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC7_DBG_BMON0_0_BASE 0x74C7000ull
#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON0_0_SECTION 0x1000
#define mmNIC7_DBG_BMON1_0_BASE 0x74C8000ull
#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON1_0_SECTION 0x1000
#define mmNIC7_DBG_BMON2_0_BASE 0x74C9000ull
#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON2_0_SECTION 0x7000
#define mmNIC7_DBG_ARC_RTT0_BASE 0x74D0000ull
#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC7_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x74E0000ull
#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC7_DBG_STM_1_BASE 0x74E1000ull
#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC7_DBG_STM_1_SECTION 0x1000
#define mmNIC7_DBG_CTI_1_BASE 0x74E2000ull
#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC7_DBG_CTI_1_SECTION 0x1000
#define mmNIC7_DBG_ETF_1_BASE 0x74E3000ull
#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC7_DBG_ETF_1_SECTION 0x1000
#define mmNIC7_DBG_SPMU_1_BASE 0x74E4000ull
#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC7_DBG_SPMU_1_SECTION 0x1000
#define mmNIC7_DBG_USER_CTI_1_BASE 0x74E5000ull
#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC7_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC7_DBG_BMON_CTI_1_BASE 0x74E6000ull
#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC7_DBG_BMON0_1_BASE 0x74E7000ull
#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON0_1_SECTION 0x1000
#define mmNIC7_DBG_BMON1_1_BASE 0x74E8000ull
#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON1_1_SECTION 0x1000
#define mmNIC7_DBG_BMON2_1_BASE 0x74E9000ull
#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC7_DBG_BMON2_1_SECTION 0x7000
#define mmNIC7_DBG_ARC_RTT1_BASE 0x74F0000ull
#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC7_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC7_DBG_FUNNEL_TX_BASE 0x74F8000ull
#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC7_DBG_FUNNEL_NCH_BASE 0x74F9000ull
#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7500000ull
#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC8_DBG_STM_0_BASE 0x7501000ull
#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC8_DBG_STM_0_SECTION 0x1000
#define mmNIC8_DBG_CTI_0_BASE 0x7502000ull
#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC8_DBG_CTI_0_SECTION 0x1000
#define mmNIC8_DBG_ETF_0_BASE 0x7503000ull
#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC8_DBG_ETF_0_SECTION 0x1000
#define mmNIC8_DBG_SPMU_0_BASE 0x7504000ull
#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC8_DBG_SPMU_0_SECTION 0x1000
#define mmNIC8_DBG_USER_CTI_0_BASE 0x7505000ull
#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC8_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC8_DBG_BMON_CTI_0_BASE 0x7506000ull
#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC8_DBG_BMON0_0_BASE 0x7507000ull
#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON0_0_SECTION 0x1000
#define mmNIC8_DBG_BMON1_0_BASE 0x7508000ull
#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON1_0_SECTION 0x1000
#define mmNIC8_DBG_BMON2_0_BASE 0x7509000ull
#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON2_0_SECTION 0x7000
#define mmNIC8_DBG_ARC_RTT0_BASE 0x7510000ull
#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC8_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7520000ull
#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC8_DBG_STM_1_BASE 0x7521000ull
#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC8_DBG_STM_1_SECTION 0x1000
#define mmNIC8_DBG_CTI_1_BASE 0x7522000ull
#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC8_DBG_CTI_1_SECTION 0x1000
#define mmNIC8_DBG_ETF_1_BASE 0x7523000ull
#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC8_DBG_ETF_1_SECTION 0x1000
#define mmNIC8_DBG_SPMU_1_BASE 0x7524000ull
#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC8_DBG_SPMU_1_SECTION 0x1000
#define mmNIC8_DBG_USER_CTI_1_BASE 0x7525000ull
#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC8_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC8_DBG_BMON_CTI_1_BASE 0x7526000ull
#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC8_DBG_BMON0_1_BASE 0x7527000ull
#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON0_1_SECTION 0x1000
#define mmNIC8_DBG_BMON1_1_BASE 0x7528000ull
#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON1_1_SECTION 0x1000
#define mmNIC8_DBG_BMON2_1_BASE 0x7529000ull
#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC8_DBG_BMON2_1_SECTION 0x7000
#define mmNIC8_DBG_ARC_RTT1_BASE 0x7530000ull
#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC8_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC8_DBG_FUNNEL_TX_BASE 0x7538000ull
#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC8_DBG_FUNNEL_NCH_BASE 0x7539000ull
#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7540000ull
#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC9_DBG_STM_0_BASE 0x7541000ull
#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC9_DBG_STM_0_SECTION 0x1000
#define mmNIC9_DBG_CTI_0_BASE 0x7542000ull
#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC9_DBG_CTI_0_SECTION 0x1000
#define mmNIC9_DBG_ETF_0_BASE 0x7543000ull
#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC9_DBG_ETF_0_SECTION 0x1000
#define mmNIC9_DBG_SPMU_0_BASE 0x7544000ull
#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC9_DBG_SPMU_0_SECTION 0x1000
#define mmNIC9_DBG_USER_CTI_0_BASE 0x7545000ull
#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC9_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC9_DBG_BMON_CTI_0_BASE 0x7546000ull
#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC9_DBG_BMON0_0_BASE 0x7547000ull
#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON0_0_SECTION 0x1000
#define mmNIC9_DBG_BMON1_0_BASE 0x7548000ull
#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON1_0_SECTION 0x1000
#define mmNIC9_DBG_BMON2_0_BASE 0x7549000ull
#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON2_0_SECTION 0x7000
#define mmNIC9_DBG_ARC_RTT0_BASE 0x7550000ull
#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC9_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x7560000ull
#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC9_DBG_STM_1_BASE 0x7561000ull
#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC9_DBG_STM_1_SECTION 0x1000
#define mmNIC9_DBG_CTI_1_BASE 0x7562000ull
#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC9_DBG_CTI_1_SECTION 0x1000
#define mmNIC9_DBG_ETF_1_BASE 0x7563000ull
#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC9_DBG_ETF_1_SECTION 0x1000
#define mmNIC9_DBG_SPMU_1_BASE 0x7564000ull
#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC9_DBG_SPMU_1_SECTION 0x1000
#define mmNIC9_DBG_USER_CTI_1_BASE 0x7565000ull
#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC9_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC9_DBG_BMON_CTI_1_BASE 0x7566000ull
#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC9_DBG_BMON0_1_BASE 0x7567000ull
#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON0_1_SECTION 0x1000
#define mmNIC9_DBG_BMON1_1_BASE 0x7568000ull
#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON1_1_SECTION 0x1000
#define mmNIC9_DBG_BMON2_1_BASE 0x7569000ull
#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC9_DBG_BMON2_1_SECTION 0x7000
#define mmNIC9_DBG_ARC_RTT1_BASE 0x7570000ull
#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC9_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC9_DBG_FUNNEL_TX_BASE 0x7578000ull
#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC9_DBG_FUNNEL_NCH_BASE 0x7579000ull
#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x7580000ull
#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC10_DBG_STM_0_BASE 0x7581000ull
#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC10_DBG_STM_0_SECTION 0x1000
#define mmNIC10_DBG_CTI_0_BASE 0x7582000ull
#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC10_DBG_CTI_0_SECTION 0x1000
#define mmNIC10_DBG_ETF_0_BASE 0x7583000ull
#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC10_DBG_ETF_0_SECTION 0x1000
#define mmNIC10_DBG_SPMU_0_BASE 0x7584000ull
#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC10_DBG_SPMU_0_SECTION 0x1000
#define mmNIC10_DBG_USER_CTI_0_BASE 0x7585000ull
#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC10_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC10_DBG_BMON_CTI_0_BASE 0x7586000ull
#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC10_DBG_BMON0_0_BASE 0x7587000ull
#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON0_0_SECTION 0x1000
#define mmNIC10_DBG_BMON1_0_BASE 0x7588000ull
#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON1_0_SECTION 0x1000
#define mmNIC10_DBG_BMON2_0_BASE 0x7589000ull
#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON2_0_SECTION 0x7000
#define mmNIC10_DBG_ARC_RTT0_BASE 0x7590000ull
#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC10_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75A0000ull
#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC10_DBG_STM_1_BASE 0x75A1000ull
#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC10_DBG_STM_1_SECTION 0x1000
#define mmNIC10_DBG_CTI_1_BASE 0x75A2000ull
#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC10_DBG_CTI_1_SECTION 0x1000
#define mmNIC10_DBG_ETF_1_BASE 0x75A3000ull
#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC10_DBG_ETF_1_SECTION 0x1000
#define mmNIC10_DBG_SPMU_1_BASE 0x75A4000ull
#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC10_DBG_SPMU_1_SECTION 0x1000
#define mmNIC10_DBG_USER_CTI_1_BASE 0x75A5000ull
#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC10_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC10_DBG_BMON_CTI_1_BASE 0x75A6000ull
#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC10_DBG_BMON0_1_BASE 0x75A7000ull
#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON0_1_SECTION 0x1000
#define mmNIC10_DBG_BMON1_1_BASE 0x75A8000ull
#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON1_1_SECTION 0x1000
#define mmNIC10_DBG_BMON2_1_BASE 0x75A9000ull
#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC10_DBG_BMON2_1_SECTION 0x7000
#define mmNIC10_DBG_ARC_RTT1_BASE 0x75B0000ull
#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC10_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC10_DBG_FUNNEL_TX_BASE 0x75B8000ull
#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC10_DBG_FUNNEL_NCH_BASE 0x75B9000ull
#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000
#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000
#define mmNIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x75C0000ull
#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000
#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000
#define mmNIC11_DBG_STM_0_BASE 0x75C1000ull
#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000
#define NIC11_DBG_STM_0_SECTION 0x1000
#define mmNIC11_DBG_CTI_0_BASE 0x75C2000ull
#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000
#define NIC11_DBG_CTI_0_SECTION 0x1000
#define mmNIC11_DBG_ETF_0_BASE 0x75C3000ull
#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000
#define NIC11_DBG_ETF_0_SECTION 0x1000
#define mmNIC11_DBG_SPMU_0_BASE 0x75C4000ull
#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000
#define NIC11_DBG_SPMU_0_SECTION 0x1000
#define mmNIC11_DBG_USER_CTI_0_BASE 0x75C5000ull
#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000
#define NIC11_DBG_USER_CTI_0_SECTION 0x1000
#define mmNIC11_DBG_BMON_CTI_0_BASE 0x75C6000ull
#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000
#define mmNIC11_DBG_BMON0_0_BASE 0x75C7000ull
#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON0_0_SECTION 0x1000
#define mmNIC11_DBG_BMON1_0_BASE 0x75C8000ull
#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON1_0_SECTION 0x1000
#define mmNIC11_DBG_BMON2_0_BASE 0x75C9000ull
#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON2_0_SECTION 0x7000
#define mmNIC11_DBG_ARC_RTT0_BASE 0x75D0000ull
#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400
#define NIC11_DBG_ARC_RTT0_SECTION 0x10000
#define mmNIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x75E0000ull
#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000
#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000
#define mmNIC11_DBG_STM_1_BASE 0x75E1000ull
#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000
#define NIC11_DBG_STM_1_SECTION 0x1000
#define mmNIC11_DBG_CTI_1_BASE 0x75E2000ull
#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000
#define NIC11_DBG_CTI_1_SECTION 0x1000
#define mmNIC11_DBG_ETF_1_BASE 0x75E3000ull
#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000
#define NIC11_DBG_ETF_1_SECTION 0x1000
#define mmNIC11_DBG_SPMU_1_BASE 0x75E4000ull
#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000
#define NIC11_DBG_SPMU_1_SECTION 0x1000
#define mmNIC11_DBG_USER_CTI_1_BASE 0x75E5000ull
#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000
#define NIC11_DBG_USER_CTI_1_SECTION 0x1000
#define mmNIC11_DBG_BMON_CTI_1_BASE 0x75E6000ull
#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000
#define mmNIC11_DBG_BMON0_1_BASE 0x75E7000ull
#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON0_1_SECTION 0x1000
#define mmNIC11_DBG_BMON1_1_BASE 0x75E8000ull
#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON1_1_SECTION 0x1000
#define mmNIC11_DBG_BMON2_1_BASE 0x75E9000ull
#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000
#define NIC11_DBG_BMON2_1_SECTION 0x7000
#define mmNIC11_DBG_ARC_RTT1_BASE 0x75F0000ull
#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400
#define NIC11_DBG_ARC_RTT1_SECTION 0x8000
#define mmNIC11_DBG_FUNNEL_TX_BASE 0x75F8000ull
#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000
#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000
#define mmNIC11_DBG_FUNNEL_NCH_BASE 0x75F9000ull
#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000

#endif /* GAUDI2_BLOCKS_LINUX_DRIVER_H_ */