/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_PDMA0_CORE_MASKS_H_
#define ASIC_REG_PDMA0_CORE_MASKS_H_

/*
 *****************************************
 *   PDMA0_CORE
 *   (Prototype: DMA_CORE)
 *****************************************
 */

/* PDMA0_CORE_CFG_0 */
#define PDMA0_CORE_CFG_0_EN_SHIFT 0
#define PDMA0_CORE_CFG_0_EN_MASK 0x1

/* PDMA0_CORE_CFG_1 */
#define PDMA0_CORE_CFG_1_HALT_SHIFT 0
#define PDMA0_CORE_CFG_1_HALT_MASK 0x1
#define PDMA0_CORE_CFG_1_FLUSH_SHIFT 1
#define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2

/* PDMA0_CORE_PROT */
#define PDMA0_CORE_PROT_VAL_SHIFT 0
#define PDMA0_CORE_PROT_VAL_MASK 0x1
#define PDMA0_CORE_PROT_ERR_VAL_SHIFT 1
#define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2

/* PDMA0_CORE_CKG */
#define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
#define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1
#define PDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2
#define PDMA0_CORE_CKG_TE_SHIFT 2
#define PDMA0_CORE_CKG_TE_MASK 0x4

/* PDMA0_CORE_RD_GLBL */
#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0
#define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
#define PDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
#define PDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20

/* PDMA0_CORE_RD_HBW_MAX_OUTSTAND */
#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
#define PDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF

/* PDMA0_CORE_RD_HBW_MAX_SIZE */
#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0
#define PDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16
#define PDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000

/* PDMA0_CORE_RD_HBW_ARCACHE */
#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0
#define PDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF

/* PDMA0_CORE_RD_HBW_INFLIGHTS */
#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0
#define PDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_RD_HBW_RATE_LIM_CFG */
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
#define PDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000

/* PDMA0_CORE_RD_LBW_MAX_OUTSTAND */
#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
#define PDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF

/* PDMA0_CORE_RD_LBW_MAX_SIZE */
#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0
#define PDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16
#define PDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000

/* PDMA0_CORE_RD_LBW_ARCACHE */
#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0
#define PDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF

/* PDMA0_CORE_RD_LBW_INFLIGHTS */
#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0
#define PDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_RD_LBW_RATE_LIM_CFG */
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31
#define PDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000

/* PDMA0_CORE_WR_HBW_MAX_OUTSTAND */
#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0
#define PDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF

/* PDMA0_CORE_WR_HBW_MAX_AWID */
#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0
#define PDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF

/* PDMA0_CORE_WR_HBW_AWCACHE */
#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0
#define PDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF

/* PDMA0_CORE_WR_HBW_INFLIGHTS */
#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0
#define PDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_WR_HBW_RATE_LIM_CFG */
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31
#define PDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000

/* PDMA0_CORE_WR_LBW_MAX_OUTSTAND */
#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0
#define PDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF

/* PDMA0_CORE_WR_LBW_MAX_AWID */
#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0
#define PDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F

/* PDMA0_CORE_WR_LBW_AWCACHE */
#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0
#define PDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF

/* PDMA0_CORE_WR_LBW_INFLIGHTS */
#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0
#define PDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_WR_LBW_RATE_LIM_CFG */
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31
#define PDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000

/* PDMA0_CORE_WR_COMP_MAX_OUTSTAND */
#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0
#define PDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F

/* PDMA0_CORE_WR_COMP_AWUSER */
#define PDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0
#define PDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_ERR_CFG */
#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0
#define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1
#define PDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2

/* PDMA0_CORE_ERR_CAUSE */
#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0
#define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1
#define PDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2
#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2
#define PDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4
#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3
#define PDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8
#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4
#define PDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10
#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5
#define PDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20
#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6
#define PDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40
#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7
#define PDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80

/* PDMA0_CORE_ERRMSG_ADDR_LO */
#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0
#define PDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_ERRMSG_ADDR_HI */
#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0
#define PDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_ERRMSG_WDATA */
#define PDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0
#define PDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS0 */
#define PDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0
#define PDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF
#define PDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16
#define PDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000
#define PDMA0_CORE_STS0_BUSY_SHIFT 31
#define PDMA0_CORE_STS0_BUSY_MASK 0x80000000

/* PDMA0_CORE_STS1 */
#define PDMA0_CORE_STS1_IS_HALT_SHIFT 0
#define PDMA0_CORE_STS1_IS_HALT_MASK 0x1

/* PDMA0_CORE_STS_RD_CTX_SEL */
#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7
#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8
#define PDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100

/* PDMA0_CORE_STS_RD_CTX_SIZE */
#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_RD_CTX_BASE_LO */
#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_RD_CTX_BASE_HI */
#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_RD_CTX_ID */
#define PDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF

/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */
#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */
#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_RD_LB_AXI_ADDR */
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31
#define PDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000

/* PDMA0_CORE_STS_WR_CTX_SEL */
#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7
#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8
#define PDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100

/* PDMA0_CORE_STS_WR_CTX_SIZE */
#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_WR_CTX_BASE_LO */
#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_WR_CTX_BASE_HI */
#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_WR_CTX_ID */
#define PDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000

/* PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31
#define PDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000

/* PDMA0_CORE_STS_WR_LB_AXI_ADDR */
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31
#define PDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000

/* PDMA0_CORE_PWRLP_CFG */
#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0
#define PDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1
#define PDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4
#define PDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10

/* PDMA0_CORE_PWRLP_STS */
#define PDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0
#define PDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F
#define PDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8
#define PDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00
#define PDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16
#define PDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000
#define PDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23
#define PDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000
#define PDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30
#define PDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000
#define PDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31
#define PDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000

/* PDMA0_CORE_DBG_DESC_CNT */
#define PDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0
#define PDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_DBG_STS */
#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0
#define PDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1
#define PDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2
#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2
#define PDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4
#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3
#define PDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8
#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4
#define PDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10
#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5
#define PDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20
#define PDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6
#define PDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40
#define PDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7
#define PDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80
#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8
#define PDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100
#define PDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9
#define PDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200
#define PDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10
#define PDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400
#define PDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11
#define PDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800

/* PDMA0_CORE_DBG_BUF_STS */
#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0
#define PDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF
#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16
#define PDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000

/* PDMA0_CORE_DBG_RD_DESC_ID */
#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0
#define PDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF

/* PDMA0_CORE_DBG_WR_DESC_ID */
#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0
#define PDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF

/* PDMA0_CORE_APB_DMA_LBW_BASE */
#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0
#define PDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF

/* PDMA0_CORE_APB_MSTR_IF_LBW_BASE */
#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0
#define PDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF

/* PDMA0_CORE_E2E_CRED_ASYNC_CFG */
#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0
#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF
#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9
#define PDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200

/* PDMA0_CORE_DBG_APB_ENABLER */
#define PDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0
#define PDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1

/* PDMA0_CORE_L2H_CMPR_LO */
#define PDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20
#define PDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000

/* PDMA0_CORE_L2H_CMPR_HI */
#define PDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0
#define PDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_L2H_MASK_LO */
#define PDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20
#define PDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000

/* PDMA0_CORE_L2H_MASK_HI */
#define PDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0
#define PDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF

/* PDMA0_CORE_IDLE_IND_MASK */
#define PDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0
#define PDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1
#define PDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1
#define PDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2
#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2
#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4
#define PDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3
#define PDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8
#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8
#define PDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00
#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16
#define PDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000
#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24
#define PDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000
#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25
#define PDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000

/* PDMA0_CORE_APB_ENABLER */
#define PDMA0_CORE_APB_ENABLER_DIS_SHIFT 0
#define PDMA0_CORE_APB_ENABLER_DIS_MASK 0x1

#endif /* ASIC_REG_PDMA0_CORE_MASKS_H_ */