drm/i915: Clean up PIPESRC defines
Use REG_GENMASK() & co. when dealing with PIPESRC.
Note that i9xx_get_initial_plane_config() will now use the
full 16 bit mask whereas previously it used 12 bits only.
But intel_get_pipe_src_size() already used the full 16 bits
on all platforms anyway, so at least we're consistent now.
The high bits beyond the max supported pipe source size
should not be set in any case so this seems fine.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 54f8776..a87b65c 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1054,8 +1054,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
plane_config->base = base;
val = intel_de_read(dev_priv, PIPESRC(pipe));
- fb->width = ((val >> 16) & 0xfff) + 1;
- fb->height = ((val >> 0) & 0xfff) + 1;
+ fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
+ fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
fb->pitches[0] = val & 0xffffffc0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e485dd0..2f2113b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3276,7 +3276,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
* always be the user's requested size.
*/
intel_de_write(dev_priv, PIPESRC(pipe),
- ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
+ PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
+ PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
}
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
@@ -3347,8 +3348,8 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
u32 tmp;
tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
- pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
- pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
+ pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
+ pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
}
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8494fd4..d0286cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3476,6 +3476,10 @@ enum {
#define _VSYNC_A 0x60014
#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
+#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
+#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
#define _PIPE_MULT_A 0x6002c
