// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * LogicTile Express 20MG
 * V2F-1XV7
 *
 * Cortex-A53 (2 cores) Soft Macrocell Model
 *
 * HBI-0247C
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2F-1XV7 Cortex-A53x2 SMM";
	arm,hbi = <0x247>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "serial0:38400n8";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0>;
			next-level-cache = <&L2_0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 1>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		smbclk: smclk {
			/* SMC clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <40000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "smclk";
		};

		volt-vio {
			/* VIO to expansion board above */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "VIO_UP";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		volt-12v {
			/* 12V from power connector J6 */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "12";
			regulator-always-on;
		};

		temp-fpga {
			/* FPGA temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "FPGA";
		};
	};

	smb: smb@8000000 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};
};