| commit | 6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 | [log] [tgz] |
|---|---|---|
| author | Joshua Yeong <joshua.yeong@starfivetech.com> | Thu Nov 16 18:53:12 2023 +0800 |
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | Wed Dec 27 15:37:11 2023 +0100 |
| tree | 80a620e91ca8a084954e4c99c014fcf28cd61252 | |
| parent | e0cf60151e6317c654c42ba0e8b1fb6ff477489a [diff] |
clocksource/timer-riscv: Add riscv_clock_shutdown callback Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when switching out riscv timer as clock source Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com