)]}'
{
  "commit": "6c56ccecf05fafe100ab4ea94f6fccbf5ff00db7",
  "tree": "c9d1f27a2fbb53251d2abeeab771b86d4122541a",
  "parents": [
    "4beb3d6d144c41525541cce2b611858b2645c725"
  ],
  "author": {
    "name": "Pallipadi, Venkatesh",
    "email": "venkatesh.pallipadi@intel.com",
    "time": "Thu Dec 17 12:27:02 2009 -0800"
  },
  "committer": {
    "name": "H. Peter Anvin",
    "email": "hpa@zytor.com",
    "time": "Thu Dec 17 14:44:35 2009 -0800"
  },
  "message": "x86: Reenable TSC sync check at boot, even with NONSTOP_TSC\n\nCommit 83ce4009 did the following change\nIf the TSC is constant and non-stop, also set it reliable.\n\nBut, there seems to be few systems that will end up with TSC warp across\nsockets, depending on how the cpus come out of reset. Skipping TSC sync\ntest on such systems may result in time inconsistency later.\n\nSo, reenable TSC sync test even on constant and non-stop TSC systems.\nSet, sched_clock_stable to 1 by default and reset it in\nmark_tsc_unstable, if TSC sync fails.\n\nThis change still gives perf benefit mentioned in 83ce4009 for systems\nwhere TSC is reliable.\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nAcked-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nLKML-Reference: \u003c20091217202702.GA18015@linux-os.sc.intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9c31e8b09d2c2676c29f87a68442e56878d6bece",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/cpu/intel.c",
      "new_id": "879666f4d871c99a312169bd30aad71049713572",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/cpu/intel.c"
    },
    {
      "type": "modify",
      "old_id": "cd982f48e23e11c74acd08e8db823c3ef4fe5886",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/tsc.c",
      "new_id": "597683aa5ba0ba3ef800ab39179669ded4e3aa57",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/tsc.c"
    }
  ]
}