tree a20e91cefa04a6c9bf78ac5027958fca23c5b6ae
parent 747e1f60470b975363cbbfcde0c41a3166391be5
author Zachary Zhang <zhangzg@marvell.com> 1505319699 +0200
committer Mark Brown <broonie@kernel.org> 1505320669 -0700

spi: armada-3700: Fix padding when sending not 4-byte aligned data

In 4-byte transfer mode, extra padding/dummy bytes '0xff' would be
sent in write operation if TX data is not 4-byte aligned since the
SPI data register is always shifted out as whole 4 bytes.

Fix this by using the header count feature that allows to transfer 0 to
4 bytes. Use it to actually send the first 1 to 3 bytes of data before
the rest of the buffer that will hence be 4-byte aligned.

Signed-off-by: Zachary Zhang <zhangzg@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>