| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2018-2019 NXP |
| * Dong Aisheng <aisheng.dong@nxp.com> |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8qm.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QM MEK"; |
| compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; |
| |
| chosen { |
| stdout-path = &lpuart0; |
| }; |
| |
| cpus { |
| /delete-node/ cpu-map; |
| /delete-node/ cpu@100; |
| /delete-node/ cpu@101; |
| }; |
| |
| thermal-zones { |
| /delete-node/ cpu1-thermal; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x00000000 0x80000000 0 0x40000000>; |
| }; |
| |
| reg_usdhc2_vmmc: usdhc2-vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD1_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &lpuart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart0>; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| no-sd; |
| no-sdio; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| bus-width = <4>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 |
| IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 |
| IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 |
| IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 |
| IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 |
| IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 |
| IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 |
| IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 |
| IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 |
| IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 |
| IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 |
| IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 |
| IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 |
| IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 |
| >; |
| }; |
| |
| pinctrl_lpuart0: lpuart0grp { |
| fsl,pins = < |
| IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 |
| IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| }; |
