arch/arm/mach-omap2/prm2xxx_3xxx.h - linux - Git at Google

 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
  *
  * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  * Paul Walmsley
  *
  * The PRM hardware modules on the OMAP2/3 are quite similar to each
  * other.  The PRM on OMAP4 has a new register layout, and is handled
  * in a separate file.
  */
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H

 #include "prcm-common.h"
 #include "prm.h"

 /*
  * Module specific PRM register offsets from PRM_BASE + domain offset
  *
  * Use prm_{read,write}_mod_reg() with these registers.
  *
  * With a few exceptions, these are the register names beginning with
  * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
  * IRQSTATUS and IRQENABLE bits.)
  */

 /* Register offsets appearing on both OMAP2 and OMAP3 */

 #define OMAP2_RM_RSTCTRL				0x0050
 #define OMAP2_RM_RSTTIME				0x0054
 #define OMAP2_RM_RSTST					0x0058
 #define OMAP2_PM_PWSTCTRL				0x00e0
 #define OMAP2_PM_PWSTST					0x00e4

 #define PM_WKEN						0x00a0
 #define PM_WKEN1					PM_WKEN
 #define PM_WKST						0x00b0
 #define PM_WKST1					PM_WKST
 #define PM_WKDEP					0x00c8
 #define PM_EVGENCTRL					0x00d4
 #define PM_EVGENONTIM					0x00d8
 #define PM_EVGENOFFTIM					0x00dc


 #ifndef __ASSEMBLER__

 #include <linux/io.h>
 #include "powerdomain.h"

 /* Power/reset management domain register get/set */
 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
 	return readl_relaxed(prm_base.va + module + idx);
 }

 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
 	writel_relaxed(val, prm_base.va + module + idx);
 }

 /* Read-modify-write a register in a PRM module. Caller must lock */
 static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
 					     s16 idx)
 {
 	u32 v;

 	v = omap2_prm_read_mod_reg(module, idx);
 	v &= ~mask;
 	v |= bits;
 	omap2_prm_write_mod_reg(v, module, idx);

 	return v;
 }

 /* Read a PRM register, AND it, and shift the result down to bit 0 */
 static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 {
 	u32 v;

 	v = omap2_prm_read_mod_reg(domain, idx);
 	v &= mask;
 	v >>= __ffs(mask);

 	return v;
 }

 static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
 	return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
 }

 static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
 	return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }

 /* These omap2_ PRM functions apply to both OMAP2 and 3 */
 int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
 int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
 			       u16 offset);
 int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
 				 s16 prm_mod, u16 reset_offset,
 				 u16 st_offset);

 extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
 extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
 extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
 extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 				    u8 pwrst);
 extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 				     u8 pwrst);
 extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
 extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
 extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
 extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);

 extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
 				 struct clockdomain *clkdm2);
 extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
 				 struct clockdomain *clkdm2);
 extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
 				  struct clockdomain *clkdm2);
 extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);

 #endif /* __ASSEMBLER */

 /*
  * Bits common to specific registers
  *
  * The 3430 register and bit names are generally used,
  * since they tend to make more sense
  */

 /* PM_EVGENONTIM_MPU */
 /* Named PM_EVEGENONTIM_MPU on the 24XX */
 #define OMAP_ONTIMEVAL_SHIFT				0
 #define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)

 /* PM_EVGENOFFTIM_MPU */
 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
 #define OMAP_OFFTIMEVAL_SHIFT				0
 #define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)

 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
 /* Named PRCM_CLKSSETUP on the 24XX */
 #define OMAP_SETUP_TIME_SHIFT				0
 #define OMAP_SETUP_TIME_MASK				(0xffff << 0)

 /* PRM_CLKSRC_CTRL */
 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 #define OMAP_SYSCLKDIV_SHIFT				6
 #define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
 #define OMAP_SYSCLKDIV_WIDTH				2
 #define OMAP_AUTOEXTCLKMODE_SHIFT			3
 #define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
 #define OMAP_SYSCLKSEL_SHIFT				0
 #define OMAP_SYSCLKSEL_MASK				(0x3 << 0)

 /* PM_EVGENCTRL_MPU */
 #define OMAP_OFFLOADMODE_SHIFT				3
 #define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
 #define OMAP_ONLOADMODE_SHIFT				1
 #define OMAP_ONLOADMODE_MASK				(0x3 << 1)
 #define OMAP_ENABLE_MASK				(1 << 0)

 /* PRM_RSTTIME */
 /* Named RM_RSTTIME_WKUP on the 24xx */
 #define OMAP_RSTTIME2_SHIFT				8
 #define OMAP_RSTTIME2_MASK				(0x1f << 8)
 #define OMAP_RSTTIME1_SHIFT				0
 #define OMAP_RSTTIME1_MASK				(0xff << 0)

 /* PRM_RSTCTRL */
 /* Named RM_RSTCTRL_WKUP on the 24xx */
 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 #define OMAP_RST_DPLL3_MASK				(1 << 2)
 #define OMAP_RST_GS_MASK				(1 << 1)


 /*
  * Bits common to module-shared registers
  *
  * Not all registers of a particular type support all of these bits -
  * check TRM if you are unsure
  */

 /*
  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
  *	 called 'COREWKUP_RST'
  *
  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
  *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
  */
 #define OMAP_COREDOMAINWKUP_RST_MASK			(1 << 3)

 /*
  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
  *
  * 2430: RM_RSTST_MDM
  *
  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
  */
 #define OMAP_DOMAINWKUP_RST_MASK			(1 << 2)

 /*
  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
  *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
  *
  * 2430: RM_RSTST_MDM
  *
  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
  */
 #define OMAP_GLOBALWARM_RST_SHIFT			1
 #define OMAP_GLOBALWARM_RST_MASK			(1 << 1)
 #define OMAP_GLOBALCOLD_RST_SHIFT			0
 #define OMAP_GLOBALCOLD_RST_MASK			(1 << 0)

 /*
  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
  *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
  *
  * 2430: PM_WKDEP_MDM
  *
  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
  *	 PM_WKDEP_PER
  */
 #define OMAP_EN_WKUP_SHIFT				4
 #define OMAP_EN_WKUP_MASK				(1 << 4)

 /*
  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
  *	 PM_PWSTCTRL_DSP
  *
  * 2430: PM_PWSTCTRL_MDM
  *
  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
  *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
  *	 PM_PWSTCTRL_NEON
  */
 #define OMAP_LOGICRETSTATE_MASK				(1 << 2)


 #endif
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
	*
	* Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
	* Copyright (C) 2008-2010 Nokia Corporation
	* Paul Walmsley
	*
	* The PRM hardware modules on the OMAP2/3 are quite similar to each
	* other. The PRM on OMAP4 has a new register layout, and is handled
	* in a separate file.
	*/
	#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
	#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H

	#include "prcm-common.h"
	#include "prm.h"

	/*
	* Module specific PRM register offsets from PRM_BASE + domain offset
	*
	* Use prm_{read,write}_mod_reg() with these registers.
	*
	* With a few exceptions, these are the register names beginning with
	* {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
	* IRQSTATUS and IRQENABLE bits.)
	*/

	/* Register offsets appearing on both OMAP2 and OMAP3 */

	#define OMAP2_RM_RSTCTRL 0x0050
	#define OMAP2_RM_RSTTIME 0x0054
	#define OMAP2_RM_RSTST 0x0058
	#define OMAP2_PM_PWSTCTRL 0x00e0
	#define OMAP2_PM_PWSTST 0x00e4

	#define PM_WKEN 0x00a0
	#define PM_WKEN1 PM_WKEN
	#define PM_WKST 0x00b0
	#define PM_WKST1 PM_WKST
	#define PM_WKDEP 0x00c8
	#define PM_EVGENCTRL 0x00d4
	#define PM_EVGENONTIM 0x00d8
	#define PM_EVGENOFFTIM 0x00dc


	#ifndef __ASSEMBLER__

	#include <linux/io.h>
	#include "powerdomain.h"

	/* Power/reset management domain register get/set */
	static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
	{
	return readl_relaxed(prm_base.va + module + idx);
	}

	static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
	{
	writel_relaxed(val, prm_base.va + module + idx);
	}

	/* Read-modify-write a register in a PRM module. Caller must lock */
	static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
	s16 idx)
	{
	u32 v;

	v = omap2_prm_read_mod_reg(module, idx);
	v &= ~mask;
	v \|= bits;
	omap2_prm_write_mod_reg(v, module, idx);

	return v;
	}

	/* Read a PRM register, AND it, and shift the result down to bit 0 */
	static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
	{
	u32 v;

	v = omap2_prm_read_mod_reg(domain, idx);
	v &= mask;
	v >>= __ffs(mask);

	return v;
	}

	static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
	{
	return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
	}

	static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
	{
	return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
	}

	/* These omap2_ PRM functions apply to both OMAP2 and 3 */
	int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
	int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
	u16 offset);
	int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
	s16 prm_mod, u16 reset_offset,
	u16 st_offset);

	extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
	extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
	extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
	extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
	u8 pwrst);
	extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
	u8 pwrst);
	extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
	extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
	extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
	extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);

	extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
	struct clockdomain *clkdm2);
	extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
	struct clockdomain *clkdm2);
	extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
	struct clockdomain *clkdm2);
	extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);

	#endif /* __ASSEMBLER */

	/*
	* Bits common to specific registers
	*
	* The 3430 register and bit names are generally used,
	* since they tend to make more sense
	*/

	/* PM_EVGENONTIM_MPU */
	/* Named PM_EVEGENONTIM_MPU on the 24XX */
	#define OMAP_ONTIMEVAL_SHIFT 0
	#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)

	/* PM_EVGENOFFTIM_MPU */
	/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
	#define OMAP_OFFTIMEVAL_SHIFT 0
	#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)

	/* PRM_CLKSETUP and PRCM_VOLTSETUP */
	/* Named PRCM_CLKSSETUP on the 24XX */
	#define OMAP_SETUP_TIME_SHIFT 0
	#define OMAP_SETUP_TIME_MASK (0xffff << 0)

	/* PRM_CLKSRC_CTRL */
	/* Named PRCM_CLKSRC_CTRL on the 24XX */
	#define OMAP_SYSCLKDIV_SHIFT 6
	#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
	#define OMAP_SYSCLKDIV_WIDTH 2
	#define OMAP_AUTOEXTCLKMODE_SHIFT 3
	#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
	#define OMAP_SYSCLKSEL_SHIFT 0
	#define OMAP_SYSCLKSEL_MASK (0x3 << 0)

	/* PM_EVGENCTRL_MPU */
	#define OMAP_OFFLOADMODE_SHIFT 3
	#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
	#define OMAP_ONLOADMODE_SHIFT 1
	#define OMAP_ONLOADMODE_MASK (0x3 << 1)
	#define OMAP_ENABLE_MASK (1 << 0)

	/* PRM_RSTTIME */
	/* Named RM_RSTTIME_WKUP on the 24xx */
	#define OMAP_RSTTIME2_SHIFT 8
	#define OMAP_RSTTIME2_MASK (0x1f << 8)
	#define OMAP_RSTTIME1_SHIFT 0
	#define OMAP_RSTTIME1_MASK (0xff << 0)

	/* PRM_RSTCTRL */
	/* Named RM_RSTCTRL_WKUP on the 24xx */
	/* 2420 calls RST_DPLL3 'RST_DPLL' */
	#define OMAP_RST_DPLL3_MASK (1 << 2)
	#define OMAP_RST_GS_MASK (1 << 1)


	/*
	* Bits common to module-shared registers
	*
	* Not all registers of a particular type support all of these bits -
	* check TRM if you are unsure
	*/

	/*
	* 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
	* called 'COREWKUP_RST'
	*
	* 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
	* RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
	*/
	#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)

	/*
	* 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
	*
	* 2430: RM_RSTST_MDM
	*
	* 3430: RM_RSTST_CORE, RM_RSTST_EMU
	*/
	#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)

	/*
	* 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
	* On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
	*
	* 2430: RM_RSTST_MDM
	*
	* 3430: RM_RSTST_CORE, RM_RSTST_EMU
	*/
	#define OMAP_GLOBALWARM_RST_SHIFT 1
	#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
	#define OMAP_GLOBALCOLD_RST_SHIFT 0
	#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)

	/*
	* 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
	* 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
	*
	* 2430: PM_WKDEP_MDM
	*
	* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
	* PM_WKDEP_PER
	*/
	#define OMAP_EN_WKUP_SHIFT 4
	#define OMAP_EN_WKUP_MASK (1 << 4)

	/*
	* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
	* PM_PWSTCTRL_DSP
	*
	* 2430: PM_PWSTCTRL_MDM
	*
	* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
	* PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
	* PM_PWSTCTRL_NEON
	*/
	#define OMAP_LOGICRETSTATE_MASK (1 << 2)


	#endif