Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A1 Interrupt Controller

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
  RZ/A2 SoCs:
    - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
    - NMI edge select.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r7s72100-irqc # RZ/A1H
          - renesas,r7s9210-irqc  # RZ/A2M
      - const: renesas,rza1-irqc

  '#interrupt-cells':
    const: 2

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupt-map:
    maxItems: 8
    description: Specifies the mapping from external interrupts to GIC interrupts.

  interrupt-map-mask:
    items:
      - const: 7
      - const: 0

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg
  - interrupt-map
  - interrupt-map-mask

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    irqc: interrupt-controller@fcfef800 {
            compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
            #interrupt-cells = <2>;
            #address-cells = <0>;
            interrupt-controller;
            reg = <0xfcfef800 0x6>;
            interrupt-map =
                    <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                    <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                    <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                    <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                    <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                    <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                    <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                    <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-map-mask = <7 0>;
    };