| /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #ifndef _I915_REG_H_ |
| #define _I915_REG_H_ |
| |
| #include <linux/bitfield.h> |
| #include <linux/bits.h> |
| |
| /** |
| * DOC: The i915 register macro definition style guide |
| * |
| * Follow the style described here for new macros, and while changing existing |
| * macros. Do **not** mass change existing definitions just to update the style. |
| * |
| * File Layout |
| * ~~~~~~~~~~~ |
| * |
| * Keep helper macros near the top. For example, _PIPE() and friends. |
| * |
| * Prefix macros that generally should not be used outside of this file with |
| * underscore '_'. For example, _PIPE() and friends, single instances of |
| * registers that are defined solely for the use by function-like macros. |
| * |
| * Avoid using the underscore prefixed macros outside of this file. There are |
| * exceptions, but keep them to a minimum. |
| * |
| * There are two basic types of register definitions: Single registers and |
| * register groups. Register groups are registers which have two or more |
| * instances, for example one per pipe, port, transcoder, etc. Register groups |
| * should be defined using function-like macros. |
| * |
| * For single registers, define the register offset first, followed by register |
| * contents. |
| * |
| * For register groups, define the register instance offsets first, prefixed |
| * with underscore, followed by a function-like macro choosing the right |
| * instance based on the parameter, followed by register contents. |
| * |
| * Define the register contents (i.e. bit and bit field macros) from most |
| * significant to least significant bit. Indent the register content macros |
| * using two extra spaces between ``#define`` and the macro name. |
| * |
| * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents |
| * using ``REG_FIELD_PREP(mask, value)``. This will define the values already |
| * shifted in place, so they can be directly OR'd together. For convenience, |
| * function-like macros may be used to define bit fields, but do note that the |
| * macros may be needed to read as well as write the register contents. |
| * |
| * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. |
| * |
| * Group the register and its contents together without blank lines, separate |
| * from other registers and their contents with one blank line. |
| * |
| * Indent macro values from macro names using TABs. Align values vertically. Use |
| * braces in macro values as needed to avoid unintended precedence after macro |
| * substitution. Use spaces in macro values according to kernel coding |
| * style. Use lower case in hexadecimal values. |
| * |
| * Naming |
| * ~~~~~~ |
| * |
| * Try to name registers according to the specs. If the register name changes in |
| * the specs from platform to another, stick to the original name. |
| * |
| * Try to re-use existing register macro definitions. Only add new macros for |
| * new register offsets, or when the register contents have changed enough to |
| * warrant a full redefinition. |
| * |
| * When a register macro changes for a new platform, prefix the new macro using |
| * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The |
| * prefix signifies the start platform/generation using the register. |
| * |
| * When a bit (field) macro changes or gets added for a new platform, while |
| * retaining the existing register macro, add a platform acronym or generation |
| * suffix to the name. For example, ``_SKL`` or ``_GEN8``. |
| * |
| * Examples |
| * ~~~~~~~~ |
| * |
| * (Note that the values in the example are indented using spaces instead of |
| * TABs to avoid misalignment in generated documentation. Use TABs in the |
| * definitions.):: |
| * |
| * #define _FOO_A 0xf000 |
| * #define _FOO_B 0xf001 |
| * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) |
| * #define FOO_ENABLE REG_BIT(31) |
| * #define FOO_MODE_MASK REG_GENMASK(19, 16) |
| * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) |
| * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) |
| * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) |
| * |
| * #define BAR _MMIO(0xb000) |
| * #define GEN8_BAR _MMIO(0xb888) |
| */ |
| |
| /** |
| * REG_BIT() - Prepare a u32 bit value |
| * @__n: 0-based bit number |
| * |
| * Local wrapper for BIT() to force u32, with compile time checks. |
| * |
| * @return: Value with bit @__n set. |
| */ |
| #define REG_BIT(__n) \ |
| ((u32)(BIT(__n) + \ |
| BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ |
| ((__n) < 0 || (__n) > 31)))) |
| |
| /** |
| * REG_GENMASK() - Prepare a continuous u32 bitmask |
| * @__high: 0-based high bit |
| * @__low: 0-based low bit |
| * |
| * Local wrapper for GENMASK() to force u32, with compile time checks. |
| * |
| * @return: Continuous bitmask from @__high to @__low, inclusive. |
| */ |
| #define REG_GENMASK(__high, __low) \ |
| ((u32)(GENMASK(__high, __low) + \ |
| BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ |
| __is_constexpr(__low) && \ |
| ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) |
| |
| /* |
| * Local integer constant expression version of is_power_of_2(). |
| */ |
| #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) |
| |
| /** |
| * REG_FIELD_PREP() - Prepare a u32 bitfield value |
| * @__mask: shifted mask defining the field's length and position |
| * @__val: value to put in the field |
| * |
| * Local copy of FIELD_PREP() to generate an integer constant expression, force |
| * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). |
| * |
| * @return: @__val masked and shifted into the field defined by @__mask. |
| */ |
| #define REG_FIELD_PREP(__mask, __val) \ |
| ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ |
| BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ |
| BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ |
| BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ |
| BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) |
| |
| /** |
| * REG_FIELD_GET() - Extract a u32 bitfield value |
| * @__mask: shifted mask defining the field's length and position |
| * @__val: value to extract the bitfield value from |
| * |
| * Local wrapper for FIELD_GET() to force u32 and for consistency with |
| * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). |
| * |
| * @return: Masked and shifted value of the field defined by @__mask in @__val. |
| */ |
| #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) |
| |
| typedef struct { |
| u32 reg; |
| } i915_reg_t; |
| |
| #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) |
| |
| #define INVALID_MMIO_REG _MMIO(0) |
| |
| static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) |
| { |
| return reg.reg; |
| } |
| |
| static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) |
| { |
| return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); |
| } |
| |
| static inline bool i915_mmio_reg_valid(i915_reg_t reg) |
| { |
| return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); |
| } |
| |
| #define VLV_DISPLAY_BASE 0x180000 |
| #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
| #define BXT_MIPI_BASE 0x60000 |
| |
| #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) |
| |
| /* |
| * Given the first two numbers __a and __b of arbitrarily many evenly spaced |
| * numbers, pick the 0-based __index'th value. |
| * |
| * Always prefer this over _PICK() if the numbers are evenly spaced. |
| */ |
| #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) |
| |
| /* |
| * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. |
| * |
| * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. |
| */ |
| #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) |
| |
| /* |
| * Named helper wrappers around _PICK_EVEN() and _PICK(). |
| */ |
| #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) |
| #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) |
| #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) |
| #define _PORT(port, a, b) _PICK_EVEN(port, a, b) |
| #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) |
| #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) |
| |
| #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) |
| #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) |
| #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) |
| #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) |
| #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) |
| #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) |
| |
| #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) |
| |
| #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) |
| #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) |
| #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) |
| #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) |
| |
| |
| /* |
| * Device info offset array based helpers for groups of registers with unevenly |
| * spaced base offsets. |
| */ |
| #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ |
| INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ |
| DISPLAY_MMIO_BASE(dev_priv)) |
| #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ |
| INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ |
| DISPLAY_MMIO_BASE(dev_priv)) |
| #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) |
| #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ |
| INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ |
| DISPLAY_MMIO_BASE(dev_priv)) |
| |
| #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) |
| #define _MASKED_FIELD(mask, value) ({ \ |
| if (__builtin_constant_p(mask)) \ |
| BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ |
| if (__builtin_constant_p(value)) \ |
| BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ |
| if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ |
| BUILD_BUG_ON_MSG((value) & ~(mask), \ |
| "Incorrect value for mask"); \ |
| __MASKED_FIELD(mask, value); }) |
| #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) |
| #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) |
| |
| /* PCI config space */ |
| |
| #define MCHBAR_I915 0x44 |
| #define MCHBAR_I965 0x48 |
| #define MCHBAR_SIZE (4 * 4096) |
| |
| #define DEVEN 0x54 |
| #define DEVEN_MCHBAR_EN (1 << 28) |
| |
| /* BSM in include/drm/i915_drm.h */ |
| |
| #define HPLLCC 0xc0 /* 85x only */ |
| #define GC_CLOCK_CONTROL_MASK (0x7 << 0) |
| #define GC_CLOCK_133_200 (0 << 0) |
| #define GC_CLOCK_100_200 (1 << 0) |
| #define GC_CLOCK_100_133 (2 << 0) |
| #define GC_CLOCK_133_266 (3 << 0) |
| #define GC_CLOCK_133_200_2 (4 << 0) |
| #define GC_CLOCK_133_266_2 (5 << 0) |
| #define GC_CLOCK_166_266 (6 << 0) |
| #define GC_CLOCK_166_250 (7 << 0) |
| |
| #define I915_GDRST 0xc0 /* PCI config register */ |
| #define GRDOM_FULL (0 << 2) |
| #define GRDOM_RENDER (1 << 2) |
| #define GRDOM_MEDIA (3 << 2) |
| #define GRDOM_MASK (3 << 2) |
| #define GRDOM_RESET_STATUS (1 << 1) |
| #define GRDOM_RESET_ENABLE (1 << 0) |
| |
| /* BSpec only has register offset, PCI device and bit found empirically */ |
| #define I830_CLOCK_GATE 0xc8 /* device 0 */ |
| #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) |
| |
| #define GCDGMBUS 0xcc |
| |
| #define GCFGC2 0xda |
| #define GCFGC 0xf0 /* 915+ only */ |
| #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
| #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
| #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) |
| #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
| #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) |
| #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) |
| #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) |
| #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) |
| #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) |
| #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
| #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
| #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
| #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
| #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
| #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
| #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
| #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
| #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
| #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
| #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
| #define I945_GC_RENDER_CLOCK_MASK (7 << 0) |
| #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
| #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
| #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
| #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
| #define I915_GC_RENDER_CLOCK_MASK (7 << 0) |
| #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
| #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
| #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
| |
| #define ASLE 0xe4 |
| #define ASLS 0xfc |
| |
| #define SWSCI 0xe8 |
| #define SWSCI_SCISEL (1 << 15) |
| #define SWSCI_GSSCIE (1 << 0) |
| |
| #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
| |
| |
| #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) |
| #define ILK_GRDOM_FULL (0 << 1) |
| #define ILK_GRDOM_RENDER (1 << 1) |
| #define ILK_GRDOM_MEDIA (3 << 1) |
| #define ILK_GRDOM_MASK (3 << 1) |
| #define ILK_GRDOM_RESET_ENABLE (1 << 0) |
| |
| #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ |
| #define GEN6_MBC_SNPCR_SHIFT 21 |
| #define GEN6_MBC_SNPCR_MASK (3 << 21) |
| #define GEN6_MBC_SNPCR_MAX (0 << 21) |
| #define GEN6_MBC_SNPCR_MED (1 << 21) |
| #define GEN6_MBC_SNPCR_LOW (2 << 21) |
| #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ |
| |
| #define VLV_G3DCTL _MMIO(0x9024) |
| #define VLV_GSCKGCTL _MMIO(0x9028) |
| |
| #define GEN6_MBCTL _MMIO(0x0907c) |
| #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) |
| #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) |
| #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) |
| #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) |
| #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) |
| |
| #define GEN6_GDRST _MMIO(0x941c) |
| #define GEN6_GRDOM_FULL (1 << 0) |
| #define GEN6_GRDOM_RENDER (1 << 1) |
| #define GEN6_GRDOM_MEDIA (1 << 2) |
| #define GEN6_GRDOM_BLT (1 << 3) |
| #define GEN6_GRDOM_VECS (1 << 4) |
| #define GEN9_GRDOM_GUC (1 << 5) |
| #define GEN8_GRDOM_MEDIA2 (1 << 7) |
| /* GEN11 changed all bit defs except for FULL & RENDER */ |
| #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL |
| #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER |
| #define GEN11_GRDOM_BLT (1 << 2) |
| #define GEN11_GRDOM_GUC (1 << 3) |
| #define GEN11_GRDOM_MEDIA (1 << 5) |
| #define GEN11_GRDOM_MEDIA2 (1 << 6) |
| #define GEN11_GRDOM_MEDIA3 (1 << 7) |
| #define GEN11_GRDOM_MEDIA4 (1 << 8) |
| #define GEN11_GRDOM_MEDIA5 (1 << 9) |
| #define GEN11_GRDOM_MEDIA6 (1 << 10) |
| #define GEN11_GRDOM_MEDIA7 (1 << 11) |
| #define GEN11_GRDOM_MEDIA8 (1 << 12) |
| #define GEN11_GRDOM_VECS (1 << 13) |
| #define GEN11_GRDOM_VECS2 (1 << 14) |
| #define GEN11_GRDOM_VECS3 (1 << 15) |
| #define GEN11_GRDOM_VECS4 (1 << 16) |
| #define GEN11_GRDOM_SFC0 (1 << 17) |
| #define GEN11_GRDOM_SFC1 (1 << 18) |
| #define GEN11_GRDOM_SFC2 (1 << 19) |
| #define GEN11_GRDOM_SFC3 (1 << 20) |
| |
| #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) |
| #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) |
| |
| #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) |
| #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) |
| #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) |
| #define GEN11_VCS_SFC_USAGE_BIT (1 << 0) |
| #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) |
| |
| #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) |
| #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) |
| #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) |
| #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) |
| #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) |
| #define GEN11_VECS_SFC_USAGE_BIT (1 << 0) |
| |
| #define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910) |
| #define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0) |
| #define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914) |
| #define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1) |
| #define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0) |
| |
| #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) |
| #define GEN12_SFC_DONE_MAX 4 |
| |
| #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) |
| #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) |
| #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) |
| #define PP_DIR_DCLV_2G 0xffffffff |
| |
| #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) |
| #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) |
| |
| #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) |
| #define GEN8_RPCS_ENABLE (1 << 31) |
| #define GEN8_RPCS_S_CNT_ENABLE (1 << 18) |
| #define GEN8_RPCS_S_CNT_SHIFT 15 |
| #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) |
| #define GEN11_RPCS_S_CNT_SHIFT 12 |
| #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) |
| #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) |
| #define GEN8_RPCS_SS_CNT_SHIFT 8 |
| #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) |
| #define GEN8_RPCS_EU_MAX_SHIFT 4 |
| #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) |
| #define GEN8_RPCS_EU_MIN_SHIFT 0 |
| #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) |
| |
| #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) |
| /* HSW only */ |
| #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 |
| #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) |
| #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 |
| #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) |
| /* HSW+ */ |
| #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) |
| #define HSW_RCS_CONTEXT_ENABLE (1 << 7) |
| #define HSW_RCS_INHIBIT (1 << 8) |
| /* Gen8 */ |
| #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 |
| #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) |
| #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 |
| #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) |
| #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) |
| #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 |
| #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) |
| #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 |
| #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) |
| #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) |
| |
| #define GAM_ECOCHK _MMIO(0x4090) |
| #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) |
| #define ECOCHK_SNB_BIT (1 << 10) |
| #define ECOCHK_DIS_TLB (1 << 8) |
| #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) |
| #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) |
| #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) |
| #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) |
| #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) |
| #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) |
| #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) |
| #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) |
| |
| #define GEN8_RC6_CTX_INFO _MMIO(0x8504) |
| |
| #define GAC_ECO_BITS _MMIO(0x14090) |
| #define ECOBITS_SNB_BIT (1 << 13) |
| #define ECOBITS_PPGTT_CACHE64B (3 << 8) |
| #define ECOBITS_PPGTT_CACHE4B (0 << 8) |
| |
| #define GAB_CTL _MMIO(0x24000) |
| #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) |
| |
| #define GU_CNTL _MMIO(0x101010) |
| #define LMEM_INIT REG_BIT(7) |
| |
| #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) |
| #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) |
| #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) |
| #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) |
| #define GEN6_STOLEN_RESERVED_1M (0 << 4) |
| #define GEN6_STOLEN_RESERVED_512K (1 << 4) |
| #define GEN6_STOLEN_RESERVED_256K (2 << 4) |
| #define GEN6_STOLEN_RESERVED_128K (3 << 4) |
| #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) |
| #define GEN7_STOLEN_RESERVED_1M (0 << 5) |
| #define GEN7_STOLEN_RESERVED_256K (1 << 5) |
| #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) |
| #define GEN8_STOLEN_RESERVED_1M (0 << 7) |
| #define GEN8_STOLEN_RESERVED_2M (1 << 7) |
| #define GEN8_STOLEN_RESERVED_4M (2 << 7) |
| #define GEN8_STOLEN_RESERVED_8M (3 << 7) |
| #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) |
| #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) |
| |
| /* VGA stuff */ |
| |
| #define VGA_ST01_MDA 0x3ba |
| #define VGA_ST01_CGA 0x3da |
| |
| #define _VGA_MSR_WRITE _MMIO(0x3c2) |
| #define VGA_MSR_WRITE 0x3c2 |
| #define VGA_MSR_READ 0x3cc |
| #define VGA_MSR_MEM_EN (1 << 1) |
| #define VGA_MSR_CGA_MODE (1 << 0) |
| |
| #define VGA_SR_INDEX 0x3c4 |
| #define SR01 1 |
| #define VGA_SR_DATA 0x3c5 |
| |
| #define VGA_AR_INDEX 0x3c0 |
| #define VGA_AR_VID_EN (1 << 5) |
| #define VGA_AR_DATA_WRITE 0x3c0 |
| #define VGA_AR_DATA_READ 0x3c1 |
| |
| #define VGA_GR_INDEX 0x3ce |
| #define VGA_GR_DATA 0x3cf |
| /* GR05 */ |
| #define VGA_GR_MEM_READ_MODE_SHIFT 3 |
| #define VGA_GR_MEM_READ_MODE_PLANE 1 |
| /* GR06 */ |
| #define VGA_GR_MEM_MODE_MASK 0xc |
| #define VGA_GR_MEM_MODE_SHIFT 2 |
| #define VGA_GR_MEM_A0000_AFFFF 0 |
| #define VGA_GR_MEM_A0000_BFFFF 1 |
| #define VGA_GR_MEM_B0000_B7FFF 2 |
| #define VGA_GR_MEM_B0000_BFFFF 3 |
| |
| #define VGA_DACMASK 0x3c6 |
| #define VGA_DACRX 0x3c7 |
| #define VGA_DACWX 0x3c8 |
| #define VGA_DACDATA 0x3c9 |
| |
| #define VGA_CR_INDEX_MDA 0x3b4 |
| #define VGA_CR_DATA_MDA 0x3b5 |
| #define VGA_CR_INDEX_CGA 0x3d4 |
| #define VGA_CR_DATA_CGA 0x3d5 |
| |
| #define MI_PREDICATE_SRC0 _MMIO(0x2400) |
| #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) |
| #define MI_PREDICATE_SRC1 _MMIO(0x2408) |
| #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) |
| #define MI_PREDICATE_DATA _MMIO(0x2410) |
| #define MI_PREDICATE_RESULT _MMIO(0x2418) |
| #define MI_PREDICATE_RESULT_1 _MMIO(0x241c) |
| #define MI_PREDICATE_RESULT_2 _MMIO(0x2214) |
| #define LOWER_SLICE_ENABLED (1 << 0) |
| #define LOWER_SLICE_DISABLED (0 << 0) |
| |
| /* |
| * Registers used only by the command parser |
| */ |
| #define BCS_SWCTRL _MMIO(0x22200) |
| #define BCS_SRC_Y REG_BIT(0) |
| #define BCS_DST_Y REG_BIT(1) |
| |
| /* There are 16 GPR registers */ |
| #define BCS_GPR(n) _MMIO(0x22600 + (n) * 8) |
| #define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4) |
| |
| #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) |
| #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) |
| #define HS_INVOCATION_COUNT _MMIO(0x2300) |
| #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) |
| #define DS_INVOCATION_COUNT _MMIO(0x2308) |
| #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) |
| #define IA_VERTICES_COUNT _MMIO(0x2310) |
| #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) |
| #define IA_PRIMITIVES_COUNT _MMIO(0x2318) |
| #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) |
| #define VS_INVOCATION_COUNT _MMIO(0x2320) |
| #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) |
| #define GS_INVOCATION_COUNT _MMIO(0x2328) |
| #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) |
| #define GS_PRIMITIVES_COUNT _MMIO(0x2330) |
| #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) |
| #define CL_INVOCATION_COUNT _MMIO(0x2338) |
| #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) |
| #define CL_PRIMITIVES_COUNT _MMIO(0x2340) |
| #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) |
| #define PS_INVOCATION_COUNT _MMIO(0x2348) |
| #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) |
| #define PS_DEPTH_COUNT _MMIO(0x2350) |
| #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) |
| |
| /* There are the 4 64-bit counter registers, one for each stream output */ |
| #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) |
| #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) |
| |
| #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) |
| #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) |
| |
| #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) |
| #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) |
| #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) |
| #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) |
| #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) |
| #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) |
| |
| #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) |
| #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) |
| #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) |
| |
| /* There are the 16 64-bit CS General Purpose Registers */ |
| #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) |
| #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) |
| |
| #define GEN7_OACONTROL _MMIO(0x2360) |
| #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 |
| #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F |
| #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 |
| #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) |
| #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) |
| #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) |
| #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) |
| #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) |
| #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) |
| #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) |
| #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) |
| #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) |
| #define GEN7_OACONTROL_FORMAT_SHIFT 2 |
| #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) |
| #define GEN7_OACONTROL_ENABLE (1 << 0) |
| |
| #define GEN8_OACTXID _MMIO(0x2364) |
| |
| #define GEN8_OA_DEBUG _MMIO(0x2B04) |
| #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) |
| #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) |
| #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) |
| #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) |
| |
| #define GEN8_OACONTROL _MMIO(0x2B00) |
| #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) |
| #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) |
| #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) |
| #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) |
| #define GEN8_OA_REPORT_FORMAT_SHIFT 2 |
| #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) |
| #define GEN8_OA_COUNTER_ENABLE (1 << 0) |
| |
| #define GEN8_OACTXCONTROL _MMIO(0x2360) |
| #define GEN8_OA_TIMER_PERIOD_MASK 0x3F |
| #define GEN8_OA_TIMER_PERIOD_SHIFT 2 |
| #define GEN8_OA_TIMER_ENABLE (1 << 1) |
| #define GEN8_OA_COUNTER_RESUME (1 << 0) |
| |
| #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ |
| #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) |
| #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) |
| #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) |
| #define GEN7_OABUFFER_RESUME (1 << 0) |
| |
| #define GEN8_OABUFFER_UDW _MMIO(0x23b4) |
| #define GEN8_OABUFFER _MMIO(0x2b14) |
| #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
| |
| #define GEN7_OASTATUS1 _MMIO(0x2364) |
| #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 |
| #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) |
| #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) |
| #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) |
| |
| #define GEN7_OASTATUS2 _MMIO(0x2368) |
| #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 |
| #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
| |
| #define GEN8_OASTATUS _MMIO(0x2b08) |
| #define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17) |
| #define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16) |
| #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) |
| #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) |
| #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) |
| #define GEN8_OASTATUS_REPORT_LOST (1 << 0) |
| |
| #define GEN8_OAHEADPTR _MMIO(0x2B0C) |
| #define GEN8_OAHEADPTR_MASK 0xffffffc0 |
| #define GEN8_OATAILPTR _MMIO(0x2B10) |
| #define GEN8_OATAILPTR_MASK 0xffffffc0 |
| |
| #define OABUFFER_SIZE_128K (0 << 3) |
| #define OABUFFER_SIZE_256K (1 << 3) |
| #define OABUFFER_SIZE_512K (2 << 3) |
| #define OABUFFER_SIZE_1M (3 << 3) |
| #define OABUFFER_SIZE_2M (4 << 3) |
| #define OABUFFER_SIZE_4M (5 << 3) |
| #define OABUFFER_SIZE_8M (6 << 3) |
| #define OABUFFER_SIZE_16M (7 << 3) |
| |
| #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) |
| |
| /* Gen12 OAR unit */ |
| #define GEN12_OAR_OACONTROL _MMIO(0x2960) |
| #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 |
| #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) |
| |
| #define GEN12_OACTXCONTROL _MMIO(0x2360) |
| #define GEN12_OAR_OASTATUS _MMIO(0x2968) |
| |
| /* Gen12 OAG unit */ |
| #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) |
| #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 |
| #define GEN12_OAG_OATAILPTR _MMIO(0xdb04) |
| #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 |
| |
| #define GEN12_OAG_OABUFFER _MMIO(0xdb08) |
| #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) |
| #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) |
| #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
| |
| #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) |
| #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 |
| #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) |
| #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) |
| |
| #define GEN12_OAG_OACONTROL _MMIO(0xdaf4) |
| #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 |
| #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) |
| |
| #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) |
| #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) |
| #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) |
| #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) |
| #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) |
| |
| #define GEN12_OAG_OASTATUS _MMIO(0xdafc) |
| #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) |
| #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) |
| #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) |
| |
| /* |
| * Flexible, Aggregate EU Counter Registers. |
| * Note: these aren't contiguous |
| */ |
| #define EU_PERF_CNTL0 _MMIO(0xe458) |
| #define EU_PERF_CNTL1 _MMIO(0xe558) |
| #define EU_PERF_CNTL2 _MMIO(0xe658) |
| #define EU_PERF_CNTL3 _MMIO(0xe758) |
| #define EU_PERF_CNTL4 _MMIO(0xe45c) |
| #define EU_PERF_CNTL5 _MMIO(0xe55c) |
| #define EU_PERF_CNTL6 _MMIO(0xe65c) |
| |
| /* |
| * OA Boolean state |
| */ |
| |
| #define OASTARTTRIG1 _MMIO(0x2710) |
| #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 |
| #define OASTARTTRIG1_THRESHOLD_MASK 0xffff |
| |
| #define OASTARTTRIG2 _MMIO(0x2714) |
| #define OASTARTTRIG2_INVERT_A_0 (1 << 0) |
| #define OASTARTTRIG2_INVERT_A_1 (1 << 1) |
| #define OASTARTTRIG2_INVERT_A_2 (1 << 2) |
| #define OASTARTTRIG2_INVERT_A_3 (1 << 3) |
| #define OASTARTTRIG2_INVERT_A_4 (1 << 4) |
| #define OASTARTTRIG2_INVERT_A_5 (1 << 5) |
| #define OASTARTTRIG2_INVERT_A_6 (1 << 6) |
| #define OASTARTTRIG2_INVERT_A_7 (1 << 7) |
| #define OASTARTTRIG2_INVERT_A_8 (1 << 8) |
| #define OASTARTTRIG2_INVERT_A_9 (1 << 9) |
| #define OASTARTTRIG2_INVERT_A_10 (1 << 10) |
| #define OASTARTTRIG2_INVERT_A_11 (1 << 11) |
| #define OASTARTTRIG2_INVERT_A_12 (1 << 12) |
| #define OASTARTTRIG2_INVERT_A_13 (1 << 13) |
| #define OASTARTTRIG2_INVERT_A_14 (1 << 14) |
| #define OASTARTTRIG2_INVERT_A_15 (1 << 15) |
| #define OASTARTTRIG2_INVERT_B_0 (1 << 16) |
| #define OASTARTTRIG2_INVERT_B_1 (1 << 17) |
| #define OASTARTTRIG2_INVERT_B_2 (1 << 18) |
| #define OASTARTTRIG2_INVERT_B_3 (1 << 19) |
| #define OASTARTTRIG2_INVERT_C_0 (1 << 20) |
| #define OASTARTTRIG2_INVERT_C_1 (1 << 21) |
| #define OASTARTTRIG2_INVERT_D_0 (1 << 22) |
| #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) |
| #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) |
| #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) |
| #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) |
| #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) |
| #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) |
| |
| #define OASTARTTRIG3 _MMIO(0x2718) |
| #define OASTARTTRIG3_NOA_SELECT_MASK 0xf |
| #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 |
| #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 |
| #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 |
| #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 |
| #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 |
| #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 |
| #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 |
| #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 |
| |
| #define OASTARTTRIG4 _MMIO(0x271c) |
| #define OASTARTTRIG4_NOA_SELECT_MASK 0xf |
| #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 |
| #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 |
| #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 |
| #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 |
| #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 |
| #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 |
| #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 |
| #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 |
| |
| #define OASTARTTRIG5 _MMIO(0x2720) |
| #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 |
| #define OASTARTTRIG5_THRESHOLD_MASK 0xffff |
| |
| #define OASTARTTRIG6 _MMIO(0x2724) |
| #define OASTARTTRIG6_INVERT_A_0 (1 << 0) |
| #define OASTARTTRIG6_INVERT_A_1 (1 << 1) |
| #define OASTARTTRIG6_INVERT_A_2 (1 << 2) |
| #define OASTARTTRIG6_INVERT_A_3 (1 << 3) |
| #define OASTARTTRIG6_INVERT_A_4 (1 << 4) |
| #define OASTARTTRIG6_INVERT_A_5 (1 << 5) |
| #define OASTARTTRIG6_INVERT_A_6 (1 << 6) |
| #define OASTARTTRIG6_INVERT_A_7 (1 << 7) |
| #define OASTARTTRIG6_INVERT_A_8 (1 << 8) |
| #define OASTARTTRIG6_INVERT_A_9 (1 << 9) |
| #define OASTARTTRIG6_INVERT_A_10 (1 << 10) |
| #define OASTARTTRIG6_INVERT_A_11 (1 << 11) |
| #define OASTARTTRIG6_INVERT_A_12 (1 << 12) |
| #define OASTARTTRIG6_INVERT_A_13 (1 << 13) |
| #define OASTARTTRIG6_INVERT_A_14 (1 << 14) |
| #define OASTARTTRIG6_INVERT_A_15 (1 << 15) |
| #define OASTARTTRIG6_INVERT_B_0 (1 << 16) |
| #define OASTARTTRIG6_INVERT_B_1 (1 << 17) |
| #define OASTARTTRIG6_INVERT_B_2 (1 << 18) |
| #define OASTARTTRIG6_INVERT_B_3 (1 << 19) |
| #define OASTARTTRIG6_INVERT_C_0 (1 << 20) |
| #define OASTARTTRIG6_INVERT_C_1 (1 << 21) |
| #define OASTARTTRIG6_INVERT_D_0 (1 << 22) |
| #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) |
| #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) |
| #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) |
| #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) |
| #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) |
| #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) |
| |
| #define OASTARTTRIG7 _MMIO(0x2728) |
| #define OASTARTTRIG7_NOA_SELECT_MASK 0xf |
| #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 |
| #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 |
| #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 |
| #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 |
| #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 |
| #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 |
| #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 |
| #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 |
| |
| #define OASTARTTRIG8 _MMIO(0x272c) |
| #define OASTARTTRIG8_NOA_SELECT_MASK 0xf |
| #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 |
| #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 |
| #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 |
| #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 |
| #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 |
| #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 |
| #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 |
| #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 |
| |
| #define OAREPORTTRIG1 _MMIO(0x2740) |
| #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff |
| #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ |
| |
| #define OAREPORTTRIG2 _MMIO(0x2744) |
| #define OAREPORTTRIG2_INVERT_A_0 (1 << 0) |
| #define OAREPORTTRIG2_INVERT_A_1 (1 << 1) |
| #define OAREPORTTRIG2_INVERT_A_2 (1 << 2) |
| #define OAREPORTTRIG2_INVERT_A_3 (1 << 3) |
| #define OAREPORTTRIG2_INVERT_A_4 (1 << 4) |
| #define OAREPORTTRIG2_INVERT_A_5 (1 << 5) |
| #define OAREPORTTRIG2_INVERT_A_6 (1 << 6) |
| #define OAREPORTTRIG2_INVERT_A_7 (1 << 7) |
| #define OAREPORTTRIG2_INVERT_A_8 (1 << 8) |
| #define OAREPORTTRIG2_INVERT_A_9 (1 << 9) |
| #define OAREPORTTRIG2_INVERT_A_10 (1 << 10) |
| #define OAREPORTTRIG2_INVERT_A_11 (1 << 11) |
| #define OAREPORTTRIG2_INVERT_A_12 (1 << 12) |
| #define OAREPORTTRIG2_INVERT_A_13 (1 << 13) |
| #define OAREPORTTRIG2_INVERT_A_14 (1 << 14) |
| #define OAREPORTTRIG2_INVERT_A_15 (1 << 15) |
| #define OAREPORTTRIG2_INVERT_B_0 (1 << 16) |
| #define OAREPORTTRIG2_INVERT_B_1 (1 << 17) |
| #define OAREPORTTRIG2_INVERT_B_2 (1 << 18) |
| #define OAREPORTTRIG2_INVERT_B_3 (1 << 19) |
| #define OAREPORTTRIG2_INVERT_C_0 (1 << 20) |
| #define OAREPORTTRIG2_INVERT_C_1 (1 << 21) |
| #define OAREPORTTRIG2_INVERT_D_0 (1 << 22) |
| #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) |
| #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) |
| |
| #define OAREPORTTRIG3 _MMIO(0x2748) |
| #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf |
| #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 |
| #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 |
| #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 |
| #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 |
| #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 |
| #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 |
| #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 |
| #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 |
| |
| #define OAREPORTTRIG4 _MMIO(0x274c) |
| #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf |
| #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 |
| #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 |
| #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 |
| #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 |
| #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 |
| #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 |
| #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 |
| #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 |
| |
| #define OAREPORTTRIG5 _MMIO(0x2750) |
| #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff |
| #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ |
| |
| #define OAREPORTTRIG6 _MMIO(0x2754) |
| #define OAREPORTTRIG6_INVERT_A_0 (1 << 0) |
| #define OAREPORTTRIG6_INVERT_A_1 (1 << 1) |
| #define OAREPORTTRIG6_INVERT_A_2 (1 << 2) |
| #define OAREPORTTRIG6_INVERT_A_3 (1 << 3) |
| #define OAREPORTTRIG6_INVERT_A_4 (1 << 4) |
| #define OAREPORTTRIG6_INVERT_A_5 (1 << 5) |
| #define OAREPORTTRIG6_INVERT_A_6 (1 << 6) |
| #define OAREPORTTRIG6_INVERT_A_7 (1 << 7) |
| #define OAREPORTTRIG6_INVERT_A_8 (1 << 8) |
| #define OAREPORTTRIG6_INVERT_A_9 (1 << 9) |
| #define OAREPORTTRIG6_INVERT_A_10 (1 << 10) |
| #define OAREPORTTRIG6_INVERT_A_11 (1 << 11) |
| #define OAREPORTTRIG6_INVERT_A_12 (1 << 12) |
| #define OAREPORTTRIG6_INVERT_A_13 (1 << 13) |
| #define OAREPORTTRIG6_INVERT_A_14 (1 << 14) |
| #define OAREPORTTRIG6_INVERT_A_15 (1 << 15) |
| #define OAREPORTTRIG6_INVERT_B_0 (1 << 16) |
| #define OAREPORTTRIG6_INVERT_B_1 (1 << 17) |
| #define OAREPORTTRIG6_INVERT_B_2 (1 << 18) |
| #define OAREPORTTRIG6_INVERT_B_3 (1 << 19) |
| #define OAREPORTTRIG6_INVERT_C_0 (1 << 20) |
| #define OAREPORTTRIG6_INVERT_C_1 (1 << 21) |
| #define OAREPORTTRIG6_INVERT_D_0 (1 << 22) |
| #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) |
| #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) |
| |
| #define OAREPORTTRIG7 _MMIO(0x2758) |
| #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf |
| #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 |
| #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 |
| #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 |
| #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 |
| #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 |
| #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 |
| #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 |
| #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 |
| |
| #define OAREPORTTRIG8 _MMIO(0x275c) |
| #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf |
| #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 |
| #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 |
| #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 |
| #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 |
| #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 |
| #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 |
| #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 |
| #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 |
| |
| /* Same layout as OASTARTTRIGX */ |
| #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900) |
| #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904) |
| #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908) |
| #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c) |
| #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910) |
| #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914) |
| #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918) |
| #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c) |
| |
| /* Same layout as OAREPORTTRIGX */ |
| #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920) |
| #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924) |
| #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928) |
| #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c) |
| #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930) |
| #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934) |
| #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938) |
| #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c) |
| |
| /* CECX_0 */ |
| #define OACEC_COMPARE_LESS_OR_EQUAL 6 |
| #define OACEC_COMPARE_NOT_EQUAL 5 |
| #define OACEC_COMPARE_LESS_THAN 4 |
| #define OACEC_COMPARE_GREATER_OR_EQUAL 3 |
| #define OACEC_COMPARE_EQUAL 2 |
| #define OACEC_COMPARE_GREATER_THAN 1 |
| #define OACEC_COMPARE_ANY_EQUAL 0 |
| |
| #define OACEC_COMPARE_VALUE_MASK 0xffff |
| #define OACEC_COMPARE_VALUE_SHIFT 3 |
| |
| #define OACEC_SELECT_NOA (0 << 19) |
| #define OACEC_SELECT_PREV (1 << 19) |
| #define OACEC_SELECT_BOOLEAN (2 << 19) |
| |
| /* 11-bit array 0: pass-through, 1: negated */ |
| #define GEN12_OASCEC_NEGATE_MASK 0x7ff |
| #define GEN12_OASCEC_NEGATE_SHIFT 21 |
| |
| /* CECX_1 */ |
| #define OACEC_MASK_MASK 0xffff |
| #define OACEC_CONSIDERATIONS_MASK 0xffff |
| #define OACEC_CONSIDERATIONS_SHIFT 16 |
| |
| #define OACEC0_0 _MMIO(0x2770) |
| #define OACEC0_1 _MMIO(0x2774) |
| #define OACEC1_0 _MMIO(0x2778) |
| #define OACEC1_1 _MMIO(0x277c) |
| #define OACEC2_0 _MMIO(0x2780) |
| #define OACEC2_1 _MMIO(0x2784) |
| #define OACEC3_0 _MMIO(0x2788) |
| #define OACEC3_1 _MMIO(0x278c) |
| #define OACEC4_0 _MMIO(0x2790) |
| #define OACEC4_1 _MMIO(0x2794) |
| #define OACEC5_0 _MMIO(0x2798) |
| #define OACEC5_1 _MMIO(0x279c) |
| #define OACEC6_0 _MMIO(0x27a0) |
| #define OACEC6_1 _MMIO(0x27a4) |
| #define OACEC7_0 _MMIO(0x27a8) |
| #define OACEC7_1 _MMIO(0x27ac) |
| |
| /* Same layout as CECX_Y */ |
| #define GEN12_OAG_CEC0_0 _MMIO(0xd940) |
| #define GEN12_OAG_CEC0_1 _MMIO(0xd944) |
| #define GEN12_OAG_CEC1_0 _MMIO(0xd948) |
| #define GEN12_OAG_CEC1_1 _MMIO(0xd94c) |
| #define GEN12_OAG_CEC2_0 _MMIO(0xd950) |
| #define GEN12_OAG_CEC2_1 _MMIO(0xd954) |
| #define GEN12_OAG_CEC3_0 _MMIO(0xd958) |
| #define GEN12_OAG_CEC3_1 _MMIO(0xd95c) |
| #define GEN12_OAG_CEC4_0 _MMIO(0xd960) |
| #define GEN12_OAG_CEC4_1 _MMIO(0xd964) |
| #define GEN12_OAG_CEC5_0 _MMIO(0xd968) |
| #define GEN12_OAG_CEC5_1 _MMIO(0xd96c) |
| #define GEN12_OAG_CEC6_0 _MMIO(0xd970) |
| #define GEN12_OAG_CEC6_1 _MMIO(0xd974) |
| #define GEN12_OAG_CEC7_0 _MMIO(0xd978) |
| #define GEN12_OAG_CEC7_1 _MMIO(0xd97c) |
| |
| /* Same layout as CECX_Y + negate 11-bit array */ |
| #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00) |
| #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04) |
| #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08) |
| #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c) |
| #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10) |
| #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14) |
| #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18) |
| #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c) |
| #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20) |
| #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24) |
| #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28) |
| #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c) |
| #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30) |
| #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34) |
| #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38) |
| #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c) |
| |
| /* OA perf counters */ |
| #define OA_PERFCNT1_LO _MMIO(0x91B8) |
| #define OA_PERFCNT1_HI _MMIO(0x91BC) |
| #define OA_PERFCNT2_LO _MMIO(0x91C0) |
| #define OA_PERFCNT2_HI _MMIO(0x91C4) |
| #define OA_PERFCNT3_LO _MMIO(0x91C8) |
| #define OA_PERFCNT3_HI _MMIO(0x91CC) |
| #define OA_PERFCNT4_LO _MMIO(0x91D8) |
| #define OA_PERFCNT4_HI _MMIO(0x91DC) |
| |
| #define OA_PERFMATRIX_LO _MMIO(0x91C8) |
| #define OA_PERFMATRIX_HI _MMIO(0x91CC) |
| |
| /* RPM unit config (Gen8+) */ |
| #define RPM_CONFIG0 _MMIO(0x0D00) |
| #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 |
| #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) |
| #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 |
| #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 |
| #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 |
| #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 |
| #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) |
| |
| #define RPM_CONFIG1 _MMIO(0x0D04) |
| #define GEN10_GT_NOA_ENABLE (1 << 9) |
| |
| /* GPM unit config (Gen9+) */ |
| #define CTC_MODE _MMIO(0xA26C) |
| #define CTC_SOURCE_PARAMETER_MASK 1 |
| #define CTC_SOURCE_CRYSTAL_CLOCK 0 |
| #define CTC_SOURCE_DIVIDE_LOGIC 1 |
| #define CTC_SHIFT_PARAMETER_SHIFT 1 |
| #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) |
| |
| /* RCP unit config (Gen8+) */ |
| #define RCP_CONFIG _MMIO(0x0D08) |
| |
| /* NOA (HSW) */ |
| #define HSW_MBVID2_NOA0 _MMIO(0x9E80) |
| #define HSW_MBVID2_NOA1 _MMIO(0x9E84) |
| #define HSW_MBVID2_NOA2 _MMIO(0x9E88) |
| #define HSW_MBVID2_NOA3 _MMIO(0x9E8C) |
| #define HSW_MBVID2_NOA4 _MMIO(0x9E90) |
| #define HSW_MBVID2_NOA5 _MMIO(0x9E94) |
| #define HSW_MBVID2_NOA6 _MMIO(0x9E98) |
| #define HSW_MBVID2_NOA7 _MMIO(0x9E9C) |
| #define HSW_MBVID2_NOA8 _MMIO(0x9EA0) |
| #define HSW_MBVID2_NOA9 _MMIO(0x9EA4) |
| |
| #define HSW_MBVID2_MISR0 _MMIO(0x9EC0) |
| |
| /* NOA (Gen8+) */ |
| #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) |
| |
| #define MICRO_BP0_0 _MMIO(0x9800) |
| #define MICRO_BP0_2 _MMIO(0x9804) |
| #define MICRO_BP0_1 _MMIO(0x9808) |
| |
| #define MICRO_BP1_0 _MMIO(0x980C) |
| #define MICRO_BP1_2 _MMIO(0x9810) |
| #define MICRO_BP1_1 _MMIO(0x9814) |
| |
| #define MICRO_BP2_0 _MMIO(0x9818) |
| #define MICRO_BP2_2 _MMIO(0x981C) |
| #define MICRO_BP2_1 _MMIO(0x9820) |
| |
| #define MICRO_BP3_0 _MMIO(0x9824) |
| #define MICRO_BP3_2 _MMIO(0x9828) |
| #define MICRO_BP3_1 _MMIO(0x982C) |
| |
| #define MICRO_BP_TRIGGER _MMIO(0x9830) |
| #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) |
| #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) |
| #define MICRO_BP_FIRED_ARMED _MMIO(0x983C) |
| |
| #define GEN12_OAA_DBG_REG _MMIO(0xdc44) |
| #define GEN12_OAG_OA_PESS _MMIO(0x2b2c) |
| #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40) |
| |
| #define GDT_CHICKEN_BITS _MMIO(0x9840) |
| #define GT_NOA_ENABLE 0x00000080 |
| |
| #define NOA_DATA _MMIO(0x986C) |
| #define NOA_WRITE _MMIO(0x9888) |
| #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) |
| |
| #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
| #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |
| #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) |
| |
| /* |
| * Reset registers |
| */ |
| #define DEBUG_RESET_I830 _MMIO(0x6070) |
| #define DEBUG_RESET_FULL (1 << 7) |
| #define DEBUG_RESET_RENDER (1 << 8) |
| #define DEBUG_RESET_DISPLAY (1 << 9) |
| |
| /* |
| * IOSF sideband |
| */ |
| #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) |
| #define IOSF_DEVFN_SHIFT 24 |
| #define IOSF_OPCODE_SHIFT 16 |
| #define IOSF_PORT_SHIFT 8 |
| #define IOSF_BYTE_ENABLES_SHIFT 4 |
| #define IOSF_BAR_SHIFT 1 |
| #define IOSF_SB_BUSY (1 << 0) |
| #define IOSF_PORT_BUNIT 0x03 |
| #define IOSF_PORT_PUNIT 0x04 |
| #define IOSF_PORT_NC 0x11 |
| #define IOSF_PORT_DPIO 0x12 |
| #define IOSF_PORT_GPIO_NC 0x13 |
| #define IOSF_PORT_CCK 0x14 |
| #define IOSF_PORT_DPIO_2 0x1a |
| #define IOSF_PORT_FLISDSI 0x1b |
| #define IOSF_PORT_GPIO_SC 0x48 |
| #define IOSF_PORT_GPIO_SUS 0xa8 |
| #define IOSF_PORT_CCU 0xa9 |
| #define CHV_IOSF_PORT_GPIO_N 0x13 |
| #define CHV_IOSF_PORT_GPIO_SE 0x48 |
| #define CHV_IOSF_PORT_GPIO_E 0xa8 |
| #define CHV_IOSF_PORT_GPIO_SW 0xb2 |
| #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) |
| #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) |
| |
| /* See configdb bunit SB addr map */ |
| #define BUNIT_REG_BISOC 0x11 |
| |
| /* PUNIT_REG_*SSPM0 */ |
| #define _SSPM0_SSC(val) ((val) << 0) |
| #define SSPM0_SSC_MASK _SSPM0_SSC(0x3) |
| #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) |
| #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) |
| #define SSPM0_SSC_RESET _SSPM0_SSC(0x2) |
| #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) |
| #define _SSPM0_SSS(val) ((val) << 24) |
| #define SSPM0_SSS_MASK _SSPM0_SSS(0x3) |
| #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) |
| #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) |
| #define SSPM0_SSS_RESET _SSPM0_SSS(0x2) |
| #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) |
| |
| /* PUNIT_REG_*SSPM1 */ |
| #define SSPM1_FREQSTAT_SHIFT 24 |
| #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) |
| #define SSPM1_FREQGUAR_SHIFT 8 |
| #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) |
| #define SSPM1_FREQ_SHIFT 0 |
| #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) |
| |
| #define PUNIT_REG_VEDSSPM0 0x32 |
| #define PUNIT_REG_VEDSSPM1 0x33 |
| |
| #define PUNIT_REG_DSPSSPM 0x36 |
| #define DSPFREQSTAT_SHIFT_CHV 24 |
| #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) |
| #define DSPFREQGUAR_SHIFT_CHV 8 |
| #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) |
| #define DSPFREQSTAT_SHIFT 30 |
| #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) |
| #define DSPFREQGUAR_SHIFT 14 |
| #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) |
| #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ |
| #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ |
| #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ |
| #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
| #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) |
| #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) |
| #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) |
| #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) |
| #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) |
| #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) |
| #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) |
| #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) |
| #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) |
| #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) |
| #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) |
| |
| #define PUNIT_REG_ISPSSPM0 0x39 |
| #define PUNIT_REG_ISPSSPM1 0x3a |
| |
| #define PUNIT_REG_PWRGT_CTRL 0x60 |
| #define PUNIT_REG_PWRGT_STATUS 0x61 |
| #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) |
| #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) |
| #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) |
| #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) |
| #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) |
| |
| #define PUNIT_PWGT_IDX_RENDER 0 |
| #define PUNIT_PWGT_IDX_MEDIA 1 |
| #define PUNIT_PWGT_IDX_DISP2D 3 |
| #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 |
| #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 |
| #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 |
| #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 |
| #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 |
| #define PUNIT_PWGT_IDX_DPIO_RX0 10 |
| #define PUNIT_PWGT_IDX_DPIO_RX1 11 |
| #define PUNIT_PWGT_IDX_DPIO_CMN_D 12 |
| |
| #define PUNIT_REG_GPU_LFM 0xd3 |
| #define PUNIT_REG_GPU_FREQ_REQ 0xd4 |
| #define PUNIT_REG_GPU_FREQ_STS 0xd8 |
| #define GPLLENABLE (1 << 4) |
| #define GENFREQSTATUS (1 << 0) |
| #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
| #define PUNIT_REG_CZ_TIMESTAMP 0xce |
| |
| #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ |
| #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ |
| |
| #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 |
| #define FB_GFX_FREQ_FUSE_MASK 0xff |
| #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 |
| #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 |
| #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 |
| |
| #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 |
| #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 |
| |
| #define PUNIT_REG_DDR_SETUP2 0x139 |
| #define FORCE_DDR_FREQ_REQ_ACK (1 << 8) |
| #define FORCE_DDR_LOW_FREQ (1 << 1) |
| #define FORCE_DDR_HIGH_FREQ (1 << 0) |
| |
| #define PUNIT_GPU_STATUS_REG 0xdb |
| #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 |
| #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff |
| #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 |
| #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff |
| |
| #define PUNIT_GPU_DUTYCYCLE_REG 0xdf |
| #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 |
| #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff |
| |
| #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
| #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 |
| #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 |
| #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 |
| #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 |
| #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 |
| #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 |
| #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 |
| #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 |
| #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 |
| |
| #define VLV_TURBO_SOC_OVERRIDE 0x04 |
| #define VLV_OVERRIDE_EN 1 |
| #define VLV_SOC_TDP_EN (1 << 1) |
| #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) |
| #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) |
| |
| /* vlv2 north clock has */ |
| #define CCK_FUSE_REG 0x8 |
| #define CCK_FUSE_HPLL_FREQ_MASK 0x3 |
| #define CCK_REG_DSI_PLL_FUSE 0x44 |
| #define CCK_REG_DSI_PLL_CONTROL 0x48 |
| #define DSI_PLL_VCO_EN (1 << 31) |
| #define DSI_PLL_LDO_GATE (1 << 30) |
| #define DSI_PLL_P1_POST_DIV_SHIFT 17 |
| #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) |
| #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) |
| #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) |
| #define DSI_PLL_MUX_MASK (3 << 9) |
| #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) |
| #define DSI_PLL_MUX_DSI0_CCK (1 << 10) |
| #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) |
| #define DSI_PLL_MUX_DSI1_CCK (1 << 9) |
| #define DSI_PLL_CLK_GATE_MASK (0xf << 5) |
| #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) |
| #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) |
| #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) |
| #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) |
| #define DSI_PLL_LOCK (1 << 0) |
| #define CCK_REG_DSI_PLL_DIVIDER 0x4c |
| #define DSI_PLL_LFSR (1 << 31) |
| #define DSI_PLL_FRACTION_EN (1 << 30) |
| #define DSI_PLL_FRAC_COUNTER_SHIFT 27 |
| #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) |
| #define DSI_PLL_USYNC_CNT_SHIFT 18 |
| #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) |
| #define DSI_PLL_N1_DIV_SHIFT 16 |
| #define DSI_PLL_N1_DIV_MASK (3 << 16) |
| #define DSI_PLL_M1_DIV_SHIFT 0 |
| #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) |
| #define CCK_CZ_CLOCK_CONTROL 0x62 |
| #define CCK_GPLL_CLOCK_CONTROL 0x67 |
| #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
| #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c |
| #define CCK_TRUNK_FORCE_ON (1 << 17) |
| #define CCK_TRUNK_FORCE_OFF (1 << 16) |
| #define CCK_FREQUENCY_STATUS (0x1f << 8) |
| #define CCK_FREQUENCY_STATUS_SHIFT 8 |
| #define CCK_FREQUENCY_VALUES (0x1f << 0) |
| |
| /* DPIO registers */ |
| #define DPIO_DEVFN 0 |
| |
| #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) |
| #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ |
| #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ |
| #define DPIO_SFR_BYPASS (1 << 1) |
| #define DPIO_CMNRST (1 << 0) |
| |
| #define DPIO_PHY(pipe) ((pipe) >> 1) |
| |
| /* |
| * Per pipe/PLL DPIO regs |
| */ |
| #define _VLV_PLL_DW3_CH0 0x800c |
| #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
| #define DPIO_POST_DIV_DAC 0 |
| #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ |
| #define DPIO_POST_DIV_LVDS1 2 |
| #define DPIO_POST_DIV_LVDS2 3 |
| #define DPIO_K_SHIFT (24) /* 4 bits */ |
| #define DPIO_P1_SHIFT (21) /* 3 bits */ |
| #define DPIO_P2_SHIFT (16) /* 5 bits */ |
| #define DPIO_N_SHIFT (12) /* 4 bits */ |
| #define DPIO_ENABLE_CALIBRATION (1 << 11) |
| #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ |
| #define DPIO_M2DIV_MASK 0xff |
| #define _VLV_PLL_DW3_CH1 0x802c |
| #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) |
| |
| #define _VLV_PLL_DW5_CH0 0x8014 |
| #define DPIO_REFSEL_OVERRIDE 27 |
| #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ |
| #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ |
| #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ |
| #define DPIO_PLL_REFCLK_SEL_MASK 3 |
| #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
| #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ |
| #define _VLV_PLL_DW5_CH1 0x8034 |
| #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) |
| |
| #define _VLV_PLL_DW7_CH0 0x801c |
| #define _VLV_PLL_DW7_CH1 0x803c |
| #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) |
| |
| #define _VLV_PLL_DW8_CH0 0x8040 |
| #define _VLV_PLL_DW8_CH1 0x8060 |
| #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) |
| |
| #define VLV_PLL_DW9_BCAST 0xc044 |
| #define _VLV_PLL_DW9_CH0 0x8044 |
| #define _VLV_PLL_DW9_CH1 0x8064 |
| #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) |
| |
| #define _VLV_PLL_DW10_CH0 0x8048 |
| #define _VLV_PLL_DW10_CH1 0x8068 |
| #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) |
| |
| #define _VLV_PLL_DW11_CH0 0x804c |
| #define _VLV_PLL_DW11_CH1 0x806c |
| #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) |
| |
| /* Spec for ref block start counts at DW10 */ |
| #define VLV_REF_DW13 0x80ac |
| |
| #define VLV_CMN_DW0 0x8100 |
| |
| /* |
| * Per DDI channel DPIO regs |
| */ |
| |
| #define _VLV_PCS_DW0_CH0 0x8200 |
| #define _VLV_PCS_DW0_CH1 0x8400 |
| #define DPIO_PCS_TX_LANE2_RESET (1 << 16) |
| #define DPIO_PCS_TX_LANE1_RESET (1 << 7) |
| #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) |
| #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) |
| #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
| |
| #define _VLV_PCS01_DW0_CH0 0x200 |
| #define _VLV_PCS23_DW0_CH0 0x400 |
| #define _VLV_PCS01_DW0_CH1 0x2600 |
| #define _VLV_PCS23_DW0_CH1 0x2800 |
| #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) |
| #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) |
| |
| #define _VLV_PCS_DW1_CH0 0x8204 |
| #define _VLV_PCS_DW1_CH1 0x8404 |
| #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) |
| #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) |
| #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) |
| #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) |
| #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) |
| #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
| |
| #define _VLV_PCS01_DW1_CH0 0x204 |
| #define _VLV_PCS23_DW1_CH0 0x404 |
| #define _VLV_PCS01_DW1_CH1 0x2604 |
| #define _VLV_PCS23_DW1_CH1 0x2804 |
| #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) |
| #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) |
| |
| #define _VLV_PCS_DW8_CH0 0x8220 |
| #define _VLV_PCS_DW8_CH1 0x8420 |
| #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
| #define CHV_PCS_USEDCLKCHANNEL (1 << 21) |
| #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
| |
| #define _VLV_PCS01_DW8_CH0 0x0220 |
| #define _VLV_PCS23_DW8_CH0 0x0420 |
| #define _VLV_PCS01_DW8_CH1 0x2620 |
| #define _VLV_PCS23_DW8_CH1 0x2820 |
| #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) |
| #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) |
| |
| #define _VLV_PCS_DW9_CH0 0x8224 |
| #define _VLV_PCS_DW9_CH1 0x8424 |
| #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) |
| #define DPIO_PCS_TX2MARGIN_000 (0 << 13) |
| #define DPIO_PCS_TX2MARGIN_101 (1 << 13) |
| #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) |
| #define DPIO_PCS_TX1MARGIN_000 (0 << 10) |
| #define DPIO_PCS_TX1MARGIN_101 (1 << 10) |
| #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
| |
| #define _VLV_PCS01_DW9_CH0 0x224 |
| #define _VLV_PCS23_DW9_CH0 0x424 |
| #define _VLV_PCS01_DW9_CH1 0x2624 |
| #define _VLV_PCS23_DW9_CH1 0x2824 |
| #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) |
| #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) |
| |
| #define _CHV_PCS_DW10_CH0 0x8228 |
| #define _CHV_PCS_DW10_CH1 0x8428 |
| #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) |
| #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) |
| #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) |
| #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) |
| #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) |
| #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) |
| #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) |
| #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) |
| #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
| |
| #define _VLV_PCS01_DW10_CH0 0x0228 |
| #define _VLV_PCS23_DW10_CH0 0x0428 |
| #define _VLV_PCS01_DW10_CH1 0x2628 |
| #define _VLV_PCS23_DW10_CH1 0x2828 |
| #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) |
| #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) |
| |
| #define _VLV_PCS_DW11_CH0 0x822c |
| #define _VLV_PCS_DW11_CH1 0x842c |
| #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) |
| #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) |
| #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) |
| #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) |
| #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
| |
| #define _VLV_PCS01_DW11_CH0 0x022c |
| #define _VLV_PCS23_DW11_CH0 0x042c |
| #define _VLV_PCS01_DW11_CH1 0x262c |
| #define _VLV_PCS23_DW11_CH1 0x282c |
| #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
| #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) |
| |
| #define _VLV_PCS01_DW12_CH0 0x0230 |
| #define _VLV_PCS23_DW12_CH0 0x0430 |
| #define _VLV_PCS01_DW12_CH1 0x2630 |
| #define _VLV_PCS23_DW12_CH1 0x2830 |
| #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) |
| #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) |
| |
| #define _VLV_PCS_DW12_CH0 0x8230 |
| #define _VLV_PCS_DW12_CH1 0x8430 |
| #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) |
| #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) |
| #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) |
| #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) |
| #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) |
| #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) |
| |
| #define _VLV_PCS_DW14_CH0 0x8238 |
| #define _VLV_PCS_DW14_CH1 0x8438 |
| #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) |
| |
| #define _VLV_PCS_DW23_CH0 0x825c |
| #define _VLV_PCS_DW23_CH1 0x845c |
| #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) |
| |
| #define _VLV_TX_DW2_CH0 0x8288 |
| #define _VLV_TX_DW2_CH1 0x8488 |
| #define DPIO_SWING_MARGIN000_SHIFT 16 |
| #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) |
| #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
| #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
| |
| #define _VLV_TX_DW3_CH0 0x828c |
| #define _VLV_TX_DW3_CH1 0x848c |
| /* The following bit for CHV phy */ |
| #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) |
| #define DPIO_SWING_MARGIN101_SHIFT 16 |
| #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) |
| #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
| |
| #define _VLV_TX_DW4_CH0 0x8290 |
| #define _VLV_TX_DW4_CH1 0x8490 |
| #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
| #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) |
| #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
| #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) |
| #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
| |
| #define _VLV_TX3_DW4_CH0 0x690 |
| #define _VLV_TX3_DW4_CH1 0x2a90 |
| #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) |
| |
| #define _VLV_TX_DW5_CH0 0x8294 |
| #define _VLV_TX_DW5_CH1 0x8494 |
| #define DPIO_TX_OCALINIT_EN (1 << 31) |
| #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
| |
| #define _VLV_TX_DW11_CH0 0x82ac |
| #define _VLV_TX_DW11_CH1 0x84ac |
| #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) |
| |
| #define _VLV_TX_DW14_CH0 0x82b8 |
| #define _VLV_TX_DW14_CH1 0x84b8 |
| #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) |
| |
| /* CHV dpPhy registers */ |
| #define _CHV_PLL_DW0_CH0 0x8000 |
| #define _CHV_PLL_DW0_CH1 0x8180 |
| #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) |
| |
| #define _CHV_PLL_DW1_CH0 0x8004 |
| #define _CHV_PLL_DW1_CH1 0x8184 |
| #define DPIO_CHV_N_DIV_SHIFT 8 |
| #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) |
| #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) |
| |
| #define _CHV_PLL_DW2_CH0 0x8008 |
| #define _CHV_PLL_DW2_CH1 0x8188 |
| #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) |
| |
| #define _CHV_PLL_DW3_CH0 0x800c |
| #define _CHV_PLL_DW3_CH1 0x818c |
| #define DPIO_CHV_FRAC_DIV_EN (1 << 16) |
| #define DPIO_CHV_FIRST_MOD (0 << 8) |
| #define DPIO_CHV_SECOND_MOD (1 << 8) |
| #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 |
| #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) |
| #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) |
| |
| #define _CHV_PLL_DW6_CH0 0x8018 |
| #define _CHV_PLL_DW6_CH1 0x8198 |
| #define DPIO_CHV_GAIN_CTRL_SHIFT 16 |
| #define DPIO_CHV_INT_COEFF_SHIFT 8 |
| #define DPIO_CHV_PROP_COEFF_SHIFT 0 |
| #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) |
| |
| #define _CHV_PLL_DW8_CH0 0x8020 |
| #define _CHV_PLL_DW8_CH1 0x81A0 |
| #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 |
| #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) |
| #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) |
| |
| #define _CHV_PLL_DW9_CH0 0x8024 |
| #define _CHV_PLL_DW9_CH1 0x81A4 |
| #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ |
| #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) |
| #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ |
| #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) |
| |
| #define _CHV_CMN_DW0_CH0 0x8100 |
| #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 |
| #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 |
| #define DPIO_ALLDL_POWERDOWN (1 << 1) |
| #define DPIO_ANYDL_POWERDOWN (1 << 0) |
| |
| #define _CHV_CMN_DW5_CH0 0x8114 |
| #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) |
| #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) |
| #define CHV_BUFRIGHTENA1_FORCE (3 << 20) |
| #define CHV_BUFRIGHTENA1_MASK (3 << 20) |
| #define CHV_BUFLEFTENA1_DISABLE (0 << 22) |
| #define CHV_BUFLEFTENA1_NORMAL (1 << 22) |
| #define CHV_BUFLEFTENA1_FORCE (3 << 22) |
| #define CHV_BUFLEFTENA1_MASK (3 << 22) |
| |
| #define _CHV_CMN_DW13_CH0 0x8134 |
| #define _CHV_CMN_DW0_CH1 0x8080 |
| #define DPIO_CHV_S1_DIV_SHIFT 21 |
| #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ |
| #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ |
| #define DPIO_CHV_K_DIV_SHIFT 4 |
| #define DPIO_PLL_FREQLOCK (1 << 1) |
| #define DPIO_PLL_LOCK (1 << 0) |
| #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) |
| |
| #define _CHV_CMN_DW14_CH0 0x8138 |
| #define _CHV_CMN_DW1_CH1 0x8084 |
| #define DPIO_AFC_RECAL (1 << 14) |
| #define DPIO_DCLKP_EN (1 << 13) |
| #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
| #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ |
| #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ |
| #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ |
| #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ |
| #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ |
| #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ |
| #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ |
| #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
| |
| #define _CHV_CMN_DW19_CH0 0x814c |
| #define _CHV_CMN_DW6_CH1 0x8098 |
| #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ |
| #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ |
| #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ |
| #define CHV_CMN_USEDCLKCHANNEL (1 << 13) |
| |
| #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) |
| |
| #define CHV_CMN_DW28 0x8170 |
| #define DPIO_CL1POWERDOWNEN (1 << 23) |
| #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) |
| #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) |
| #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) |
| #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) |
| #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) |
| |
| #define CHV_CMN_DW30 0x8178 |
| #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) |
| #define DPIO_LRC_BYPASS (1 << 3) |
| |
| #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ |
| (lane) * 0x200 + (offset)) |
| |
| #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
| #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) |
| #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) |
| #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) |
| #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) |
| #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) |
| #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) |
| #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) |
| #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) |
| #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) |
| #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) |
| #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
| #define DPIO_FRC_LATENCY_SHFIT 8 |
| #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) |
| #define DPIO_UPAR_SHIFT 30 |
| |
| /* BXT PHY registers */ |
| #define _BXT_PHY0_BASE 0x6C000 |
| #define _BXT_PHY1_BASE 0x162000 |
| #define _BXT_PHY2_BASE 0x163000 |
| #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ |
| _BXT_PHY1_BASE, \ |
| _BXT_PHY2_BASE) |
| |
| #define _BXT_PHY(phy, reg) \ |
| _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) |
| |
| #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ |
| (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ |
| (reg_ch1) - _BXT_PHY0_BASE)) |
| #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ |
| _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) |
| |
| #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) |
| #define MIPIO_RST_CTRL (1 << 2) |
| |
| #define _BXT_PHY_CTL_DDI_A 0x64C00 |
| #define _BXT_PHY_CTL_DDI_B 0x64C10 |
| #define _BXT_PHY_CTL_DDI_C 0x64C20 |
| #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) |
| #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) |
| #define BXT_PHY_LANE_ENABLED (1 << 8) |
| #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ |
| _BXT_PHY_CTL_DDI_B) |
| |
| #define _PHY_CTL_FAMILY_EDP 0x64C80 |
| #define _PHY_CTL_FAMILY_DDI 0x64C90 |
| #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 |
| #define COMMON_RESET_DIS (1 << 31) |
| #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ |
| _PHY_CTL_FAMILY_EDP, \ |
| _PHY_CTL_FAMILY_DDI_C) |
| |
| /* BXT PHY PLL registers */ |
| #define _PORT_PLL_A 0x46074 |
| #define _PORT_PLL_B 0x46078 |
| #define _PORT_PLL_C 0x4607c |
| #define PORT_PLL_ENABLE (1 << 31) |
| #define PORT_PLL_LOCK (1 << 30) |
| #define PORT_PLL_REF_SEL (1 << 27) |
| #define PORT_PLL_POWER_ENABLE (1 << 26) |
| #define PORT_PLL_POWER_STATE (1 << 25) |
| #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) |
| |
| #define _PORT_PLL_EBB_0_A 0x162034 |
| #define _PORT_PLL_EBB_0_B 0x6C034 |
| #define _PORT_PLL_EBB_0_C 0x6C340 |
| #define PORT_PLL_P1_SHIFT 13 |
| #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) |
| #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) |
| #define PORT_PLL_P2_SHIFT 8 |
| #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) |
| #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) |
| #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PLL_EBB_0_B, \ |
| _PORT_PLL_EBB_0_C) |
| |
| #define _PORT_PLL_EBB_4_A 0x162038 |
| #define _PORT_PLL_EBB_4_B 0x6C038 |
| #define _PORT_PLL_EBB_4_C 0x6C344 |
| #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) |
| #define PORT_PLL_RECALIBRATE (1 << 14) |
| #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PLL_EBB_4_B, \ |
| _PORT_PLL_EBB_4_C) |
| |
| #define _PORT_PLL_0_A 0x162100 |
| #define _PORT_PLL_0_B 0x6C100 |
| #define _PORT_PLL_0_C 0x6C380 |
| /* PORT_PLL_0_A */ |
| #define PORT_PLL_M2_MASK 0xFF |
| /* PORT_PLL_1_A */ |
| #define PORT_PLL_N_SHIFT 8 |
| #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) |
| #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) |
| /* PORT_PLL_2_A */ |
| #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF |
| /* PORT_PLL_3_A */ |
| #define PORT_PLL_M2_FRAC_ENABLE (1 << 16) |
| /* PORT_PLL_6_A */ |
| #define PORT_PLL_PROP_COEFF_MASK 0xF |
| #define PORT_PLL_INT_COEFF_MASK (0x1F << 8) |
| #define PORT_PLL_INT_COEFF(x) ((x) << 8) |
| #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) |
| #define PORT_PLL_GAIN_CTL(x) ((x) << 16) |
| /* PORT_PLL_8_A */ |
| #define PORT_PLL_TARGET_CNT_MASK 0x3FF |
| /* PORT_PLL_9_A */ |
| #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 |
| #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) |
| /* PORT_PLL_10_A */ |
| #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) |
| #define PORT_PLL_DCO_AMP_DEFAULT 15 |
| #define PORT_PLL_DCO_AMP_MASK 0x3c00 |
| #define PORT_PLL_DCO_AMP(x) ((x) << 10) |
| #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ |
| _PORT_PLL_0_B, \ |
| _PORT_PLL_0_C) |
| #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ |
| (idx) * 4) |
| |
| /* BXT PHY common lane registers */ |
| #define _PORT_CL1CM_DW0_A 0x162000 |
| #define _PORT_CL1CM_DW0_BC 0x6C000 |
| #define PHY_POWER_GOOD (1 << 16) |
| #define PHY_RESERVED (1 << 7) |
| #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) |
| |
| #define _PORT_CL1CM_DW9_A 0x162024 |
| #define _PORT_CL1CM_DW9_BC 0x6C024 |
| #define IREF0RC_OFFSET_SHIFT 8 |
| #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) |
| #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) |
| |
| #define _PORT_CL1CM_DW10_A 0x162028 |
| #define _PORT_CL1CM_DW10_BC 0x6C028 |
| #define IREF1RC_OFFSET_SHIFT 8 |
| #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) |
| #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) |
| |
| #define _PORT_CL1CM_DW28_A 0x162070 |
| #define _PORT_CL1CM_DW28_BC 0x6C070 |
| #define OCL1_POWER_DOWN_EN (1 << 23) |
| #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) |
| #define SUS_CLK_CONFIG 0x3 |
| #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) |
| |
| #define _PORT_CL1CM_DW30_A 0x162078 |
| #define _PORT_CL1CM_DW30_BC 0x6C078 |
| #define OCL2_LDOFUSE_PWR_DIS (1 << 6) |
| #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) |
| |
| /* |
| * ICL Port/COMBO-PHY Registers |
| */ |
| #define _ICL_COMBOPHY_A 0x162000 |
| #define _ICL_COMBOPHY_B 0x6C000 |
| #define _EHL_COMBOPHY_C 0x160000 |
| #define _RKL_COMBOPHY_D 0x161000 |
| #define _ADL_COMBOPHY_E 0x16B000 |
| |
| #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ |
| _ICL_COMBOPHY_B, \ |
| _EHL_COMBOPHY_C, \ |
| _RKL_COMBOPHY_D, \ |
| _ADL_COMBOPHY_E) |
| |
| /* ICL Port CL_DW registers */ |
| #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| 4 * (dw)) |
| |
| #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) |
| #define CL_POWER_DOWN_ENABLE (1 << 4) |
| #define SUS_CLOCK_CONFIG (3 << 0) |
| |
| #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) |
| #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) |
| #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 |
| #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) |
| #define PWR_UP_ALL_LANES (0x0 << 4) |
| #define PWR_DOWN_LN_3_2_1 (0xe << 4) |
| #define PWR_DOWN_LN_3_2 (0xc << 4) |
| #define PWR_DOWN_LN_3 (0x8 << 4) |
| #define PWR_DOWN_LN_2_1_0 (0x7 << 4) |
| #define PWR_DOWN_LN_1_0 (0x3 << 4) |
| #define PWR_DOWN_LN_3_1 (0xa << 4) |
| #define PWR_DOWN_LN_3_1_0 (0xb << 4) |
| #define PWR_DOWN_LN_MASK (0xf << 4) |
| #define PWR_DOWN_LN_SHIFT 4 |
| #define EDP4K2K_MODE_OVRD_EN (1 << 3) |
| #define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) |
| |
| #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) |
| #define ICL_LANE_ENABLE_AUX (1 << 0) |
| |
| /* ICL Port COMP_DW registers */ |
| #define _ICL_PORT_COMP 0x100 |
| #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_COMP + 4 * (dw)) |
| |
| #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) |
| #define COMP_INIT (1 << 31) |
| |
| #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) |
| |
| #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) |
| #define PROCESS_INFO_DOT_0 (0 << 26) |
| #define PROCESS_INFO_DOT_1 (1 << 26) |
| #define PROCESS_INFO_DOT_4 (2 << 26) |
| #define PROCESS_INFO_MASK (7 << 26) |
| #define PROCESS_INFO_SHIFT 26 |
| #define VOLTAGE_INFO_0_85V (0 << 24) |
| #define VOLTAGE_INFO_0_95V (1 << 24) |
| #define VOLTAGE_INFO_1_05V (2 << 24) |
| #define VOLTAGE_INFO_MASK (3 << 24) |
| #define VOLTAGE_INFO_SHIFT 24 |
| |
| #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) |
| #define IREFGEN (1 << 24) |
| |
| #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) |
| |
| #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) |
| |
| /* ICL Port PCS registers */ |
| #define _ICL_PORT_PCS_AUX 0x300 |
| #define _ICL_PORT_PCS_GRP 0x600 |
| #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) |
| #define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_PCS_AUX + 4 * (dw)) |
| #define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_PCS_GRP + 4 * (dw)) |
| #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_PCS_LN(ln) + 4 * (dw)) |
| #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) |
| #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) |
| #define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy)) |
| #define DCC_MODE_SELECT_MASK (0x3 << 20) |
| #define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) |
| #define COMMON_KEEPER_EN (1 << 26) |
| #define LATENCY_OPTIM_MASK (0x3 << 2) |
| #define LATENCY_OPTIM_VAL(x) ((x) << 2) |
| |
| /* ICL Port TX registers */ |
| #define _ICL_PORT_TX_AUX 0x380 |
| #define _ICL_PORT_TX_GRP 0x680 |
| #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) |
| |
| #define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_TX_AUX + 4 * (dw)) |
| #define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_TX_GRP + 4 * (dw)) |
| #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ |
| _ICL_PORT_TX_LN(ln) + 4 * (dw)) |
| |
| #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) |
| #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) |
| #define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy)) |
| #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) |
| #define SWING_SEL_UPPER_MASK (1 << 15) |
| #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) |
| #define SWING_SEL_LOWER_MASK (0x7 << 11) |
| #define FRC_LATENCY_OPTIM_MASK (0x7 << 8) |
| #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) |
| #define RCOMP_SCALAR(x) ((x) << 0) |
| #define RCOMP_SCALAR_MASK (0xFF << 0) |
| |
| #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) |
| #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) |
| #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) |
| #define LOADGEN_SELECT (1 << 31) |
| #define POST_CURSOR_1(x) ((x) << 12) |
| #define POST_CURSOR_1_MASK (0x3F << 12) |
| #define POST_CURSOR_2(x) ((x) << 6) |
| #define POST_CURSOR_2_MASK (0x3F << 6) |
| #define CURSOR_COEFF(x) ((x) << 0) |
| #define CURSOR_COEFF_MASK (0x3F << 0) |
| |
| #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) |
| #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) |
| #define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy)) |
| #define TX_TRAINING_EN (1 << 31) |
| #define TAP2_DISABLE (1 << 30) |
| #define TAP3_DISABLE (1 << 29) |
| #define SCALING_MODE_SEL(x) ((x) << 18) |
| #define SCALING_MODE_SEL_MASK (0x7 << 18) |
| #define RTERM_SELECT(x) ((x) << 3) |
| #define RTERM_SELECT_MASK (0x7 << 3) |
| |
| #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) |
| #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) |
| #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) |
| #define N_SCALAR(x) ((x) << 24) |
| #define N_SCALAR_MASK (0x7F << 24) |
| |
| #define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy)) |
| #define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) |
| #define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy)) |
| #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) |
| #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) |
| #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) |
| |
| #define _ICL_DPHY_CHKN_REG 0x194 |
| #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) |
| #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) |
| |
| #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ |
| _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) |
| |
| #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C |
| #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C |
| #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C |
| #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C |
| #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C |
| #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C |
| #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C |
| #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C |
| #define MG_TX1_LINK_PARAMS(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ |
| MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ |
| MG_TX_LINK_PARAMS_TX1LN1_PORT1) |
| |
| #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC |
| #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC |
| #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC |
| #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC |
| #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC |
| #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC |
| #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC |
| #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC |
| #define MG_TX2_LINK_PARAMS(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ |
| MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ |
| MG_TX_LINK_PARAMS_TX2LN1_PORT1) |
| #define CRI_USE_FS32 (1 << 5) |
| |
| #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C |
| #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C |
| #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C |
| #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C |
| #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C |
| #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C |
| #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C |
| #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C |
| #define MG_TX1_PISO_READLOAD(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ |
| MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ |
| MG_TX_PISO_READLOAD_TX1LN1_PORT1) |
| |
| #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC |
| #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC |
| #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC |
| #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC |
| #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC |
| #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC |
| #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC |
| #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC |
| #define MG_TX2_PISO_READLOAD(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ |
| MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ |
| MG_TX_PISO_READLOAD_TX2LN1_PORT1) |
| #define CRI_CALCINIT (1 << 1) |
| |
| #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 |
| #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 |
| #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 |
| #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 |
| #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 |
| #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 |
| #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 |
| #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 |
| #define MG_TX1_SWINGCTRL(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ |
| MG_TX_SWINGCTRL_TX1LN0_PORT2, \ |
| MG_TX_SWINGCTRL_TX1LN1_PORT1) |
| |
| #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 |
| #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 |
| #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 |
| #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 |
| #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 |
| #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 |
| #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 |
| #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 |
| #define MG_TX2_SWINGCTRL(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ |
| MG_TX_SWINGCTRL_TX2LN0_PORT2, \ |
| MG_TX_SWINGCTRL_TX2LN1_PORT1) |
| #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) |
| #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) |
| |
| #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 |
| #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 |
| #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 |
| #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 |
| #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 |
| #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 |
| #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 |
| #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 |
| #define MG_TX1_DRVCTRL(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ |
| MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ |
| MG_TX_DRVCTRL_TX1LN1_TXPORT1) |
| |
| #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 |
| #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 |
| #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 |
| #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 |
| #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 |
| #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 |
| #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 |
| #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 |
| #define MG_TX2_DRVCTRL(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ |
| MG_TX_DRVCTRL_TX2LN0_PORT2, \ |
| MG_TX_DRVCTRL_TX2LN1_PORT1) |
| #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) |
| #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) |
| #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) |
| #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) |
| #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) |
| #define CRI_LOADGEN_SEL(x) ((x) << 12) |
| #define CRI_LOADGEN_SEL_MASK (0x3 << 12) |
| |
| #define MG_CLKHUB_LN0_PORT1 0x16839C |
| #define MG_CLKHUB_LN1_PORT1 0x16879C |
| #define MG_CLKHUB_LN0_PORT2 0x16939C |
| #define MG_CLKHUB_LN1_PORT2 0x16979C |
| #define MG_CLKHUB_LN0_PORT3 0x16A39C |
| #define MG_CLKHUB_LN1_PORT3 0x16A79C |
| #define MG_CLKHUB_LN0_PORT4 0x16B39C |
| #define MG_CLKHUB_LN1_PORT4 0x16B79C |
| #define MG_CLKHUB(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \ |
| MG_CLKHUB_LN0_PORT2, \ |
| MG_CLKHUB_LN1_PORT1) |
| #define CFG_LOW_RATE_LKREN_EN (1 << 11) |
| |
| #define MG_TX_DCC_TX1LN0_PORT1 0x168110 |
| #define MG_TX_DCC_TX1LN1_PORT1 0x168510 |
| #define MG_TX_DCC_TX1LN0_PORT2 0x169110 |
| #define MG_TX_DCC_TX1LN1_PORT2 0x169510 |
| #define MG_TX_DCC_TX1LN0_PORT3 0x16A110 |
| #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 |
| #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 |
| #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 |
| #define MG_TX1_DCC(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \ |
| MG_TX_DCC_TX1LN0_PORT2, \ |
| MG_TX_DCC_TX1LN1_PORT1) |
| #define MG_TX_DCC_TX2LN0_PORT1 0x168090 |
| #define MG_TX_DCC_TX2LN1_PORT1 0x168490 |
| #define MG_TX_DCC_TX2LN0_PORT2 0x169090 |
| #define MG_TX_DCC_TX2LN1_PORT2 0x169490 |
| #define MG_TX_DCC_TX2LN0_PORT3 0x16A090 |
| #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 |
| #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 |
| #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 |
| #define MG_TX2_DCC(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \ |
| MG_TX_DCC_TX2LN0_PORT2, \ |
| MG_TX_DCC_TX2LN1_PORT1) |
| #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) |
| #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) |
| #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) |
| |
| #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 |
| #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 |
| #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 |
| #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 |
| #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 |
| #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 |
| #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 |
| #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 |
| #define MG_DP_MODE(ln, tc_port) \ |
| MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \ |
| MG_DP_MODE_LN0_ACU_PORT2, \ |
| MG_DP_MODE_LN1_ACU_PORT1) |
| #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) |
| #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) |
| |
| /* |
| * DG2 SNPS PHY registers (TC1 = PHY_E) |
| */ |
| #define _SNPS_PHY_A_BASE 0x168000 |
| #define _SNPS_PHY_B_BASE 0x169000 |
| #define _SNPS_PHY(phy) _PHY(phy, \ |
| _SNPS_PHY_A_BASE, \ |
| _SNPS_PHY_B_BASE) |
| #define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \ |
| _SNPS_PHY_A_BASE + (reg)) |
| #define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg)) |
| #define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \ |
| (reg) + (ln) * 0x10)) |
| |
| #define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000) |
| #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25) |
| #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17) |
| #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9) |
| #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1) |
| |
| #define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004) |
| #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31) |
| #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30) |
| #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29) |
| #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26) |
| #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24) |
| #define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16) |
| #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10) |
| #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9) |
| #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8) |
| #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5) |
| |
| #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008) |
| #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31) |
| #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30) |
| #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0) |
| |
| #define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C) |
| #define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16) |
| #define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0) |
| |
| #define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014) |
| #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31) |
| #define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30) |
| #define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10) |
| |
| #define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018) |
| #define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11) |
| |
| #define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C) |
| #define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18) |
| #define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15) |
| #define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12) |
| #define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0) |
| |
| #define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188) |
| #define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27) |
| |
| #define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200) |
| #define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30) |
| |
| #define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300) |
| #define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18) |
| #define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10) |
| #define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2) |
| |
| /* The spec defines this only for BXT PHY0, but lets assume that this |
| * would exist for PHY1 too if it had a second channel. |
| */ |
| #define _PORT_CL2CM_DW6_A 0x162358 |
| #define _PORT_CL2CM_DW6_BC 0x6C358 |
| #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) |
| #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) |
| |
| #define FIA1_BASE 0x163000 |
| #define FIA2_BASE 0x16E000 |
| #define FIA3_BASE 0x16F000 |
| #define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE) |
| #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) |
| |
| /* ICL PHY DFLEX registers */ |
| #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0) |
| #define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx))) |
| #define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx))) |
| #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx))) |
| #define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx))) |
| #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx))) |
| #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx))) |
| |
| /* BXT PHY Ref registers */ |
| #define _PORT_REF_DW3_A 0x16218C |
| #define _PORT_REF_DW3_BC 0x6C18C |
| #define GRC_DONE (1 << 22) |
| #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) |
| |
| #define _PORT_REF_DW6_A 0x162198 |
| #define _PORT_REF_DW6_BC 0x6C198 |
| #define GRC_CODE_SHIFT 24 |
| #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) |
| #define GRC_CODE_FAST_SHIFT 16 |
| #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) |
| #define GRC_CODE_SLOW_SHIFT 8 |
| #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) |
| #define GRC_CODE_NOM_MASK 0xFF |
| #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) |
| |
| #define _PORT_REF_DW8_A 0x1621A0 |
| #define _PORT_REF_DW8_BC 0x6C1A0 |
| #define GRC_DIS (1 << 15) |
| #define GRC_RDY_OVRD (1 << 1) |
| #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) |
| |
| /* BXT PHY PCS registers */ |
| #define _PORT_PCS_DW10_LN01_A 0x162428 |
| #define _PORT_PCS_DW10_LN01_B 0x6C428 |
| #define _PORT_PCS_DW10_LN01_C 0x6C828 |
| #define _PORT_PCS_DW10_GRP_A 0x162C28 |
| #define _PORT_PCS_DW10_GRP_B 0x6CC28 |
| #define _PORT_PCS_DW10_GRP_C 0x6CE28 |
| #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PCS_DW10_LN01_B, \ |
| _PORT_PCS_DW10_LN01_C) |
| #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PCS_DW10_GRP_B, \ |
| _PORT_PCS_DW10_GRP_C) |
| |
| #define TX2_SWING_CALC_INIT (1 << 31) |
| #define TX1_SWING_CALC_INIT (1 << 30) |
| |
| #define _PORT_PCS_DW12_LN01_A 0x162430 |
| #define _PORT_PCS_DW12_LN01_B 0x6C430 |
| #define _PORT_PCS_DW12_LN01_C 0x6C830 |
| #define _PORT_PCS_DW12_LN23_A 0x162630 |
| #define _PORT_PCS_DW12_LN23_B 0x6C630 |
| #define _PORT_PCS_DW12_LN23_C 0x6CA30 |
| #define _PORT_PCS_DW12_GRP_A 0x162c30 |
| #define _PORT_PCS_DW12_GRP_B 0x6CC30 |
| #define _PORT_PCS_DW12_GRP_C 0x6CE30 |
| #define LANESTAGGER_STRAP_OVRD (1 << 6) |
| #define LANE_STAGGER_MASK 0x1F |
| #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PCS_DW12_LN01_B, \ |
| _PORT_PCS_DW12_LN01_C) |
| #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PCS_DW12_LN23_B, \ |
| _PORT_PCS_DW12_LN23_C) |
| #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_PCS_DW12_GRP_B, \ |
| _PORT_PCS_DW12_GRP_C) |
| |
| /* BXT PHY TX registers */ |
| #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ |
| ((lane) & 1) * 0x80) |
| |
| #define _PORT_TX_DW2_LN0_A 0x162508 |
| #define _PORT_TX_DW2_LN0_B 0x6C508 |
| #define _PORT_TX_DW2_LN0_C 0x6C908 |
| #define _PORT_TX_DW2_GRP_A 0x162D08 |
| #define _PORT_TX_DW2_GRP_B 0x6CD08 |
| #define _PORT_TX_DW2_GRP_C 0x6CF08 |
| #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW2_LN0_B, \ |
| _PORT_TX_DW2_LN0_C) |
| #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW2_GRP_B, \ |
| _PORT_TX_DW2_GRP_C) |
| #define MARGIN_000_SHIFT 16 |
| #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) |
| #define UNIQ_TRANS_SCALE_SHIFT 8 |
| #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) |
| |
| #define _PORT_TX_DW3_LN0_A 0x16250C |
| #define _PORT_TX_DW3_LN0_B 0x6C50C |
| #define _PORT_TX_DW3_LN0_C 0x6C90C |
| #define _PORT_TX_DW3_GRP_A 0x162D0C |
| #define _PORT_TX_DW3_GRP_B 0x6CD0C |
| #define _PORT_TX_DW3_GRP_C 0x6CF0C |
| #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW3_LN0_B, \ |
| _PORT_TX_DW3_LN0_C) |
| #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW3_GRP_B, \ |
| _PORT_TX_DW3_GRP_C) |
| #define SCALE_DCOMP_METHOD (1 << 26) |
| #define UNIQUE_TRANGE_EN_METHOD (1 << 27) |
| |
| #define _PORT_TX_DW4_LN0_A 0x162510 |
| #define _PORT_TX_DW4_LN0_B 0x6C510 |
| #define _PORT_TX_DW4_LN0_C 0x6C910 |
| #define _PORT_TX_DW4_GRP_A 0x162D10 |
| #define _PORT_TX_DW4_GRP_B 0x6CD10 |
| #define _PORT_TX_DW4_GRP_C 0x6CF10 |
| #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW4_LN0_B, \ |
| _PORT_TX_DW4_LN0_C) |
| #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW4_GRP_B, \ |
| _PORT_TX_DW4_GRP_C) |
| #define DEEMPH_SHIFT 24 |
| #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) |
| |
| #define _PORT_TX_DW5_LN0_A 0x162514 |
| #define _PORT_TX_DW5_LN0_B 0x6C514 |
| #define _PORT_TX_DW5_LN0_C 0x6C914 |
| #define _PORT_TX_DW5_GRP_A 0x162D14 |
| #define _PORT_TX_DW5_GRP_B 0x6CD14 |
| #define _PORT_TX_DW5_GRP_C 0x6CF14 |
| #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW5_LN0_B, \ |
| _PORT_TX_DW5_LN0_C) |
| #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ |
| _PORT_TX_DW5_GRP_B, \ |
| _PORT_TX_DW5_GRP_C) |
| #define DCC_DELAY_RANGE_1 (1 << 9) |
| #define DCC_DELAY_RANGE_2 (1 << 8) |
| |
| #define _PORT_TX_DW14_LN0_A 0x162538 |
| #define _PORT_TX_DW14_LN0_B 0x6C538 |
| #define _PORT_TX_DW14_LN0_C 0x6C938 |
| #define LATENCY_OPTIM_SHIFT 30 |
| #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) |
| #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ |
| _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ |
| _PORT_TX_DW14_LN0_C) + \ |
| _BXT_LANE_OFFSET(lane)) |
| |
| /* UAIMI scratch pad register 1 */ |
| #define UAIMI_SPR1 _MMIO(0x4F074) |
| /* SKL VccIO mask */ |
| #define SKL_VCCIO_MASK 0x1 |
| /* SKL balance leg register */ |
| #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) |
| /* I_boost values */ |
| #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) |
| #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) |
| /* Balance leg disable bits */ |
| #define BALANCE_LEG_DISABLE_SHIFT 23 |
| #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) |
| |
| /* |
| * Fence registers |
| * [0-7] @ 0x2000 gen2,gen3 |
| * [8-15] @ 0x3000 945,g33,pnv |
| * |
| * [0-15] @ 0x3000 gen4,gen5 |
| * |
| * [0-15] @ 0x100000 gen6,vlv,chv |
| * [0-31] @ 0x100000 gen7+ |
| */ |
| #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) |
| #define I830_FENCE_START_MASK 0x07f80000 |
| #define I830_FENCE_TILING_Y_SHIFT 12 |
| #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
| #define I830_FENCE_PITCH_SHIFT 4 |
| #define I830_FENCE_REG_VALID (1 << 0) |
| #define I915_FENCE_MAX_PITCH_VAL 4 |
| #define I830_FENCE_MAX_PITCH_VAL 6 |
| #define I830_FENCE_MAX_SIZE_VAL (1 << 8) |
| |
| #define I915_FENCE_START_MASK 0x0ff00000 |
| #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
| |
| #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) |
| #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) |
| #define I965_FENCE_PITCH_SHIFT 2 |
| #define I965_FENCE_TILING_Y_SHIFT 1 |
| #define I965_FENCE_REG_VALID (1 << 0) |
| #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
| |
| #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) |
| #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) |
| #define GEN6_FENCE_PITCH_SHIFT 32 |
| #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
| |
| |
| /* control register for cpu gtt access */ |
| #define TILECTL _MMIO(0x101000) |
| #define TILECTL_SWZCTL (1 << 0) |
| #define TILECTL_TLBPF (1 << 1) |
| #define TILECTL_TLB_PREFETCH_DIS (1 << 2) |
| #define TILECTL_BACKSNOOP_DIS (1 << 3) |
| |
| /* |
| * Instruction and interrupt control regs |
| */ |
| #define PGTBL_CTL _MMIO(0x02020) |
| #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ |
| #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ |
| #define PGTBL_ER _MMIO(0x02024) |
| #define PRB0_BASE (0x2030 - 0x30) |
| #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ |
| #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ |
| #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ |
| #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ |
| #define SRB2_BASE (0x2120 - 0x30) /* 830 */ |
| #define SRB3_BASE (0x2130 - 0x30) /* 830 */ |
| #define RENDER_RING_BASE 0x02000 |
| #define BSD_RING_BASE 0x04000 |
| #define GEN6_BSD_RING_BASE 0x12000 |
| #define GEN8_BSD2_RING_BASE 0x1c000 |
| #define GEN11_BSD_RING_BASE 0x1c0000 |
| #define GEN11_BSD2_RING_BASE 0x1c4000 |
| #define GEN11_BSD3_RING_BASE 0x1d0000 |
| #define GEN11_BSD4_RING_BASE 0x1d4000 |
| #define XEHP_BSD5_RING_BASE 0x1e0000 |
| #define XEHP_BSD6_RING_BASE 0x1e4000 |
| #define XEHP_BSD7_RING_BASE 0x1f0000 |
| #define XEHP_BSD8_RING_BASE 0x1f4000 |
| #define VEBOX_RING_BASE 0x1a000 |
| #define GEN11_VEBOX_RING_BASE 0x1c8000 |
| #define GEN11_VEBOX2_RING_BASE 0x1d8000 |
| #define XEHP_VEBOX3_RING_BASE 0x1e8000 |
| #define XEHP_VEBOX4_RING_BASE 0x1f8000 |
| #define BLT_RING_BASE 0x22000 |
| #define RING_TAIL(base) _MMIO((base) + 0x30) |
| #define RING_HEAD(base) _MMIO((base) + 0x34) |
| #define RING_START(base) _MMIO((base) + 0x38) |
| #define RING_CTL(base) _MMIO((base) + 0x3c) |
| #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ |
| #define RING_SYNC_0(base) _MMIO((base) + 0x40) |
| #define RING_SYNC_1(base) _MMIO((base) + 0x44) |
| #define RING_SYNC_2(base) _MMIO((base) + 0x48) |
| #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) |
| #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) |
| #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) |
| #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) |
| #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) |
| #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) |
| #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) |
| #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) |
| #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) |
| #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) |
| #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) |
| #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) |
| #define GEN6_NOSYNC INVALID_MMIO_REG |
| #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) |
| #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) |
| #define RING_HWS_PGA(base) _MMIO((base) + 0x80) |
| #define RING_ID(base) _MMIO((base) + 0x8c) |
| #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) |
| |
| #define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) |
| /* |
| * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. |
| * The lsb of each can be considered a separate enabling bit for encryption. |
| * 6:0 == default MOCS value for reads => 6:1 == table index for reads. |
| * 13:7 == default MOCS value for writes => 13:8 == table index for writes. |
| * 15:14 == Reserved => 31:30 are set to 0. |
| */ |
| #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) |
| #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) |
| #define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \ |
| CMD_CCTL_READ_OVERRIDE_MASK) |
| #define CMD_CCTL_MOCS_OVERRIDE(write, read) \ |
| (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ |
| REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) |
| |
| #define BLIT_CCTL(base) _MMIO((base) + 0x204) |
| #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) |
| #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) |
| #define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \ |
| BLIT_CCTL_SRC_MOCS_MASK) |
| #define BLIT_CCTL_MOCS(dst, src) \ |
| (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \ |
| REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1)) |
| |
| #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) |
| #define RESET_CTL_CAT_ERROR REG_BIT(2) |
| #define RESET_CTL_READY_TO_RESET REG_BIT(1) |
| #define RESET_CTL_REQUEST_RESET REG_BIT(0) |
| |
| #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) |
| |
| #define HSW_GTT_CACHE_EN _MMIO(0x4024) |
| #define GTT_CACHE_EN_ALL 0xF0007FFF |
| #define GEN7_WR_WATERMARK _MMIO(0x4028) |
| #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) |
| #define ARB_MODE _MMIO(0x4030) |
| #define ARB_MODE_SWIZZLE_SNB (1 << 4) |
| #define ARB_MODE_SWIZZLE_IVB (1 << 5) |
| #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) |
| #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) |
| /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ |
| #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) |
| #define GEN7_LRA_LIMITS_REG_NUM 13 |
| #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) |
| #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) |
| |
| #define GAMTARBMODE _MMIO(0x04a08) |
| #define ARB_MODE_BWGTLB_DISABLE (1 << 9) |
| #define ARB_MODE_SWIZZLE_BDW (1 << 1) |
| #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) |
| |
| #define _RING_FAULT_REG_RCS 0x4094 |
| #define _RING_FAULT_REG_VCS 0x4194 |
| #define _RING_FAULT_REG_BCS 0x4294 |
| #define _RING_FAULT_REG_VECS 0x4394 |
| #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \ |
| _RING_FAULT_REG_RCS, \ |
| _RING_FAULT_REG_VCS, \ |
| _RING_FAULT_REG_VECS, \ |
| _RING_FAULT_REG_BCS)) |
| #define GEN8_RING_FAULT_REG _MMIO(0x4094) |
| #define GEN12_RING_FAULT_REG _MMIO(0xcec4) |
| #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) |
| #define RING_FAULT_GTTSEL_MASK (1 << 11) |
| #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) |
| #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) |
| #define RING_FAULT_VALID (1 << 0) |
| #define DONE_REG _MMIO(0x40b0) |
| #define GEN12_GAM_DONE _MMIO(0xcf68) |
| #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) |
| #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) |
| #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) |
| #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) |
| #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) |
| #define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) |
| #define GEN12_VD0_AUX_NV _MMIO(0x4218) |
| #define GEN12_VD1_AUX_NV _MMIO(0x4228) |
| #define GEN12_VD2_AUX_NV _MMIO(0x4298) |
| #define GEN12_VD3_AUX_NV _MMIO(0x42A8) |
| #define GEN12_VE0_AUX_NV _MMIO(0x4238) |
| #define GEN12_VE1_AUX_NV _MMIO(0x42B8) |
| #define AUX_INV REG_BIT(0) |
| #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) |
| #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) |
| #define RING_ACTHD(base) _MMIO((base) + 0x74) |
| #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) |
| #define RING_NOPID(base) _MMIO((base) + 0x94) |
| #define RING_IMR(base) _MMIO((base) + 0xa8) |
| #define RING_HWSTAM(base) _MMIO((base) + 0x98) |
| #define RING_TIMESTAMP(base) _MMIO((base) + 0x358) |
| #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) |
| #define TAIL_ADDR 0x001FFFF8 |
| #define HEAD_WRAP_COUNT 0xFFE00000 |
| #define HEAD_WRAP_ONE 0x00200000 |
| #define HEAD_ADDR 0x001FFFFC |
| #define RING_NR_PAGES 0x001FF000 |
| #define RING_REPORT_MASK 0x00000006 |
| #define RING_REPORT_64K 0x00000002 |
| #define RING_REPORT_128K 0x00000004 |
| #define RING_NO_REPORT 0x00000000 |
| #define RING_VALID_MASK 0x00000001 |
| #define RING_VALID 0x00000001 |
| #define RING_INVALID 0x00000000 |
| #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ |
| #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ |
| #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ |
| |
| /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ |
| #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) |
| #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) |
| |
| #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) |
| #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) |
| #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ |
| #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) |
| #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) |
| #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) |
| #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) |
| #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ |
| #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) |
| #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) |
| #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) |
| #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) |
| #define RING_FORCE_TO_NONPRIV_MASK_VALID \ |
| (RING_FORCE_TO_NONPRIV_RANGE_MASK \ |
| | RING_FORCE_TO_NONPRIV_ACCESS_MASK) |
| #define RING_MAX_NONPRIV_SLOTS 12 |
| |
| #define GEN7_TLB_RD_ADDR _MMIO(0x4700) |
| |
| #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) |
| #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) |
| |
| #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) |
| #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF |
| #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) |
| |
| #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) |
| #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) |
| #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) |
| #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) |
| |
| #if 0 |
| #define PRB0_TAIL _MMIO(0x2030) |
| #define PRB0_HEAD _MMIO(0x2034) |
| #define PRB0_START _MMIO(0x2038) |
| #define PRB0_CTL _MMIO(0x203c) |
| #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ |
| #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ |
| #define PRB1_START _MMIO(0x2048) /* 915+ only */ |
| #define PRB1_CTL _MMIO(0x204c) /* 915+ only */ |
| #endif |
| #define IPEIR_I965 _MMIO(0x2064) |
| #define IPEHR_I965 _MMIO(0x2068) |
| #define GEN7_SC_INSTDONE _MMIO(0x7100) |
| #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) |
| #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) |
| #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) |
| #define GEN7_ROW_INSTDONE _MMIO(0xe164) |
| #define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c) |
| #define MCFG_MCR_SELECTOR _MMIO(0xfd0) |
| #define SF_MCR_SELECTOR _MMIO(0xfd8) |
| #define GEN8_MCR_SELECTOR _MMIO(0xfdc) |
| #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) |
| #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) |
| #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) |
| #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) |
| #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) |
| #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) |
| #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) |
| #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) |
| #define RING_IPEIR(base) _MMIO((base) + 0x64) |
| #define RING_IPEHR(base) _MMIO((base) + 0x68) |
| #define RING_EIR(base) _MMIO((base) + 0xb0) |
| #define RING_EMR(base) _MMIO((base) + 0xb4) |
| #define RING_ESR(base) _MMIO((base) + 0xb8) |
| /* |
| * On GEN4, only the render ring INSTDONE exists and has a different |
| * layout than the GEN7+ version. |
| * The GEN2 counterpart of this register is GEN2_INSTDONE. |
| */ |
| #define RING_INSTDONE(base) _MMIO((base) + 0x6c) |
| #define RING_INSTPS(base) _MMIO((base) + 0x70) |
| #define RING_DMA_FADD(base) _MMIO((base) + 0x78) |
| #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ |
| #define RING_INSTPM(base) _MMIO((base) + 0xc0) |
| #define RING_MI_MODE(base) _MMIO((base) + 0x9c) |
| #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) |
| #define INSTPS _MMIO(0x2070) /* 965+ only */ |
| #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ |
| #define ACTHD_I965 _MMIO(0x2074) |
| #define HWS_PGA _MMIO(0x2080) |
| #define HWS_ADDRESS_MASK 0xfffff000 |
| #define HWS_START_ADDRESS_SHIFT 4 |
| #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ |
| #define PWRCTX_EN (1 << 0) |
| #define IPEIR(base) _MMIO((base) + 0x88) |
| #define IPEHR(base) _MMIO((base) + 0x8c) |
| #define GEN2_INSTDONE _MMIO(0x2090) |
| #define NOPID _MMIO(0x2094) |
| #define HWSTAM _MMIO(0x2098) |
| #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) |
| #define RING_BBSTATE(base) _MMIO((base) + 0x110) |
| #define RING_BB_PPGTT (1 << 5) |
| #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ |
| #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ |
| #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ |
| #define RING_BBADDR(base) _MMIO((base) + 0x140) |
| #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ |
| #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ |
| #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ |
| #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ |
| #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ |
| |
| #define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) |
| #define IECPUNIT_CLKGATE_DIS REG_BIT(22) |
| |
| #define ERROR_GEN6 _MMIO(0x40a0) |
| #define GEN7_ERR_INT _MMIO(0x44040) |
| #define ERR_INT_POISON (1 << 31) |
| #define ERR_INT_MMIO_UNCLAIMED (1 << 13) |
| #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) |
| #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) |
| #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) |
| #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) |
| #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) |
| #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) |
| #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) |
| #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) |
| |
| #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) |
| #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) |
| #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) |
| #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) |
| #define FAULT_VA_HIGH_BITS (0xf << |