| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
| // |
| // This file is provided under a dual BSD/GPLv2 license. When using or |
| // redistributing this file, you may do so under either license. |
| // |
| // Copyright(c) 2018 Intel Corporation. All rights reserved. |
| // |
| // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> |
| // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> |
| // Rander Wang <rander.wang@intel.com> |
| // Keyon Jie <yang.jie@linux.intel.com> |
| // |
| |
| /* |
| * Hardware interface for audio DSP on Cannonlake. |
| */ |
| |
| #include "../ops.h" |
| #include "hda.h" |
| #include "hda-ipc.h" |
| #include "../sof-audio.h" |
| |
| static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = { |
| {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| }; |
| |
| static void cnl_ipc_host_done(struct snd_sof_dev *sdev); |
| static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev); |
| |
| irqreturn_t cnl_ipc_irq_thread(int irq, void *context) |
| { |
| struct snd_sof_dev *sdev = context; |
| u32 hipci; |
| u32 hipcida; |
| u32 hipctdr; |
| u32 hipctdd; |
| u32 msg; |
| u32 msg_ext; |
| bool ipc_irq = false; |
| |
| hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); |
| hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); |
| hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD); |
| hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR); |
| |
| /* reply message from DSP */ |
| if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) { |
| msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK; |
| msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK; |
| |
| dev_vdbg(sdev->dev, |
| "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n", |
| msg, msg_ext); |
| |
| /* mask Done interrupt */ |
| snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, |
| CNL_DSP_REG_HIPCCTL, |
| CNL_DSP_REG_HIPCCTL_DONE, 0); |
| |
| spin_lock_irq(&sdev->ipc_lock); |
| |
| /* handle immediate reply from DSP core */ |
| hda_dsp_ipc_get_reply(sdev); |
| snd_sof_ipc_reply(sdev, msg); |
| |
| cnl_ipc_dsp_done(sdev); |
| |
| spin_unlock_irq(&sdev->ipc_lock); |
| |
| ipc_irq = true; |
| } |
| |
| /* new message from DSP */ |
| if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) { |
| msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK; |
| msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK; |
| |
| dev_vdbg(sdev->dev, |
| "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n", |
| msg, msg_ext); |
| |
| /* handle messages from DSP */ |
| if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) == |
| SOF_IPC_PANIC_MAGIC) { |
| snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext)); |
| } else { |
| snd_sof_ipc_msgs_rx(sdev); |
| } |
| |
| cnl_ipc_host_done(sdev); |
| |
| ipc_irq = true; |
| } |
| |
| if (!ipc_irq) { |
| /* |
| * This interrupt is not shared so no need to return IRQ_NONE. |
| */ |
| dev_dbg_ratelimited(sdev->dev, |
| "nothing to do in IPC IRQ thread\n"); |
| } |
| |
| return IRQ_HANDLED; |
| } |
| |
| static void cnl_ipc_host_done(struct snd_sof_dev *sdev) |
| { |
| /* |
| * clear busy interrupt to tell dsp controller this |
| * interrupt has been accepted, not trigger it again |
| */ |
| snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, |
| CNL_DSP_REG_HIPCTDR, |
| CNL_DSP_REG_HIPCTDR_BUSY, |
| CNL_DSP_REG_HIPCTDR_BUSY); |
| /* |
| * set done bit to ack dsp the msg has been |
| * processed and send reply msg to dsp |
| */ |
| snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, |
| CNL_DSP_REG_HIPCTDA, |
| CNL_DSP_REG_HIPCTDA_DONE, |
| CNL_DSP_REG_HIPCTDA_DONE); |
| } |
| |
| static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev) |
| { |
| /* |
| * set DONE bit - tell DSP we have received the reply msg |
| * from DSP, and processed it, don't send more reply to host |
| */ |
| snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, |
| CNL_DSP_REG_HIPCIDA, |
| CNL_DSP_REG_HIPCIDA_DONE, |
| CNL_DSP_REG_HIPCIDA_DONE); |
| |
| /* unmask Done interrupt */ |
| snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, |
| CNL_DSP_REG_HIPCCTL, |
| CNL_DSP_REG_HIPCCTL_DONE, |
| CNL_DSP_REG_HIPCCTL_DONE); |
| } |
| |
| static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg, |
| u32 *dr, u32 *dd) |
| { |
| struct sof_ipc_pm_gate *pm_gate; |
| |
| if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) { |
| pm_gate = msg->msg_data; |
| |
| /* send the compact message via the primary register */ |
| *dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE; |
| |
| /* send payload via the extended data register */ |
| *dd = pm_gate->flags; |
| |
| return true; |
| } |
| |
| return false; |
| } |
| |
| int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) |
| { |
| struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; |
| struct sof_ipc_cmd_hdr *hdr; |
| u32 dr = 0; |
| u32 dd = 0; |
| |
| /* |
| * Currently the only compact IPC supported is the PM_GATE |
| * IPC which is used for transitioning the DSP between the |
| * D0I0 and D0I3 states. And these are sent only during the |
| * set_power_state() op. Therefore, there will never be a case |
| * that a compact IPC results in the DSP exiting D0I3 without |
| * the host and FW being in sync. |
| */ |
| if (cnl_compact_ipc_compress(msg, &dr, &dd)) { |
| /* send the message via IPC registers */ |
| snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD, |
| dd); |
| snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, |
| CNL_DSP_REG_HIPCIDR_BUSY | dr); |
| return 0; |
| } |
| |
| /* send the message via mailbox */ |
| sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, |
| msg->msg_size); |
| snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR, |
| CNL_DSP_REG_HIPCIDR_BUSY); |
| |
| hdr = msg->msg_data; |
| |
| /* |
| * Use mod_delayed_work() to schedule the delayed work |
| * to avoid scheduling multiple workqueue items when |
| * IPCs are sent at a high-rate. mod_delayed_work() |
| * modifies the timer if the work is pending. |
| * Also, a new delayed work should not be queued after the |
| * CTX_SAVE IPC, which is sent before the DSP enters D3. |
| */ |
| if (hdr->cmd != (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE)) |
| mod_delayed_work(system_wq, &hdev->d0i3_work, |
| msecs_to_jiffies(SOF_HDA_D0I3_WORK_DELAY_MS)); |
| |
| return 0; |
| } |
| |
| void cnl_ipc_dump(struct snd_sof_dev *sdev) |
| { |
| u32 hipcctl; |
| u32 hipcida; |
| u32 hipctdr; |
| |
| hda_ipc_irq_dump(sdev); |
| |
| /* read IPC status */ |
| hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA); |
| hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL); |
| hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR); |
| |
| /* dump the IPC regs */ |
| /* TODO: parse the raw msg */ |
| dev_err(sdev->dev, |
| "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", |
| hipcida, hipctdr, hipcctl); |
| } |
| |
| /* cannonlake ops */ |
| const struct snd_sof_dsp_ops sof_cnl_ops = { |
| /* probe/remove/shutdown */ |
| .probe = hda_dsp_probe, |
| .remove = hda_dsp_remove, |
| .shutdown = hda_dsp_shutdown, |
| |
| /* Register IO */ |
| .write = sof_io_write, |
| .read = sof_io_read, |
| .write64 = sof_io_write64, |
| .read64 = sof_io_read64, |
| |
| /* Block IO */ |
| .block_read = sof_block_read, |
| .block_write = sof_block_write, |
| |
| /* Mailbox IO */ |
| .mailbox_read = sof_mailbox_read, |
| .mailbox_write = sof_mailbox_write, |
| |
| /* doorbell */ |
| .irq_thread = cnl_ipc_irq_thread, |
| |
| /* ipc */ |
| .send_msg = cnl_ipc_send_msg, |
| .fw_ready = sof_fw_ready, |
| .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, |
| .get_window_offset = hda_dsp_ipc_get_window_offset, |
| |
| .ipc_msg_data = hda_ipc_msg_data, |
| .ipc_pcm_params = hda_ipc_pcm_params, |
| |
| /* machine driver */ |
| .machine_select = hda_machine_select, |
| .machine_register = sof_machine_register, |
| .machine_unregister = sof_machine_unregister, |
| .set_mach_params = hda_set_mach_params, |
| |
| /* debug */ |
| .debug_map = cnl_dsp_debugfs, |
| .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs), |
| .dbg_dump = hda_dsp_dump, |
| .ipc_dump = cnl_ipc_dump, |
| .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, |
| |
| /* stream callbacks */ |
| .pcm_open = hda_dsp_pcm_open, |
| .pcm_close = hda_dsp_pcm_close, |
| .pcm_hw_params = hda_dsp_pcm_hw_params, |
| .pcm_hw_free = hda_dsp_stream_hw_free, |
| .pcm_trigger = hda_dsp_pcm_trigger, |
| .pcm_pointer = hda_dsp_pcm_pointer, |
| |
| #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES) |
| /* probe callbacks */ |
| .probe_assign = hda_probe_compr_assign, |
| .probe_free = hda_probe_compr_free, |
| .probe_set_params = hda_probe_compr_set_params, |
| .probe_trigger = hda_probe_compr_trigger, |
| .probe_pointer = hda_probe_compr_pointer, |
| #endif |
| |
| /* firmware loading */ |
| .load_firmware = snd_sof_load_firmware_raw, |
| |
| /* pre/post fw run */ |
| .pre_fw_run = hda_dsp_pre_fw_run, |
| .post_fw_run = hda_dsp_post_fw_run, |
| |
| /* parse platform specific extended manifest */ |
| .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data, |
| |
| /* dsp core power up/down */ |
| .core_power_up = hda_dsp_enable_core, |
| .core_power_down = hda_dsp_core_reset_power_down, |
| |
| /* firmware run */ |
| .run = hda_dsp_cl_boot_firmware, |
| |
| /* trace callback */ |
| .trace_init = hda_dsp_trace_init, |
| .trace_release = hda_dsp_trace_release, |
| .trace_trigger = hda_dsp_trace_trigger, |
| |
| /* DAI drivers */ |
| .drv = skl_dai, |
| .num_drv = SOF_SKL_NUM_DAIS, |
| |
| /* PM */ |
| .suspend = hda_dsp_suspend, |
| .resume = hda_dsp_resume, |
| .runtime_suspend = hda_dsp_runtime_suspend, |
| .runtime_resume = hda_dsp_runtime_resume, |
| .runtime_idle = hda_dsp_runtime_idle, |
| .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, |
| .set_power_state = hda_dsp_set_power_state, |
| |
| /* ALSA HW info flags */ |
| .hw_info = SNDRV_PCM_INFO_MMAP | |
| SNDRV_PCM_INFO_MMAP_VALID | |
| SNDRV_PCM_INFO_INTERLEAVED | |
| SNDRV_PCM_INFO_PAUSE | |
| SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, |
| |
| .dsp_arch_ops = &sof_xtensa_arch_ops, |
| }; |
| EXPORT_SYMBOL_NS(sof_cnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); |
| |
| const struct sof_intel_dsp_desc cnl_chip_info = { |
| /* Cannonlake */ |
| .cores_num = 4, |
| .init_core_mask = 1, |
| .host_managed_cores_mask = GENMASK(3, 0), |
| .ipc_req = CNL_DSP_REG_HIPCIDR, |
| .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
| .ipc_ack = CNL_DSP_REG_HIPCIDA, |
| .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
| .ipc_ctl = CNL_DSP_REG_HIPCCTL, |
| .rom_init_timeout = 300, |
| .ssp_count = CNL_SSP_COUNT, |
| .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
| .sdw_shim_base = SDW_SHIM_BASE, |
| .sdw_alh_base = SDW_ALH_BASE, |
| .check_sdw_irq = hda_common_check_sdw_irq, |
| }; |
| EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |
| |
| const struct sof_intel_dsp_desc jsl_chip_info = { |
| /* Jasperlake */ |
| .cores_num = 2, |
| .init_core_mask = 1, |
| .host_managed_cores_mask = GENMASK(1, 0), |
| .ipc_req = CNL_DSP_REG_HIPCIDR, |
| .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
| .ipc_ack = CNL_DSP_REG_HIPCIDA, |
| .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
| .ipc_ctl = CNL_DSP_REG_HIPCCTL, |
| .rom_init_timeout = 300, |
| .ssp_count = ICL_SSP_COUNT, |
| .ssp_base_offset = CNL_SSP_BASE_OFFSET, |
| .sdw_shim_base = SDW_SHIM_BASE, |
| .sdw_alh_base = SDW_ALH_BASE, |
| .check_sdw_irq = hda_common_check_sdw_irq, |
| }; |
| EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |