tree b6332377945fa655317bafa2cb4eaa0b134cb600
parent 8f5d481959a04ad81cc928c698ebe6a9dae23971
author Fancy Fang <chen.fang@nxp.com> 1572250079 +0000
committer Shawn Guo <shawnguo@kernel.org> 1572262357 +0800

clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock

The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.

MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.

So it should be used only for MIPI DSI and not be exported
out for other usages.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>