/*
 * Device Tree Source for the r8a7793 SoC
 *
 * Copyright (C) 2014-2015 Renesas Electronics Corporation
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7793-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7793";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		spi0 = &qspi;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1500000000>;
			voltage-tolerance = <1>; /* 1% */
			clocks = <&cpg_clocks R8A7793_CLK_Z>;
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1500000 1000000>,
					   <1312500 1000000>,
					   <1125000 1000000>,
					   < 937500 1000000>,
					   < 750000 1000000>,
					   < 375000 1000000>;
			next-level-cache = <&L2_CA15>;
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive	= <0>;
			polling-delay		= <0>;

			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature	= <115000>;
					hysteresis	= <0>;
					type		= "critical";
				};
			};
			cooling-maps {
			};
		};
	};

	L2_CA15: cache-controller@0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gpio0: gpio@e6050000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6050000 0 0x50>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
		power-domains = <&cpg_clocks>;
	};

	gpio1: gpio@e6051000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6051000 0 0x50>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 26>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
		power-domains = <&cpg_clocks>;
	};

	gpio2: gpio@e6052000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6052000 0 0x50>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
		power-domains = <&cpg_clocks>;
	};

	gpio3: gpio@e6053000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6053000 0 0x50>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
		power-domains = <&cpg_clocks>;
	};

	gpio4: gpio@e6054000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6054000 0 0x50>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
		power-domains = <&cpg_clocks>;
	};

	gpio5: gpio@e6055000 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6055000 0 0x50>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
		power-domains = <&cpg_clocks>;
	};

	gpio6: gpio@e6055400 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6055400 0 0x50>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
		power-domains = <&cpg_clocks>;
	};

	gpio7: gpio@e6055800 {
		compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
		reg = <0 0xe6055800 0 0x50>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 224 26>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
		power-domains = <&cpg_clocks>;
	};

	thermal: thermal@e61f0000 {
		compatible =	"renesas,thermal-r8a7793",
				"renesas,rcar-gen2-thermal",
				"renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
		power-domains = <&cpg_clocks>;
		#thermal-sensor-cells = <0>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	cmt0: timer@ffca0000 {
		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
		reg = <0 0xffca0000 0 0x1004>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		renesas,channels-mask = <0x60>;

		status = "disabled";
	};

	cmt1: timer@e6130000 {
		compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
		reg = <0 0xe6130000 0 0x1004>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		renesas,channels-mask = <0xff>;

		status = "disabled";
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc-r8a7793", "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
		power-domains = <&cpg_clocks>;
	};

	dmac0: dma-controller@e6700000 {
		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
		reg = <0 0xe6700000 0 0x20000>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12", "ch13", "ch14";
		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		#dma-cells = <1>;
		dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
		reg = <0 0xe6720000 0 0x20000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12", "ch13", "ch14";
		clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		#dma-cells = <1>;
		dma-channels = <15>;
	};

	audma0: dma-controller@ec700000 {
		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
		reg = <0 0xec700000 0 0x10000>;
		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12";
		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		#dma-cells = <1>;
		dma-channels = <13>;
	};

	audma1: dma-controller@ec720000 {
		compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
		reg = <0 0xec720000 0 0x10000>;
		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12";
		clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		#dma-cells = <1>;
		dma-channels = <13>;
	};

	/* The memory map in the User's Manual maps the cores to bus numbers */
	i2c0: i2c@e6508000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6508000 0 0x40>;
		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <6>;
		status = "disabled";
	};

	i2c1: i2c@e6518000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6518000 0 0x40>;
		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <6>;
		status = "disabled";
	};

	i2c2: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6530000 0 0x40>;
		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <6>;
		status = "disabled";
	};

	i2c3: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6540000 0 0x40>;
		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <6>;
		status = "disabled";
	};

	i2c4: i2c@e6520000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6520000 0 0x40>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <6>;
		status = "disabled";
	};

	i2c5: i2c@e6528000 {
		/* doesn't need pinmux */
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7793";
		reg = <0 0xe6528000 0 0x40>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <110>;
		status = "disabled";
	};

	i2c6: i2c@e60b0000 {
		/* doesn't need pinmux */
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
		reg = <0 0xe60b0000 0 0x425>;
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
		dmas = <&dmac0 0x77>, <&dmac0 0x78>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c7: i2c@e6500000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
		reg = <0 0xe6500000 0 0x425>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
		dmas = <&dmac0 0x61>, <&dmac0 0x62>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c8: i2c@e6510000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
		reg = <0 0xe6510000 0 0x425>;
		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
		dmas = <&dmac0 0x65>, <&dmac0 0x66>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	pfc: pfc@e6060000 {
		compatible = "renesas,pfc-r8a7793";
		reg = <0 0xe6060000 0 0x250>;
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c40000 0 64>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
		clock-names = "fck";
		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c50000 0 64>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
		clock-names = "fck";
		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c60000 0 64>;
		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
		clock-names = "fck";
		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c70000 0 64>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
		clock-names = "fck";
		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifa4: serial@e6c78000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c78000 0 64>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
		clock-names = "fck";
		dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifa5: serial@e6c80000 {
		compatible = "renesas,scifa-r8a7793",
			     "renesas,rcar-gen2-scifa", "renesas,scifa";
		reg = <0 0xe6c80000 0 64>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
		clock-names = "fck";
		dmas = <&dmac0 0x23>, <&dmac0 0x24>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifb0: serial@e6c20000 {
		compatible = "renesas,scifb-r8a7793",
			     "renesas,rcar-gen2-scifb", "renesas,scifb";
		reg = <0 0xe6c20000 0 64>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
		clock-names = "fck";
		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifb1: serial@e6c30000 {
		compatible = "renesas,scifb-r8a7793",
			     "renesas,rcar-gen2-scifb", "renesas,scifb";
		reg = <0 0xe6c30000 0 64>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
		clock-names = "fck";
		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scifb2: serial@e6ce0000 {
		compatible = "renesas,scifb-r8a7793",
			     "renesas,rcar-gen2-scifb", "renesas,scifb";
		reg = <0 0xe6ce0000 0 64>;
		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
		clock-names = "fck";
		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif0: serial@e6e60000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6e60000 0 64>;
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@e6e68000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6e68000 0 64>;
		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@e6e58000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6e58000 0 64>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@e6ea8000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6ea8000 0 64>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@e6ee0000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6ee0000 0 64>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@e6ee8000 {
		compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
			     "renesas,scif";
		reg = <0 0xe6ee8000 0 64>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hscif0: serial@e62c0000 {
		compatible = "renesas,hscif-r8a7793",
			     "renesas,rcar-gen2-hscif", "renesas,hscif";
		reg = <0 0xe62c0000 0 96>;
		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hscif1: serial@e62c8000 {
		compatible = "renesas,hscif-r8a7793",
			     "renesas,rcar-gen2-hscif", "renesas,hscif";
		reg = <0 0xe62c8000 0 96>;
		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hscif2: serial@e62d0000 {
		compatible = "renesas,hscif-r8a7793",
			     "renesas,rcar-gen2-hscif", "renesas,hscif";
		reg = <0 0xe62d0000 0 96>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	ether: ethernet@ee700000 {
		compatible = "renesas,ether-r8a7793";
		reg = <0 0xee700000 0 0x400>;
		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
		power-domains = <&cpg_clocks>;
		phy-mode = "rmii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	qspi: spi@e6b10000 {
		compatible = "renesas,qspi-r8a7793", "renesas,qspi";
		reg = <0 0xe6b10000 0 0x2c>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
		dmas = <&dmac0 0x17>, <&dmac0 0x18>;
		dma-names = "tx", "rx";
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	du: display@feb00000 {
		compatible = "renesas,du-r8a7793";
		reg = <0 0xfeb00000 0 0x40000>,
		      <0 0xfeb90000 0 0x1c>;
		reg-names = "du", "lvds.0";
		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7793_CLK_DU0>,
			 <&mstp7_clks R8A7793_CLK_DU1>,
			 <&mstp7_clks R8A7793_CLK_LVDS0>;
		clock-names = "du.0", "du.1", "lvds.0";
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_lvds0: endpoint {
				};
			};
		};
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* External root clock */
		extal_clk: extal_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
			clock-output-names = "extal";
		};

		/*
		 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
		 * default. Boards that provide audio clocks should override them.
		 */
		audio_clk_a: audio_clk_a {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_a";
		};
		audio_clk_b: audio_clk_b {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_b";
		};
		audio_clk_c: audio_clk_c {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "audio_clk_c";
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
			status = "disabled";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,r8a7793-cpg-clocks",
				     "renesas,rcar-gen2-cpg-clocks";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll3",
					     "lb", "qspi", "sdh", "sd0", "z",
					     "rcan", "adsp";
			#power-domain-cells = <0>;
		};

		/* Variable factor clocks */
		sd2_clk: sd2_clk@e6150078 {
			compatible = "renesas,r8a7793-div6-clock",
				     "renesas,cpg-div6-clock";
			reg = <0 0xe6150078 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd2";
		};
		sd3_clk: sd3_clk@e615026c {
			compatible = "renesas,r8a7793-div6-clock",
				     "renesas,cpg-div6-clock";
			reg = <0 0xe615026c 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd3";
		};
		mmc0_clk: mmc0_clk@e6150240 {
			compatible = "renesas,r8a7793-div6-clock",
				     "renesas,cpg-div6-clock";
			reg = <0 0xe6150240 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mmc0";
		};

		/* Fixed factor clocks */
		pll1_div2_clk: pll1_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "pll1_div2";
		};
		zg_clk: zg_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <5>;
			clock-mult = <1>;
			clock-output-names = "zg";
		};
		zx_clk: zx_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <3>;
			clock-mult = <1>;
			clock-output-names = "zx";
		};
		zs_clk: zs_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <6>;
			clock-mult = <1>;
			clock-output-names = "zs";
		};
		hp_clk: hp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
			clock-output-names = "hp";
		};
		p_clk: p_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
			clock-output-names = "p";
		};
		m2_clk: m2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "m2";
		};
		rclk_clk: rclk_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <(48 * 1024)>;
			clock-mult = <1>;
			clock-output-names = "rclk";
		};
		mp_clk: mp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-div = <15>;
			clock-mult = <1>;
			clock-output-names = "mp";
		};
		cp_clk: cp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&extal_clk>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "cp";
		};

		/* Gate clocks */
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,r8a7793-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
			clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
				 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
				 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
				 <&zs_clk>, <&zs_clk>, <&zs_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
				R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
				R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
				R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
				R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
				R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
				R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
				R8A7793_CLK_VSP1_S
			>;
			clock-output-names =
				"vcp0", "vpc0", "ssp_dev", "tmu1",
				"pvrsrvkm", "tddmac", "fdp1", "fdp0",
				"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
				"vsp1-du0", "vsps";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
				 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
				R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
				R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
			>;
			clock-output-names =
				"scifa2", "scifa1", "scifa0", "scifb0",
				"scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,r8a7793-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
			clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
				 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
				 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
				R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
				R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
				R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
				R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
				R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
			>;
			clock-output-names =
				"tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
				"i2c7", "pciec", "i2c8", "ssusb", "cmt1",
				"usbdmac0", "usbdmac1";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
			clocks = <&cp_clk>;
			#clock-cells = <1>;
			clock-indices = <R8A7793_CLK_IRQC>;
			clock-output-names = "irqc";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
			clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
			#clock-cells = <1>;
			clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
					 R8A7793_CLK_THERMAL>;
			clock-output-names = "audmac0", "audmac1", "thermal";
		};
		mstp7_clks: mstp7_clks@e615014c {
			compatible = "renesas,r8a7793-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
			clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
				 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
				 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
				 <&zx_clk>, <&zx_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
				R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
				R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
				R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
				R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
				R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
				R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
			>;
			clock-output-names =
				"ehci", "hsusb", "hscif2", "scif5", "scif4",
				"hscif1", "hscif0", "scif3", "scif2",
				"scif1", "scif0", "du1", "du0", "lvds0";
		};
		mstp8_clks: mstp8_clks@e6150990 {
			compatible = "renesas,r8a7793-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
			clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
				 <&p_clk>, <&zs_clk>, <&zs_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
				R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
				R8A7793_CLK_ETHER R8A7793_CLK_SATA1
				R8A7793_CLK_SATA0
			>;
			clock-output-names =
				"ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
				"sata1", "sata0";
		};
		mstp9_clks: mstp9_clks@e6150994 {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
				 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
				 <&hp_clk>, <&hp_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
				R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
				R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
				R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
				R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
				R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
				R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
				R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
			>;
			clock-output-names =
				"gpio7", "gpio6", "gpio5", "gpio4",
				"gpio3", "gpio2", "gpio1", "gpio0",
				"qspi_mod", "i2c5", "i2c6", "i2c4",
				"i2c3", "i2c2", "i2c1", "i2c0";
		};
		mstp10_clks: mstp10_clks@e6150998 {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
			clocks = <&p_clk>,
				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
				<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
				<&p_clk>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
				<&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;

			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_SSI_ALL
				R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
				R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
				R8A7793_CLK_SCU_ALL
				R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
				R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
				R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
				R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
			>;
			clock-output-names =
				"ssi-all",
				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
				"scu-all",
				"scu-dvc1", "scu-dvc0",
				"scu-ctu1-mix1", "scu-ctu0-mix0",
				"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
				"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
		};
		mstp11_clks: mstp11_clks@e615099c {
			compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
			>;
			clock-output-names = "scifa3", "scifa4", "scifa5";
		};
	};

	ipmmu_sy0: mmu@e6280000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xe6280000 0 0x1000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_sy1: mmu@e6290000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xe6290000 0 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_ds: mmu@e6740000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xe6740000 0 0x1000>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_mp: mmu@ec680000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xec680000 0 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_mx: mmu@fe951000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xfe951000 0 0x1000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_rt: mmu@ffc80000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xffc80000 0 0x1000>;
		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	ipmmu_gp: mmu@e62a0000 {
		compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
		reg = <0 0xe62a0000 0 0x1000>;
		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		status = "disabled";
	};

	rcar_sound: sound@ec500000 {
		/*
		 * #sound-dai-cells is required
		 *
		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
		 */
		compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
		reg =	<0 0xec500000 0 0x1000>, /* SCU */
			<0 0xec5a0000 0 0x100>,  /* ADG */
			<0 0xec540000 0 0x1000>, /* SSIU */
			<0 0xec541000 0 0x280>,  /* SSI */
			<0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
		reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

		clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
			<&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
			<&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
			<&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
			<&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
			<&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
			<&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
			<&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
			<&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
			<&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
			<&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
			<&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
		clock-names = "ssi-all",
				"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
				"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
				"src.9", "src.8", "src.7", "src.6", "src.5",
				"src.4", "src.3", "src.2", "src.1", "src.0",
				"dvc.0", "dvc.1",
				"clk_a", "clk_b", "clk_c", "clk_i";
		power-domains = <&cpg_clocks>;

		status = "disabled";

		rcar_sound,dvc {
			dvc0: dvc@0 {
				dmas = <&audma0 0xbc>;
				dma-names = "tx";
			};
			dvc1: dvc@1 {
				dmas = <&audma0 0xbe>;
				dma-names = "tx";
			};
		};

		rcar_sound,src {
			src0: src@0 {
				interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x85>, <&audma1 0x9a>;
				dma-names = "rx", "tx";
			};
			src1: src@1 {
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x87>, <&audma1 0x9c>;
				dma-names = "rx", "tx";
			};
			src2: src@2 {
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x89>, <&audma1 0x9e>;
				dma-names = "rx", "tx";
			};
			src3: src@3 {
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x8b>, <&audma1 0xa0>;
				dma-names = "rx", "tx";
			};
			src4: src@4 {
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x8d>, <&audma1 0xb0>;
				dma-names = "rx", "tx";
			};
			src5: src@5 {
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x8f>, <&audma1 0xb2>;
				dma-names = "rx", "tx";
			};
			src6: src@6 {
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x91>, <&audma1 0xb4>;
				dma-names = "rx", "tx";
			};
			src7: src@7 {
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x93>, <&audma1 0xb6>;
				dma-names = "rx", "tx";
			};
			src8: src@8 {
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x95>, <&audma1 0xb8>;
				dma-names = "rx", "tx";
			};
			src9: src@9 {
				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x97>, <&audma1 0xba>;
				dma-names = "rx", "tx";
			};
		};

		rcar_sound,ssi {
			ssi0: ssi@0 {
				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi1: ssi@1 {
				 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi2: ssi@2 {
				interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi3: ssi@3 {
				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi4: ssi@4 {
				interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi5: ssi@5 {
				interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi6: ssi@6 {
				interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi7: ssi@7 {
				interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi8: ssi@8 {
				interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
			ssi9: ssi@9 {
				interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
				dma-names = "rx", "tx", "rxu", "txu";
			};
		};
	};
};