// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"

/ {
	chosen {
		stdout-path = &uart2;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "yellow:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	hdmi-connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&adv7533_out>;
			};
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <12000>;
		enable-active-high;
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ir>;
		linux,autosuspend-period = <125>;
	};

	audio_codec_bt_sco: audio-codec-bt-sco {
		compatible = "linux,bt-sco";
		#sound-dai-cells = <1>;
	};

	wm8524: audio-codec {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8524";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_wlf>;
		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
	};

	sound-bt-sco {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bt-sco-audio";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,bitclock-inversion;
		simple-audio-card,frame-master = <&btcpu>;
		simple-audio-card,bitclock-master = <&btcpu>;

		btcpu: simple-audio-card,cpu {
			sound-dai = <&sai2>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <16>;
		};

		simple-audio-card,codec {
			sound-dai = <&audio_codec_bt_sco 1>;
		};
	};

	sound-wm8524 {
		compatible = "fsl,imx-audio-wm8524";
		model = "wm8524-audio";
		audio-cpu = <&sai3>;
		audio-codec = <&wm8524>;
		audio-asrc = <&easrc>;
		audio-routing =
			"Line Out Jack", "LINEVOUTL",
			"Line Out Jack", "LINEVOUTR";
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif1>;
		spdif-out;
		spdif-in;
	};

	sound-micfil {
		compatible = "fsl,imx-audio-card";
		model = "micfil-audio";

		pri-dai-link {
			link-name = "micfil hifi";
			format = "i2s";

			cpu {
				sound-dai = <&micfil>;
			};
		};
	};
};

&easrc {
	fsl,asrc-rate = <48000>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			qca,disable-smarteee;
			vddio-supply = <&vddio>;

			vddio: vddio-regulator {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <166000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	hdmi@3d {
		compatible = "adi,adv7535";
		reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
		reg-names = "main", "cec", "edid", "packet";
		adi,dsi-lanes = <4>;

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";
		adi,input-style = <1>;
		adi,input-justification = "evenly";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				adv7533_in: endpoint {
					remote-endpoint = <&dsi_out>;
				};
			};

			port@1 {
				reg = <1>;

				adv7533_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};

		};
	};

	ptn5110: tcpc@50 {
		compatible = "nxp,ptn5110";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec1>;
		reg = <0x50>;
		interrupt-parent = <&gpio2>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		typec1_con: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			power-role = "dual";
			data-role = "dual";
			try-power-role = "sink";
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
				     PDO_VAR(5000, 20000, 3000)>;
			op-sink-microwatt = <15000000>;
			self-powered;

			port {
				typec1_dr_sw: endpoint {
					remote-endpoint = <&usb1_drd_sw>;
				};
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	camera@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_camera>;
		clocks = <&clk IMX8MN_CLK_CLKO1>;
		clock-names = "xclk";
		assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
		assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
		assigned-clock-rates = <24000000>;
		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;

		port {
			ov5640_to_mipi_csi2: endpoint {
				remote-endpoint = <&imx8mn_mipi_csi_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};
};

&isi {
	status = "okay";
};

&micfil {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pdm>;
	assigned-clocks = <&clk IMX8MN_CLK_PDM>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <196608000>;
	status = "okay";
};

&mipi_csi {
	status = "okay";

	ports {
		port@0 {
			imx8mn_mipi_csi_in: endpoint {
				remote-endpoint = <&ov5640_to_mipi_csi2>;
				data-lanes = <1 2>;
			};
		};
	};
};

&lcdif {
	status = "okay";
};

&mipi_dsi {
	samsung,esc-clock-frequency = <10000000>;
	status = "okay";

	ports {
		port@1 {
			reg = <1>;

			dsi_out: endpoint {
				remote-endpoint = <&adv7533_in>;
				data-lanes = <1 2 3 4>;
			};
		};
	};
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&spdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif1>;
	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&uart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MN_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&usbphynop1 {
	wakeup-source;
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	disable-over-current;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_camera: cameragrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
			MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
		>;
	};

	pinctrl_gpio_wlf: gpiowlfgrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
		>;
	};

	pinctrl_ir: irgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16	0x1c3
			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17	0x1c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18	0x1c3
			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19	0x1c3
		>;
	};

	pinctrl_pdm: pdmgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
			MX8MN_IOMUXC_SAI5_RXC_PDM_CLK		0xd6
			MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
			MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0	0xd6
			MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1	0xd6
			MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2	0xd6
			MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3	0xd6
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
			MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
			MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
			MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
		>;
	};

	pinctrl_spdif1: spdif1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
		>;
	};

	pinctrl_typec1: typec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x140
			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
		>;
	};
};