| commit | 7c62f299bafef82c83169ac0c4cf77874446fc83 | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Fri Oct 02 13:42:21 2015 +0900 |
| committer | Olof Johansson <olof@lixom.net> | Tue Oct 27 09:21:02 2015 +0900 |
| tree | ff7f1ce4d392a456c0394e9946ae1befca0aaf8f | |
| parent | 3d2ef3b3962c60e3b25de6a981127d95cb0be98b [diff] |
ARM: dts: uniphier: add outer cache controller nodes Add L2 cache controller nodes for all the UniPhier SoC DTSI. Also, add an L3 cache controller node for PH1-Pro5 DTSI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>