| commit | 8230a5ab435c6a0f395ff8fb190e53b563f06179 | [log] [tgz] |
|---|---|---|
| author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | Wed Mar 12 12:41:41 2014 -0300 |
| committer | Jason Cooper <jason@lakedaemon.net> | Thu Mar 13 23:20:27 2014 +0000 |
| tree | bd9c0bc620fddb356e4944aa1da05ac176b043ac | |
| parent | e9646fe1169de0162d461472df7ed19e0c729b61 [diff] |
clk: mvebu: Fix ratio register offset on A375 SoC This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 4da6076..4af33ba 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c
@@ -213,7 +213,7 @@ .set_rate = clk_corediv_set_rate, }, .ratio_reload = BIT(8), - .ratio_offset = 0x8, + .ratio_offset = 0x4, }; static void __init