| commit | 8304b15e132f1608973aca4527a8e12af41ddc0e | [log] [tgz] |
|---|---|---|
| author | Richard Zhu <hongxing.zhu@nxp.com> | Mon Mar 15 16:17:48 2021 +0800 |
| committer | Abel Vesa <abel.vesa@nxp.com> | Sun Apr 04 22:39:05 2021 +0300 |
| tree | 9ad1122ac74a0bb51dd546747d84f2028cc3dbf1 | |
| parent | 1840518ae7de0e1eeb9075069cbe632fde16c88d [diff] |
clk: imx8mq: Correct the pcie1 sels - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock. Change the sys2_pll_500m to sys2_pll_50m. - Correct one misspell of the imx8mq_pcie1_ctrl_sels definition, from "sys2_pll_250m" to "sys2_pll_333m". Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>