| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <linux/clk.h> |
| #include <linux/clk-provider.h> |
| #include <linux/delay.h> |
| #include <linux/err.h> |
| #include <linux/io.h> |
| #include <linux/iopoll.h> |
| #include <linux/kernel.h> |
| #include <linux/module.h> |
| #include <linux/of.h> |
| #include <linux/of_device.h> |
| #include <linux/of_address.h> |
| #include <linux/phy/phy.h> |
| #include <linux/platform_device.h> |
| #include <linux/regulator/consumer.h> |
| #include <linux/reset.h> |
| #include <linux/slab.h> |
| |
| #include <dt-bindings/phy/phy.h> |
| |
| #include "phy-qcom-qmp.h" |
| |
| /* QPHY_SW_RESET bit */ |
| #define SW_RESET BIT(0) |
| /* QPHY_POWER_DOWN_CONTROL */ |
| #define SW_PWRDN BIT(0) |
| #define REFCLK_DRV_DSBL BIT(1) |
| /* QPHY_START_CONTROL bits */ |
| #define SERDES_START BIT(0) |
| #define PCS_START BIT(1) |
| #define PLL_READY_GATE_EN BIT(3) |
| /* QPHY_PCS_STATUS bit */ |
| #define PHYSTATUS BIT(6) |
| #define PHYSTATUS_4_20 BIT(7) |
| /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ |
| #define PCS_READY BIT(0) |
| |
| /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ |
| /* DP PHY soft reset */ |
| #define SW_DPPHY_RESET BIT(0) |
| /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ |
| #define SW_DPPHY_RESET_MUX BIT(1) |
| /* USB3 PHY soft reset */ |
| #define SW_USB3PHY_RESET BIT(2) |
| /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ |
| #define SW_USB3PHY_RESET_MUX BIT(3) |
| |
| /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ |
| #define USB3_MODE BIT(0) /* enables USB3 mode */ |
| #define DP_MODE BIT(1) /* enables DP mode */ |
| |
| /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ |
| #define ARCVR_DTCT_EN BIT(0) |
| #define ALFPS_DTCT_EN BIT(1) |
| #define ARCVR_DTCT_EVENT_SEL BIT(4) |
| |
| /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ |
| #define IRQ_CLEAR BIT(0) |
| |
| /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ |
| #define RCVR_DETECT BIT(0) |
| |
| /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ |
| #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ |
| |
| #define PHY_INIT_COMPLETE_TIMEOUT 10000 |
| #define POWER_DOWN_DELAY_US_MIN 10 |
| #define POWER_DOWN_DELAY_US_MAX 11 |
| |
| #define MAX_PROP_NAME 32 |
| |
| /* Define the assumed distance between lanes for underspecified device trees. */ |
| #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 |
| |
| struct qmp_phy_init_tbl { |
| unsigned int offset; |
| unsigned int val; |
| /* |
| * register part of layout ? |
| * if yes, then offset gives index in the reg-layout |
| */ |
| bool in_layout; |
| /* |
| * mask of lanes for which this register is written |
| * for cases when second lane needs different values |
| */ |
| u8 lane_mask; |
| }; |
| |
| #define QMP_PHY_INIT_CFG(o, v) \ |
| { \ |
| .offset = o, \ |
| .val = v, \ |
| .lane_mask = 0xff, \ |
| } |
| |
| #define QMP_PHY_INIT_CFG_L(o, v) \ |
| { \ |
| .offset = o, \ |
| .val = v, \ |
| .in_layout = true, \ |
| .lane_mask = 0xff, \ |
| } |
| |
| #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ |
| { \ |
| .offset = o, \ |
| .val = v, \ |
| .lane_mask = l, \ |
| } |
| |
| /* set of registers with offsets different per-PHY */ |
| enum qphy_reg_layout { |
| /* Common block control registers */ |
| QPHY_COM_SW_RESET, |
| QPHY_COM_POWER_DOWN_CONTROL, |
| QPHY_COM_START_CONTROL, |
| QPHY_COM_PCS_READY_STATUS, |
| /* PCS registers */ |
| QPHY_SW_RESET, |
| QPHY_START_CTRL, |
| QPHY_PCS_READY_STATUS, |
| QPHY_PCS_STATUS, |
| QPHY_PCS_AUTONOMOUS_MODE_CTRL, |
| QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, |
| QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, |
| QPHY_PCS_POWER_DOWN_CONTROL, |
| /* PCS_MISC registers */ |
| QPHY_PCS_MISC_TYPEC_CTRL, |
| /* Keep last to ensure regs_layout arrays are properly initialized */ |
| QPHY_LAYOUT_SIZE |
| }; |
| |
| static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { |
| [QPHY_SW_RESET] = 0x00, |
| [QPHY_START_CTRL] = 0x44, |
| [QPHY_PCS_STATUS] = 0x14, |
| [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, |
| }; |
| |
| static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { |
| [QPHY_COM_SW_RESET] = 0x400, |
| [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, |
| [QPHY_COM_START_CONTROL] = 0x408, |
| [QPHY_COM_PCS_READY_STATUS] = 0x448, |
| [QPHY_SW_RESET] = 0x00, |
| [QPHY_START_CTRL] = 0x08, |
| [QPHY_PCS_STATUS] = 0x174, |
| }; |
| |
| static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { |
| [QPHY_SW_RESET] = 0x00, |
| [QPHY_START_CTRL] = 0x08, |
| [QPHY_PCS_STATUS] = 0x174, |
| }; |
| |
| static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { |
| [QPHY_SW_RESET] = 0x00, |
| [QPHY_START_CTRL] = 0x08, |
| [QPHY_PCS_STATUS] = 0x2ac, |
| }; |
| |
| static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { |
| [QPHY_SW_RESET] = 0x00, |
| [QPHY_START_CTRL] = 0x44, |
| [QPHY_PCS_STATUS] = 0x14, |
| [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, |
| }; |
| |
| static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), |
| }; |
| |
| static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), |
| }; |
| |
| static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), |
| }; |
| |
| static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), |
| QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), |
| QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), |
| QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), |
| QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), |
| QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), |
| QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), |
| QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), |
| QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), |
| QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), |
| QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), |
| QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), |
| QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), |
| QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), |
| QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), |
| QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), |
| |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), |
| |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), |
| |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
| |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), |
| QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { |
| }; |
| |
| static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), |
| QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), |
| }; |
| |
| static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
| }; |
| |
| static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), |
| }; |
| |
| static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), |
| }; |
| |
| static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), |
| }; |
| |
| static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), |
| QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), |
| QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
| QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), |
| }; |
| |
| static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), |
| QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), |
| QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), |
| QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), |
| |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), |
| |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), |
| |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), |
| |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), |
| QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), |
| QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), |
| }; |
| |
| static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), |
| QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), |
| }; |
| |
| struct qmp_phy; |
| |
| /* struct qmp_phy_cfg - per-PHY initialization config */ |
| struct qmp_phy_cfg { |
| /* phy-type - PCIE/UFS/USB */ |
| unsigned int type; |
| /* number of lanes provided by phy */ |
| int nlanes; |
| |
| /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ |
| const struct qmp_phy_init_tbl *serdes_tbl; |
| int serdes_tbl_num; |
| const struct qmp_phy_init_tbl *serdes_tbl_sec; |
| int serdes_tbl_num_sec; |
| const struct qmp_phy_init_tbl *tx_tbl; |
| int tx_tbl_num; |
| const struct qmp_phy_init_tbl *tx_tbl_sec; |
| int tx_tbl_num_sec; |
| const struct qmp_phy_init_tbl *rx_tbl; |
| int rx_tbl_num; |
| const struct qmp_phy_init_tbl *rx_tbl_sec; |
| int rx_tbl_num_sec; |
| const struct qmp_phy_init_tbl *pcs_tbl; |
| int pcs_tbl_num; |
| const struct qmp_phy_init_tbl *pcs_tbl_sec; |
| int pcs_tbl_num_sec; |
| const struct qmp_phy_init_tbl *pcs_misc_tbl; |
| int pcs_misc_tbl_num; |
| const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; |
| int pcs_misc_tbl_num_sec; |
| |
| /* clock ids to be requested */ |
| const char * const *clk_list; |
| int num_clks; |
| /* resets to be requested */ |
| const char * const *reset_list; |
| int num_resets; |
| /* regulators to be requested */ |
| const char * const *vreg_list; |
| int num_vregs; |
| |
| /* array of registers with different offsets */ |
| const unsigned int *regs; |
| |
| unsigned int start_ctrl; |
| unsigned int pwrdn_ctrl; |
| unsigned int mask_com_pcs_ready; |
| /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ |
| unsigned int phy_status; |
| |
| /* true, if PHY needs delay after POWER_DOWN */ |
| bool has_pwrdn_delay; |
| /* power_down delay in usec */ |
| int pwrdn_delay_min; |
| int pwrdn_delay_max; |
| |
| /* true, if PHY has secondary tx/rx lanes to be configured */ |
| bool is_dual_lane_phy; |
| |
| /* QMP PHY pipe clock interface rate */ |
| unsigned long pipe_clock_rate; |
| }; |
| |
| /** |
| * struct qmp_phy - per-lane phy descriptor |
| * |
| * @phy: generic phy |
| * @cfg: phy specific configuration |
| * @serdes: iomapped memory space for phy's serdes (i.e. PLL) |
| * @tx: iomapped memory space for lane's tx |
| * @rx: iomapped memory space for lane's rx |
| * @pcs: iomapped memory space for lane's pcs |
| * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) |
| * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) |
| * @pcs_misc: iomapped memory space for lane's pcs_misc |
| * @pipe_clk: pipe clock |
| * @index: lane index |
| * @qmp: QMP phy to which this lane belongs |
| * @mode: current PHY mode |
| */ |
| struct qmp_phy { |
| struct phy *phy; |
| const struct qmp_phy_cfg *cfg; |
| void __iomem *serdes; |
| void __iomem *tx; |
| void __iomem *rx; |
| void __iomem *pcs; |
| void __iomem *tx2; |
| void __iomem *rx2; |
| void __iomem *pcs_misc; |
| struct clk *pipe_clk; |
| unsigned int index; |
| struct qcom_qmp *qmp; |
| enum phy_mode mode; |
| }; |
| |
| /** |
| * struct qcom_qmp - structure holding QMP phy block attributes |
| * |
| * @dev: device |
| * |
| * @clks: array of clocks required by phy |
| * @resets: array of resets required by phy |
| * @vregs: regulator supplies bulk data |
| * |
| * @phys: array of per-lane phy descriptors |
| */ |
| struct qcom_qmp { |
| struct device *dev; |
| |
| struct clk_bulk_data *clks; |
| struct reset_control_bulk_data *resets; |
| struct regulator_bulk_data *vregs; |
| |
| struct qmp_phy **phys; |
| }; |
| |
| static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) |
| { |
| u32 reg; |
| |
| reg = readl(base + offset); |
| reg |= val; |
| writel(reg, base + offset); |
| |
| /* ensure that above write is through */ |
| readl(base + offset); |
| } |
| |
| static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) |
| { |
| u32 reg; |
| |
| reg = readl(base + offset); |
| reg &= ~val; |
| writel(reg, base + offset); |
| |
| /* ensure that above write is through */ |
| readl(base + offset); |
| } |
| |
| /* list of clocks required by phy */ |
| static const char * const msm8996_phy_clk_l[] = { |
| "aux", "cfg_ahb", "ref", |
| }; |
| |
| |
| static const char * const sdm845_pciephy_clk_l[] = { |
| "aux", "cfg_ahb", "ref", "refgen", |
| }; |
| |
| /* list of regulators */ |
| static const char * const qmp_phy_vreg_l[] = { |
| "vdda-phy", "vdda-pll", |
| }; |
| |
| static const char * const ipq8074_pciephy_clk_l[] = { |
| "aux", "cfg_ahb", |
| }; |
| |
| /* list of resets */ |
| static const char * const ipq8074_pciephy_reset_l[] = { |
| "phy", "common", |
| }; |
| |
| static const char * const sdm845_pciephy_reset_l[] = { |
| "phy", |
| }; |
| |
| static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = ipq8074_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), |
| .tx_tbl = ipq8074_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), |
| .rx_tbl = ipq8074_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), |
| .pcs_tbl = ipq8074_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), |
| .clk_list = ipq8074_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), |
| .reset_list = ipq8074_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
| .vreg_list = NULL, |
| .num_vregs = 0, |
| .regs = pciephy_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), |
| .tx_tbl = ipq8074_pcie_gen3_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), |
| .rx_tbl = ipq8074_pcie_gen3_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), |
| .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), |
| .clk_list = ipq8074_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), |
| .reset_list = ipq8074_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
| .vreg_list = NULL, |
| .num_vregs = 0, |
| .regs = ipq_pciephy_gen3_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| |
| .pipe_clock_rate = 250000000, |
| }; |
| |
| static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = ipq6018_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), |
| .tx_tbl = ipq6018_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), |
| .rx_tbl = ipq6018_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), |
| .pcs_tbl = ipq6018_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), |
| .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), |
| .clk_list = ipq8074_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), |
| .reset_list = ipq8074_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
| .vreg_list = NULL, |
| .num_vregs = 0, |
| .regs = ipq_pciephy_gen3_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), |
| .tx_tbl = sdm845_qmp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), |
| .rx_tbl = sdm845_qmp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), |
| .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), |
| .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sdm845_qmp_pciephy_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), |
| .tx_tbl = sdm845_qhp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), |
| .rx_tbl = sdm845_qhp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), |
| .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sdm845_qhp_pciephy_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), |
| .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, |
| .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), |
| .tx_tbl = sm8250_qmp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), |
| .rx_tbl = sm8250_qmp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), |
| .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, |
| .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), |
| .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), |
| .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, |
| .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), |
| .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), |
| .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 2, |
| |
| .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), |
| .tx_tbl = sm8250_qmp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), |
| .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, |
| .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), |
| .rx_tbl = sm8250_qmp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), |
| .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, |
| .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), |
| .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), |
| .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, |
| .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), |
| .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), |
| .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .is_dual_lane_phy = true, |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg msm8998_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = msm8998_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), |
| .tx_tbl = msm8998_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), |
| .rx_tbl = msm8998_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), |
| .pcs_tbl = msm8998_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), |
| .clk_list = msm8996_phy_clk_l, |
| .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), |
| .reset_list = ipq8074_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = pciephy_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| }; |
| |
| static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), |
| .tx_tbl = sc8180x_qmp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), |
| .rx_tbl = sc8180x_qmp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), |
| .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), |
| .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 2, |
| |
| .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), |
| .tx_tbl = sdx55_qmp_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), |
| .rx_tbl = sdx55_qmp_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), |
| .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), |
| .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = PCS_START | SERDES_START, |
| .pwrdn_ctrl = SW_PWRDN, |
| .phy_status = PHYSTATUS_4_20, |
| |
| .is_dual_lane_phy = true, |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 1, |
| |
| .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), |
| .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), |
| .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), |
| .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), |
| .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS, |
| |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { |
| .type = PHY_TYPE_PCIE, |
| .nlanes = 2, |
| |
| .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, |
| .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), |
| .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, |
| .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), |
| .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, |
| .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), |
| .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), |
| .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, |
| .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), |
| .clk_list = sdm845_pciephy_clk_l, |
| .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), |
| .reset_list = sdm845_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), |
| .vreg_list = qmp_phy_vreg_l, |
| .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), |
| .regs = sm8250_pcie_regs_layout, |
| |
| .start_ctrl = SERDES_START | PCS_START, |
| .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, |
| .phy_status = PHYSTATUS_4_20, |
| |
| .is_dual_lane_phy = true, |
| .has_pwrdn_delay = true, |
| .pwrdn_delay_min = 995, /* us */ |
| .pwrdn_delay_max = 1005, /* us */ |
| }; |
| |
| static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, |
| const unsigned int *regs, |
| const struct qmp_phy_init_tbl tbl[], |
| int num, |
| u8 lane_mask) |
| { |
| int i; |
| const struct qmp_phy_init_tbl *t = tbl; |
| |
| if (!t) |
| return; |
| |
| for (i = 0; i < num; i++, t++) { |
| if (!(t->lane_mask & lane_mask)) |
| continue; |
| |
| if (t->in_layout) |
| writel(t->val, base + regs[t->offset]); |
| else |
| writel(t->val, base + t->offset); |
| } |
| } |
| |
| static void qcom_qmp_phy_pcie_configure(void __iomem *base, |
| const unsigned int *regs, |
| const struct qmp_phy_init_tbl tbl[], |
| int num) |
| { |
| qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); |
| } |
| |
| static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) |
| { |
| const struct qmp_phy_cfg *cfg = qphy->cfg; |
| void __iomem *serdes = qphy->serdes; |
| const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; |
| int serdes_tbl_num = cfg->serdes_tbl_num; |
| |
| qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); |
| if (cfg->serdes_tbl_sec) |
| qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, |
| cfg->serdes_tbl_num_sec); |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) |
| { |
| struct qcom_qmp *qmp = qphy->qmp; |
| const struct qmp_phy_cfg *cfg = qphy->cfg; |
| void __iomem *pcs = qphy->pcs; |
| int ret; |
| |
| /* turn on regulator supplies */ |
| ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); |
| if (ret) { |
| dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); |
| return ret; |
| } |
| |
| ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); |
| if (ret) { |
| dev_err(qmp->dev, "reset assert failed\n"); |
| goto err_disable_regulators; |
| } |
| |
| ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); |
| if (ret) { |
| dev_err(qmp->dev, "reset deassert failed\n"); |
| goto err_disable_regulators; |
| } |
| |
| ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); |
| if (ret) |
| goto err_assert_reset; |
| |
| if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) |
| qphy_setbits(pcs, |
| cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], |
| cfg->pwrdn_ctrl); |
| else |
| qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, |
| cfg->pwrdn_ctrl); |
| |
| return 0; |
| |
| err_assert_reset: |
| reset_control_bulk_assert(cfg->num_resets, qmp->resets); |
| err_disable_regulators: |
| regulator_bulk_disable(cfg->num_vregs, qmp->vregs); |
| |
| return ret; |
| } |
| |
| static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) |
| { |
| struct qcom_qmp *qmp = qphy->qmp; |
| const struct qmp_phy_cfg *cfg = qphy->cfg; |
| |
| reset_control_bulk_assert(cfg->num_resets, qmp->resets); |
| |
| clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); |
| |
| regulator_bulk_disable(cfg->num_vregs, qmp->vregs); |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_init(struct phy *phy) |
| { |
| struct qmp_phy *qphy = phy_get_drvdata(phy); |
| struct qcom_qmp *qmp = qphy->qmp; |
| int ret; |
| dev_vdbg(qmp->dev, "Initializing QMP phy\n"); |
| |
| ret = qcom_qmp_phy_pcie_com_init(qphy); |
| if (ret) |
| return ret; |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_power_on(struct phy *phy) |
| { |
| struct qmp_phy *qphy = phy_get_drvdata(phy); |
| struct qcom_qmp *qmp = qphy->qmp; |
| const struct qmp_phy_cfg *cfg = qphy->cfg; |
| void __iomem *tx = qphy->tx; |
| void __iomem *rx = qphy->rx; |
| void __iomem *pcs = qphy->pcs; |
| void __iomem *pcs_misc = qphy->pcs_misc; |
| void __iomem *status; |
| unsigned int mask, val, ready; |
| int ret; |
| |
| qcom_qmp_phy_pcie_serdes_init(qphy); |
| |
| ret = clk_prepare_enable(qphy->pipe_clk); |
| if (ret) { |
| dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); |
| return ret; |
| } |
| |
| /* Tx, Rx, and PCS configurations */ |
| qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, |
| cfg->tx_tbl, cfg->tx_tbl_num, 1); |
| if (cfg->tx_tbl_sec) |
| qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, |
| cfg->tx_tbl_num_sec, 1); |
| |
| /* Configuration for other LANE for USB-DP combo PHY */ |
| if (cfg->is_dual_lane_phy) { |
| qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, |
| cfg->tx_tbl, cfg->tx_tbl_num, 2); |
| if (cfg->tx_tbl_sec) |
| qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, |
| cfg->tx_tbl_sec, |
| cfg->tx_tbl_num_sec, 2); |
| } |
| |
| qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, |
| cfg->rx_tbl, cfg->rx_tbl_num, 1); |
| if (cfg->rx_tbl_sec) |
| qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, |
| cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); |
| |
| if (cfg->is_dual_lane_phy) { |
| qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, |
| cfg->rx_tbl, cfg->rx_tbl_num, 2); |
| if (cfg->rx_tbl_sec) |
| qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, |
| cfg->rx_tbl_sec, |
| cfg->rx_tbl_num_sec, 2); |
| } |
| |
| qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); |
| if (cfg->pcs_tbl_sec) |
| qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, |
| cfg->pcs_tbl_num_sec); |
| |
| qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, |
| cfg->pcs_misc_tbl_num); |
| if (cfg->pcs_misc_tbl_sec) |
| qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, |
| cfg->pcs_misc_tbl_num_sec); |
| |
| /* |
| * Pull out PHY from POWER DOWN state. |
| * This is active low enable signal to power-down PHY. |
| */ |
| qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); |
| |
| if (cfg->has_pwrdn_delay) |
| usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); |
| |
| /* Pull PHY out of reset state */ |
| qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); |
| |
| /* start SerDes and Phy-Coding-Sublayer */ |
| qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); |
| |
| status = pcs + cfg->regs[QPHY_PCS_STATUS]; |
| mask = cfg->phy_status; |
| ready = 0; |
| |
| ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, |
| PHY_INIT_COMPLETE_TIMEOUT); |
| if (ret) { |
| dev_err(qmp->dev, "phy initialization timed-out\n"); |
| goto err_disable_pipe_clk; |
| } |
| |
| return 0; |
| |
| err_disable_pipe_clk: |
| clk_disable_unprepare(qphy->pipe_clk); |
| |
| return ret; |
| } |
| |
| static int qcom_qmp_phy_pcie_power_off(struct phy *phy) |
| { |
| struct qmp_phy *qphy = phy_get_drvdata(phy); |
| const struct qmp_phy_cfg *cfg = qphy->cfg; |
| |
| clk_disable_unprepare(qphy->pipe_clk); |
| |
| /* PHY reset */ |
| qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); |
| |
| /* stop SerDes and Phy-Coding-Sublayer */ |
| qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); |
| |
| /* Put PHY into POWER DOWN state: active low */ |
| if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { |
| qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], |
| cfg->pwrdn_ctrl); |
| } else { |
| qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, |
| cfg->pwrdn_ctrl); |
| } |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_exit(struct phy *phy) |
| { |
| struct qmp_phy *qphy = phy_get_drvdata(phy); |
| |
| qcom_qmp_phy_pcie_com_exit(qphy); |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_enable(struct phy *phy) |
| { |
| int ret; |
| |
| ret = qcom_qmp_phy_pcie_init(phy); |
| if (ret) |
| return ret; |
| |
| ret = qcom_qmp_phy_pcie_power_on(phy); |
| if (ret) |
| qcom_qmp_phy_pcie_exit(phy); |
| |
| return ret; |
| } |
| |
| static int qcom_qmp_phy_pcie_disable(struct phy *phy) |
| { |
| int ret; |
| |
| ret = qcom_qmp_phy_pcie_power_off(phy); |
| if (ret) |
| return ret; |
| return qcom_qmp_phy_pcie_exit(phy); |
| } |
| |
| static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, |
| enum phy_mode mode, int submode) |
| { |
| struct qmp_phy *qphy = phy_get_drvdata(phy); |
| |
| qphy->mode = mode; |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) |
| { |
| struct qcom_qmp *qmp = dev_get_drvdata(dev); |
| int num = cfg->num_vregs; |
| int i; |
| |
| qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); |
| if (!qmp->vregs) |
| return -ENOMEM; |
| |
| for (i = 0; i < num; i++) |
| qmp->vregs[i].supply = cfg->vreg_list[i]; |
| |
| return devm_regulator_bulk_get(dev, num, qmp->vregs); |
| } |
| |
| static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) |
| { |
| struct qcom_qmp *qmp = dev_get_drvdata(dev); |
| int i; |
| int ret; |
| |
| qmp->resets = devm_kcalloc(dev, cfg->num_resets, |
| sizeof(*qmp->resets), GFP_KERNEL); |
| if (!qmp->resets) |
| return -ENOMEM; |
| |
| for (i = 0; i < cfg->num_resets; i++) |
| qmp->resets[i].id = cfg->reset_list[i]; |
| |
| ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); |
| if (ret) |
| return dev_err_probe(dev, ret, "failed to get resets\n"); |
| |
| return 0; |
| } |
| |
| static int qcom_qmp_phy_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) |
| { |
| struct qcom_qmp *qmp = dev_get_drvdata(dev); |
| int num = cfg->num_clks; |
| int i; |
| |
| qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); |
| if (!qmp->clks) |
| return -ENOMEM; |
| |
| for (i = 0; i < num; i++) |
| qmp->clks[i].id = cfg->clk_list[i]; |
| |
| return devm_clk_bulk_get(dev, num, qmp->clks); |
| } |
| |
| static void phy_clk_release_provider(void *res) |
| { |
| of_clk_del_provider(res); |
| } |
| |
| /* |
| * Register a fixed rate pipe clock. |
| * |
| * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate |
| * controls it. The <s>_pipe_clk coming out of the GCC is requested |
| * by the PHY driver for its operations. |
| * We register the <s>_pipe_clksrc here. The gcc driver takes care |
| * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. |
| * Below picture shows this relationship. |
| * |
| * +---------------+ |
| * | PHY block |<<---------------------------------------+ |
| * | | | |
| * | +-------+ | +-----+ | |
| * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ |
| * clk | +-------+ | +-----+ |
| * +---------------+ |
| */ |
| static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) |
| { |
| struct clk_fixed_rate *fixed; |
| struct clk_init_data init = { }; |
| int ret; |
| |
| ret = of_property_read_string(np, "clock-output-names", &init.name); |
| if (ret) { |
| dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); |
| return ret; |
| } |
| |
| fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); |
| if (!fixed) |
| return -ENOMEM; |
| |
| init.ops = &clk_fixed_rate_ops; |
| |
| /* |
| * Controllers using QMP PHY-s use 125MHz pipe clock interface |
| * unless other frequency is specified in the PHY config. |
| */ |
| if (qmp->phys[0]->cfg->pipe_clock_rate) |
| fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; |
| else |
| fixed->fixed_rate = 125000000; |
| |
| fixed->hw.init = &init; |
| |
| ret = devm_clk_hw_register(qmp->dev, &fixed->hw); |
| if (ret) |
| return ret; |
| |
| ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); |
| if (ret) |
| return ret; |
| |
| /* |
| * Roll a devm action because the clock provider is the child node, but |
| * the child node is not actually a device. |
| */ |
| return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); |
| } |
| |
| static const struct phy_ops qcom_qmp_phy_pcie_ops = { |
| .power_on = qcom_qmp_phy_pcie_enable, |
| .power_off = qcom_qmp_phy_pcie_disable, |
| .set_mode = qcom_qmp_phy_pcie_set_mode, |
| .owner = THIS_MODULE, |
| }; |
| |
| static |
| int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, |
| void __iomem *serdes, const struct qmp_phy_cfg *cfg) |
| { |
| struct qcom_qmp *qmp = dev_get_drvdata(dev); |
| struct phy *generic_phy; |
| struct qmp_phy *qphy; |
| char prop_name[MAX_PROP_NAME]; |
| int ret; |
| |
| qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); |
| if (!qphy) |
| return -ENOMEM; |
| |
| qphy->cfg = cfg; |
| qphy->serdes = serdes; |
| /* |
| * Get memory resources for each phy lane: |
| * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. |
| * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 |
| * For single lane PHYs: pcs_misc (optional) -> 3. |
| */ |
| qphy->tx = of_iomap(np, 0); |
| if (!qphy->tx) |
| return -ENOMEM; |
| |
| qphy->rx = of_iomap(np, 1); |
| if (!qphy->rx) |
| return -ENOMEM; |
| |
| qphy->pcs = of_iomap(np, 2); |
| if (!qphy->pcs) |
| return -ENOMEM; |
| |
| /* |
| * If this is a dual-lane PHY, then there should be registers for the |
| * second lane. Some old device trees did not specify this, so fall |
| * back to old legacy behavior of assuming they can be reached at an |
| * offset from the first lane. |
| */ |
| if (cfg->is_dual_lane_phy) { |
| qphy->tx2 = of_iomap(np, 3); |
| qphy->rx2 = of_iomap(np, 4); |
| if (!qphy->tx2 || !qphy->rx2) { |
| dev_warn(dev, |
| "Underspecified device tree, falling back to legacy register regions\n"); |
| |
| /* In the old version, pcs_misc is at index 3. */ |
| qphy->pcs_misc = qphy->tx2; |
| qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; |
| qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; |
| |
| } else { |
| qphy->pcs_misc = of_iomap(np, 5); |
| } |
| |
| } else { |
| qphy->pcs_misc = of_iomap(np, 3); |
| } |
| |
| if (!qphy->pcs_misc && |
| of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) |
| qphy->pcs_misc = qphy->pcs + 0x400; |
| |
| if (!qphy->pcs_misc) |
| dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); |
| |
| snprintf(prop_name, sizeof(prop_name), "pipe%d", id); |
| qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); |
| if (IS_ERR(qphy->pipe_clk)) { |
| return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), |
| "failed to get lane%d pipe clock\n", id); |
| } |
| |
| generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); |
| if (IS_ERR(generic_phy)) { |
| ret = PTR_ERR(generic_phy); |
| dev_err(dev, "failed to create qphy %d\n", ret); |
| return ret; |
| } |
| |
| qphy->phy = generic_phy; |
| qphy->index = id; |
| qphy->qmp = qmp; |
| qmp->phys[id] = qphy; |
| phy_set_drvdata(generic_phy, qphy); |
| |
| return 0; |
| } |
| |
| static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { |
| { |
| .compatible = "qcom,msm8998-qmp-pcie-phy", |
| .data = &msm8998_pciephy_cfg, |
| }, { |
| .compatible = "qcom,ipq8074-qmp-pcie-phy", |
| .data = &ipq8074_pciephy_cfg, |
| }, { |
| .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", |
| .data = &ipq8074_pciephy_gen3_cfg, |
| }, { |
| .compatible = "qcom,ipq6018-qmp-pcie-phy", |
| .data = &ipq6018_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sc8180x-qmp-pcie-phy", |
| .data = &sc8180x_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sdm845-qhp-pcie-phy", |
| .data = &sdm845_qhp_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sdm845-qmp-pcie-phy", |
| .data = &sdm845_qmp_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", |
| .data = &sm8250_qmp_gen3x1_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", |
| .data = &sm8250_qmp_gen3x2_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sm8250-qmp-modem-pcie-phy", |
| .data = &sm8250_qmp_gen3x2_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sdx55-qmp-pcie-phy", |
| .data = &sdx55_qmp_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", |
| .data = &sm8450_qmp_gen3x1_pciephy_cfg, |
| }, { |
| .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", |
| .data = &sm8450_qmp_gen4x2_pciephy_cfg, |
| }, |
| { }, |
| }; |
| MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); |
| |
| static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) |
| { |
| struct qcom_qmp *qmp; |
| struct device *dev = &pdev->dev; |
| struct device_node *child; |
| struct phy_provider *phy_provider; |
| void __iomem *serdes; |
| const struct qmp_phy_cfg *cfg = NULL; |
| int num, id; |
| int ret; |
| |
| qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); |
| if (!qmp) |
| return -ENOMEM; |
| |
| qmp->dev = dev; |
| dev_set_drvdata(dev, qmp); |
| |
| /* Get the specific init parameters of QMP phy */ |
| cfg = of_device_get_match_data(dev); |
| if (!cfg) |
| return -EINVAL; |
| |
| /* per PHY serdes; usually located at base address */ |
| serdes = devm_platform_ioremap_resource(pdev, 0); |
| if (IS_ERR(serdes)) |
| return PTR_ERR(serdes); |
| |
| ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); |
| if (ret) |
| return ret; |
| |
| ret = qcom_qmp_phy_pcie_reset_init(dev, cfg); |
| if (ret) |
| return ret; |
| |
| ret = qcom_qmp_phy_pcie_vreg_init(dev, cfg); |
| if (ret) { |
| if (ret != -EPROBE_DEFER) |
| dev_err(dev, "failed to get regulator supplies: %d\n", |
| ret); |
| return ret; |
| } |
| |
| num = of_get_available_child_count(dev->of_node); |
| /* do we have a rogue child node ? */ |
| if (num > 1) |
| return -EINVAL; |
| |
| qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); |
| if (!qmp->phys) |
| return -ENOMEM; |
| |
| pm_runtime_set_active(dev); |
| pm_runtime_enable(dev); |
| /* |
| * Prevent runtime pm from being ON by default. Users can enable |
| * it using power/control in sysfs. |
| */ |
| pm_runtime_forbid(dev); |
| |
| id = 0; |
| for_each_available_child_of_node(dev->of_node, child) { |
| /* Create per-lane phy */ |
| ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); |
| if (ret) { |
| dev_err(dev, "failed to create lane%d phy, %d\n", |
| id, ret); |
| goto err_node_put; |
| } |
| |
| /* |
| * Register the pipe clock provided by phy. |
| * See function description to see details of this pipe clock. |
| */ |
| ret = phy_pipe_clk_register(qmp, child); |
| if (ret) { |
| dev_err(qmp->dev, |
| "failed to register pipe clock source\n"); |
| goto err_node_put; |
| } |
| |
| id++; |
| } |
| |
| phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
| if (!IS_ERR(phy_provider)) |
| dev_info(dev, "Registered Qcom-QMP phy\n"); |
| else |
| pm_runtime_disable(dev); |
| |
| return PTR_ERR_OR_ZERO(phy_provider); |
| |
| err_node_put: |
| pm_runtime_disable(dev); |
| of_node_put(child); |
| return ret; |
| } |
| |
| static struct platform_driver qcom_qmp_phy_pcie_driver = { |
| .probe = qcom_qmp_phy_pcie_probe, |
| .driver = { |
| .name = "qcom-qmp-pcie-phy", |
| .of_match_table = qcom_qmp_phy_pcie_of_match_table, |
| }, |
| }; |
| |
| module_platform_driver(qcom_qmp_phy_pcie_driver); |
| |
| MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); |
| MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); |
| MODULE_LICENSE("GPL v2"); |