tree 60a1ecb382a012bb5626b556f7c2aa848f7038d0
parent 7a8ca0a0c480fedf91bdbadf8b90edd5374ce18b
author Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> 1421285356 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1422545086 +0000

ARM: 8278/1: sa1100: split irq handling for low GPIOs

Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>