arch/arm64/boot/dts/intel/socfpga_agilex.dtsi - linux - Git at Google

 // SPDX-License-Identifier:     GPL-2.0
 /*
  * Copyright (C) 2019, Intel Corporation
  */

 /dts-v1/;
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/agilex-clock.h>

 / {
 	compatible = "intel,socfpga-agilex";
 	#address-cells = <2>;
 	#size-cells = <2>;

 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		service_reserved: svcbuffer@0 {
 			compatible = "shared-dma-pool";
 			reg = <0x0 0x0 0x0 0x2000000>;
 			alignment = <0x1000>;
 			no-map;
 		};
 	};

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x0>;
 		};

 		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x1>;
 		};

 		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x2>;
 		};

 		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			enable-method = "psci";
 			reg = <0x3>;
 		};
 	};

 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-affinity = <&cpu0>,
 				     <&cpu1>,
 				     <&cpu2>,
 				     <&cpu3>;
 		interrupt-parent = <&intc>;
 	};

 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
 	};

 	intc: interrupt-controller@fffc1000 {
 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
 		reg = <0x0 0xfffc1000 0x0 0x1000>,
 		      <0x0 0xfffc2000 0x0 0x2000>,
 		      <0x0 0xfffc4000 0x0 0x2000>,
 		      <0x0 0xfffc6000 0x0 0x2000>;
 	};

 	clocks {
 		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 		};

 		cb_intosc_ls_clk: cb-intosc-ls-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 		};

 		f2s_free_clk: f2s-free-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 		};

 		osc1: osc1 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 		};

 		qspi_clk: qspi-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <200000000>;
 		};
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&intc>;
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};

 	usbphy0: usbphy {
 		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
 	};

 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		device_type = "soc";
 		interrupt-parent = <&intc>;
 		ranges = <0 0 0 0xffffffff>;

 		base_fpga_region {
 			#address-cells = <0x2>;
 			#size-cells = <0x2>;
 			compatible = "fpga-region";
 			fpga-mgr = <&fpga_mgr>;
 		};

 		clkmgr: clock-controller@ffd10000 {
 			compatible = "intel,agilex-clkmgr";
 			reg = <0xffd10000 0x1000>;
 			#clock-cells = <1>;
 		};

 		gmac0: ethernet@ff800000 {
 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 			reg = <0xff800000 0x2000>;
 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
 			tx-fifo-depth = <16384>;
 			rx-fifo-depth = <16384>;
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 1>;
 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 			clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
 		};

 		gmac1: ethernet@ff802000 {
 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 			reg = <0xff802000 0x2000>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
 			tx-fifo-depth = <16384>;
 			rx-fifo-depth = <16384>;
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 2>;
 			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 			clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
 		};

 		gmac2: ethernet@ff804000 {
 			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
 			reg = <0xff804000 0x2000>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
 			tx-fifo-depth = <16384>;
 			rx-fifo-depth = <16384>;
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 3>;
 			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
 			clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
 		};

 		gpio0: gpio@ffc03200 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc03200 0x100>;
 			resets = <&rst GPIO0_RESET>;
 			status = "disabled";

 			porta: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <24>;
 				reg = <0>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};

 		gpio1: gpio@ffc03300 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc03300 0x100>;
 			resets = <&rst GPIO1_RESET>;
 			status = "disabled";

 			portb: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
 				gpio-controller;
 				#gpio-cells = <2>;
 				snps,nr-gpios = <24>;
 				reg = <0>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};

 		i2c0: i2c@ffc02800 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,designware-i2c";
 			reg = <0xffc02800 0x100>;
 			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst I2C0_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		i2c1: i2c@ffc02900 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,designware-i2c";
 			reg = <0xffc02900 0x100>;
 			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst I2C1_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		i2c2: i2c@ffc02a00 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,designware-i2c";
 			reg = <0xffc02a00 0x100>;
 			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst I2C2_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		i2c3: i2c@ffc02b00 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,designware-i2c";
 			reg = <0xffc02b00 0x100>;
 			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst I2C3_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		i2c4: i2c@ffc02c00 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "snps,designware-i2c";
 			reg = <0xffc02c00 0x100>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst I2C4_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		mmc: mmc@ff808000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "altr,socfpga-dw-mshc";
 			reg = <0xff808000 0x1000>;
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			fifo-depth = <0x400>;
 			resets = <&rst SDMMC_RESET>;
 			reset-names = "reset";
 			clocks = <&clkmgr AGILEX_L4_MP_CLK>,
 				 <&clkmgr AGILEX_SDMMC_CLK>;
 			clock-names = "biu", "ciu";
 			iommus = <&smmu 5>;
 			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
 			status = "disabled";
 		};

 		nand: nand-controller@ffb90000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "altr,socfpga-denali-nand";
 			reg = <0xffb90000 0x10000>,
 			      <0xffb80000 0x1000>;
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX_NAND_CLK>,
 				 <&clkmgr AGILEX_NAND_X_CLK>,
 				 <&clkmgr AGILEX_NAND_ECC_CLK>;
 			clock-names = "nand", "nand_x", "ecc";
 			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
 			status = "disabled";
 		};

 		ocram: sram@ffe00000 {
 			compatible = "mmio-sram";
 			reg = <0xffe00000 0x40000>;
 		};

 		pdma: dma-controller@ffda0000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0xffda0000 0x1000>;
 			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
 			reset-names = "dma", "dma-ocp";
 			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
 			clock-names = "apb_pclk";
 		};

 		pinctrl0: pinctrl@ffd13000 {
 			compatible = "pinctrl-single";
 			#pinctrl-cells = <1>;
 			reg = <0xffd13000 0xa0>;
 			pinctrl-single,register-width = <32>;
 			pinctrl-single,function-mask = <0x0000000f>;
 		};

 		pinctrl1: pinconf@ffd13100 {
 			compatible = "pinctrl-single";
 			#pinctrl-cells = <1>;
 			reg = <0xffd13100 0x20>;
 			pinctrl-single,register-width = <32>;
 		};

 		rst: rstmgr@ffd11000 {
 			#reset-cells = <1>;
 			compatible = "altr,stratix10-rst-mgr";
 			reg = <0xffd11000 0x100>;
 		};

 		smmu: iommu@fa000000 {
 			compatible = "arm,mmu-500", "arm,smmu-v2";
 			reg = <0xfa000000 0x40000>;
 			#global-interrupts = <2>;
 			#iommu-cells = <1>;
 			interrupt-parent = <&intc>;
 			/* Global Secure Fault */
 			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 				/* Global Non-secure Fault */
 				<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 				/* Non-secure Context Interrupts (32) */
 				<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 			stream-match-mask = <0x7ff0>;
 			clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
 				 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
 				 <&clkmgr AGILEX_L4_MAIN_CLK>;
 			status = "disabled";
 		};

 		spi0: spi@ffda4000 {
 			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda4000 0x1000>;
 			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst SPIM0_RESET>;
 			reset-names = "spi";
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
 			status = "disabled";
 		};

 		spi1: spi@ffda5000 {
 			compatible = "snps,dw-apb-ssi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xffda5000 0x1000>;
 			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst SPIM1_RESET>;
 			reset-names = "spi";
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
 			status = "disabled";
 		};

 		sysmgr: sysmgr@ffd12000 {
 			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
 			reg = <0xffd12000 0x500>;
 		};

 		timer0: timer0@ffc03000 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffc03000 0x100>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			clock-names = "timer";
 		};

 		timer1: timer1@ffc03100 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffc03100 0x100>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			clock-names = "timer";
 		};

 		timer2: timer2@ffd00000 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffd00000 0x100>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			clock-names = "timer";
 		};

 		timer3: timer3@ffd00100 {
 			compatible = "snps,dw-apb-timer";
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0xffd00100 0x100>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			clock-names = "timer";
 		};

 		uart0: serial@ffc02000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc02000 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			resets = <&rst UART0_RESET>;
 			status = "disabled";
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 		};

 		uart1: serial@ffc02100 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0xffc02100 0x100>;
 			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			resets = <&rst UART1_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SP_CLK>;
 			status = "disabled";
 		};

 		usb0: usb@ffb00000 {
 			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb00000 0x40000>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 			reset-names = "dwc2", "dwc2-ecc";
 			clocks = <&clkmgr AGILEX_USB_CLK>;
 			clock-names = "otg";
 			iommus = <&smmu 6>;
 			status = "disabled";
 		};

 		usb1: usb@ffb40000 {
 			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
 			reg = <0xffb40000 0x40000>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usbphy0>;
 			phy-names = "usb2-phy";
 			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 			reset-names = "dwc2", "dwc2-ecc";
 			iommus = <&smmu 7>;
 			clocks = <&clkmgr AGILEX_USB_CLK>;
 			status = "disabled";
 		};

 		watchdog0: watchdog@ffd00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0xffd00200 0x100>;
 			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst WATCHDOG0_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
 			status = "disabled";
 		};

 		watchdog1: watchdog@ffd00300 {
 			compatible = "snps,dw-wdt";
 			reg = <0xffd00300 0x100>;
 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst WATCHDOG1_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
 			status = "disabled";
 		};

 		watchdog2: watchdog@ffd00400 {
 			compatible = "snps,dw-wdt";
 			reg = <0xffd00400 0x100>;
 			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst WATCHDOG2_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
 			status = "disabled";
 		};

 		watchdog3: watchdog@ffd00500 {
 			compatible = "snps,dw-wdt";
 			reg = <0xffd00500 0x100>;
 			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 			resets = <&rst WATCHDOG3_RESET>;
 			clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
 			status = "disabled";
 		};

 		sdr: sdr@f8011100 {
 			compatible = "altr,sdr-ctl", "syscon";
 			reg = <0xf8011100 0xc0>;
 		};

 		eccmgr {
 			compatible = "altr,socfpga-s10-ecc-manager",
 				     "altr,socfpga-a10-ecc-manager";
 			altr,sysmgr-syscon = <&sysmgr>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			ranges;

 			sdramedac {
 				compatible = "altr,sdram-edac-s10";
 				altr,sdr-syscon = <&sdr>;
 				interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
 			};

 			ocram-ecc@ff8cc000 {
 				compatible = "altr,socfpga-s10-ocram-ecc",
 					     "altr,socfpga-a10-ocram-ecc";
 				reg = <0xff8cc000 0x100>;
 				altr,ecc-parent = <&ocram>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 			};

 			usb0-ecc@ff8c4000 {
 				compatible = "altr,socfpga-s10-usb-ecc",
 					     "altr,socfpga-usb-ecc";
 				reg = <0xff8c4000 0x100>;
 				altr,ecc-parent = <&usb0>;
 				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 			};

 			emac0-rx-ecc@ff8c0000 {
 				compatible = "altr,socfpga-s10-eth-mac-ecc",
 					     "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0000 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 			};

 			emac0-tx-ecc@ff8c0400 {
 				compatible = "altr,socfpga-s10-eth-mac-ecc",
 					     "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0400 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
 			};

 			sdmmca-ecc@ff8c8c00 {
 				compatible = "altr,socfpga-s10-sdmmc-ecc",
 					     "altr,socfpga-sdmmc-ecc";
 				reg = <0xff8c8c00 0x100>;
 				altr,ecc-parent = <&mmc>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
 					     <15 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};

 		qspi: spi@ff8d2000 {
 			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xff8d2000 0x100>,
 			      <0xff900000 0x100000>;
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			cdns,fifo-depth = <128>;
 			cdns,fifo-width = <4>;
 			cdns,trigger-address = <0x00000000>;
 			clocks = <&qspi_clk>;

 			status = "disabled";
 		};

 		firmware {
 			svc {
 				compatible = "intel,agilex-svc";
 				method = "smc";
 				memory-region = <&service_reserved>;

 				fpga_mgr: fpga-mgr {
 					compatible = "intel,agilex-soc-fpga-mgr";
 				};
 			};
 		};
 	};
 };
	// SPDX-License-Identifier: GPL-2.0
	/*
	* Copyright (C) 2019, Intel Corporation
	*/

	/dts-v1/;
	#include <dt-bindings/reset/altr,rst-mgr-s10.h>
	#include <dt-bindings/gpio/gpio.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/agilex-clock.h>

	/ {
	compatible = "intel,socfpga-agilex";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	service_reserved: svcbuffer@0 {
	compatible = "shared-dma-pool";
	reg = <0x0 0x0 0x0 0x2000000>;
	alignment = <0x1000>;
	no-map;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	enable-method = "psci";
	reg = <0x0>;
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	enable-method = "psci";
	reg = <0x1>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	enable-method = "psci";
	reg = <0x2>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a53";
	device_type = "cpu";
	enable-method = "psci";
	reg = <0x3>;
	};
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>,
	<&cpu1>,
	<&cpu2>,
	<&cpu3>;
	interrupt-parent = <&intc>;
	};

	psci {
	compatible = "arm,psci-0.2";
	method = "smc";
	};

	intc: interrupt-controller@fffc1000 {
	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	#interrupt-cells = <3>;
	interrupt-controller;
	reg = <0x0 0xfffc1000 0x0 0x1000>,
	<0x0 0xfffc2000 0x0 0x2000>,
	<0x0 0xfffc4000 0x0 0x2000>,
	<0x0 0xfffc6000 0x0 0x2000>;
	};

	clocks {
	cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	cb_intosc_ls_clk: cb-intosc-ls-clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	f2s_free_clk: f2s-free-clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	osc1: osc1 {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	};

	qspi_clk: qspi-clk {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <200000000>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&intc>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	usbphy0: usbphy {
	#phy-cells = <0>;
	compatible = "usb-nop-xceiv";
	};

	soc {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	device_type = "soc";
	interrupt-parent = <&intc>;
	ranges = <0 0 0 0xffffffff>;

	base_fpga_region {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	compatible = "fpga-region";
	fpga-mgr = <&fpga_mgr>;
	};

	clkmgr: clock-controller@ffd10000 {
	compatible = "intel,agilex-clkmgr";
	reg = <0xffd10000 0x1000>;
	#clock-cells = <1>;
	};

	gmac0: ethernet@ff800000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
	reg = <0xff800000 0x2000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	mac-address = [00 00 00 00 00 00];
	resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	tx-fifo-depth = <16384>;
	rx-fifo-depth = <16384>;
	snps,multicast-filter-bins = <256>;
	iommus = <&smmu 1>;
	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
	clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
	clock-names = "stmmaceth", "ptp_ref";
	status = "disabled";
	};

	gmac1: ethernet@ff802000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
	reg = <0xff802000 0x2000>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	mac-address = [00 00 00 00 00 00];
	resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	tx-fifo-depth = <16384>;
	rx-fifo-depth = <16384>;
	snps,multicast-filter-bins = <256>;
	iommus = <&smmu 2>;
	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
	clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
	clock-names = "stmmaceth", "ptp_ref";
	status = "disabled";
	};

	gmac2: ethernet@ff804000 {
	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
	reg = <0xff804000 0x2000>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq";
	mac-address = [00 00 00 00 00 00];
	resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
	reset-names = "stmmaceth", "stmmaceth-ocp";
	tx-fifo-depth = <16384>;
	rx-fifo-depth = <16384>;
	snps,multicast-filter-bins = <256>;
	iommus = <&smmu 3>;
	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
	clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
	clock-names = "stmmaceth", "ptp_ref";
	status = "disabled";
	};

	gpio0: gpio@ffc03200 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dw-apb-gpio";
	reg = <0xffc03200 0x100>;
	resets = <&rst GPIO0_RESET>;
	status = "disabled";

	porta: gpio-controller@0 {
	compatible = "snps,dw-apb-gpio-port";
	gpio-controller;
	#gpio-cells = <2>;
	snps,nr-gpios = <24>;
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	gpio1: gpio@ffc03300 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,dw-apb-gpio";
	reg = <0xffc03300 0x100>;
	resets = <&rst GPIO1_RESET>;
	status = "disabled";

	portb: gpio-controller@0 {
	compatible = "snps,dw-apb-gpio-port";
	gpio-controller;
	#gpio-cells = <2>;
	snps,nr-gpios = <24>;
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	i2c0: i2c@ffc02800 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02800 0x100>;
	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst I2C0_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	i2c1: i2c@ffc02900 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02900 0x100>;
	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst I2C1_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	i2c2: i2c@ffc02a00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02a00 0x100>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst I2C2_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	i2c3: i2c@ffc02b00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02b00 0x100>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst I2C3_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	i2c4: i2c@ffc02c00 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "snps,designware-i2c";
	reg = <0xffc02c00 0x100>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst I2C4_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	mmc: mmc@ff808000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "altr,socfpga-dw-mshc";
	reg = <0xff808000 0x1000>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	fifo-depth = <0x400>;
	resets = <&rst SDMMC_RESET>;
	reset-names = "reset";
	clocks = <&clkmgr AGILEX_L4_MP_CLK>,
	<&clkmgr AGILEX_SDMMC_CLK>;
	clock-names = "biu", "ciu";
	iommus = <&smmu 5>;
	altr,sysmgr-syscon = <&sysmgr 0x28 4>;
	status = "disabled";
	};

	nand: nand-controller@ffb90000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "altr,socfpga-denali-nand";
	reg = <0xffb90000 0x10000>,
	<0xffb80000 0x1000>;
	reg-names = "nand_data", "denali_reg";
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clkmgr AGILEX_NAND_CLK>,
	<&clkmgr AGILEX_NAND_X_CLK>,
	<&clkmgr AGILEX_NAND_ECC_CLK>;
	clock-names = "nand", "nand_x", "ecc";
	resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
	status = "disabled";
	};

	ocram: sram@ffe00000 {
	compatible = "mmio-sram";
	reg = <0xffe00000 0x40000>;
	};

	pdma: dma-controller@ffda0000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0xffda0000 0x1000>;
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
	reset-names = "dma", "dma-ocp";
	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
	clock-names = "apb_pclk";
	};

	pinctrl0: pinctrl@ffd13000 {
	compatible = "pinctrl-single";
	#pinctrl-cells = <1>;
	reg = <0xffd13000 0xa0>;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0x0000000f>;
	};

	pinctrl1: pinconf@ffd13100 {
	compatible = "pinctrl-single";
	#pinctrl-cells = <1>;
	reg = <0xffd13100 0x20>;
	pinctrl-single,register-width = <32>;
	};

	rst: rstmgr@ffd11000 {
	#reset-cells = <1>;
	compatible = "altr,stratix10-rst-mgr";
	reg = <0xffd11000 0x100>;
	};

	smmu: iommu@fa000000 {
	compatible = "arm,mmu-500", "arm,smmu-v2";
	reg = <0xfa000000 0x40000>;
	#global-interrupts = <2>;
	#iommu-cells = <1>;
	interrupt-parent = <&intc>;
	/* Global Secure Fault */
	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	/* Global Non-secure Fault */
	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	/* Non-secure Context Interrupts (32) */
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	stream-match-mask = <0x7ff0>;
	clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
	<&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
	<&clkmgr AGILEX_L4_MAIN_CLK>;
	status = "disabled";
	};

	spi0: spi@ffda4000 {
	compatible = "snps,dw-apb-ssi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xffda4000 0x1000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst SPIM0_RESET>;
	reset-names = "spi";
	reg-io-width = <4>;
	num-cs = <4>;
	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
	status = "disabled";
	};

	spi1: spi@ffda5000 {
	compatible = "snps,dw-apb-ssi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xffda5000 0x1000>;
	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst SPIM1_RESET>;
	reset-names = "spi";
	reg-io-width = <4>;
	num-cs = <4>;
	clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
	status = "disabled";
	};

	sysmgr: sysmgr@ffd12000 {
	compatible = "altr,sys-mgr-s10","altr,sys-mgr";
	reg = <0xffd12000 0x500>;
	};

	timer0: timer0@ffc03000 {
	compatible = "snps,dw-apb-timer";
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffc03000 0x100>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	clock-names = "timer";
	};

	timer1: timer1@ffc03100 {
	compatible = "snps,dw-apb-timer";
	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffc03100 0x100>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	clock-names = "timer";
	};

	timer2: timer2@ffd00000 {
	compatible = "snps,dw-apb-timer";
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffd00000 0x100>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	clock-names = "timer";
	};

	timer3: timer3@ffd00100 {
	compatible = "snps,dw-apb-timer";
	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xffd00100 0x100>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	clock-names = "timer";
	};

	uart0: serial@ffc02000 {
	compatible = "snps,dw-apb-uart";
	reg = <0xffc02000 0x100>;
	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	resets = <&rst UART0_RESET>;
	status = "disabled";
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	};

	uart1: serial@ffc02100 {
	compatible = "snps,dw-apb-uart";
	reg = <0xffc02100 0x100>;
	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	reg-shift = <2>;
	reg-io-width = <4>;
	resets = <&rst UART1_RESET>;
	clocks = <&clkmgr AGILEX_L4_SP_CLK>;
	status = "disabled";
	};

	usb0: usb@ffb00000 {
	compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
	reg = <0xffb00000 0x40000>;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
	reset-names = "dwc2", "dwc2-ecc";
	clocks = <&clkmgr AGILEX_USB_CLK>;
	clock-names = "otg";
	iommus = <&smmu 6>;
	status = "disabled";
	};

	usb1: usb@ffb40000 {
	compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
	reg = <0xffb40000 0x40000>;
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&usbphy0>;
	phy-names = "usb2-phy";
	resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
	reset-names = "dwc2", "dwc2-ecc";
	iommus = <&smmu 7>;
	clocks = <&clkmgr AGILEX_USB_CLK>;
	status = "disabled";
	};

	watchdog0: watchdog@ffd00200 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00200 0x100>;
	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst WATCHDOG0_RESET>;
	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
	status = "disabled";
	};

	watchdog1: watchdog@ffd00300 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00300 0x100>;
	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst WATCHDOG1_RESET>;
	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
	status = "disabled";
	};

	watchdog2: watchdog@ffd00400 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00400 0x100>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst WATCHDOG2_RESET>;
	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
	status = "disabled";
	};

	watchdog3: watchdog@ffd00500 {
	compatible = "snps,dw-wdt";
	reg = <0xffd00500 0x100>;
	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
	resets = <&rst WATCHDOG3_RESET>;
	clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
	status = "disabled";
	};

	sdr: sdr@f8011100 {
	compatible = "altr,sdr-ctl", "syscon";
	reg = <0xf8011100 0xc0>;
	};

	eccmgr {
	compatible = "altr,socfpga-s10-ecc-manager",
	"altr,socfpga-a10-ecc-manager";
	altr,sysmgr-syscon = <&sysmgr>;
	#address-cells = <1>;
	#size-cells = <1>;
	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	ranges;

	sdramedac {
	compatible = "altr,sdram-edac-s10";
	altr,sdr-syscon = <&sdr>;
	interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
	};

	ocram-ecc@ff8cc000 {
	compatible = "altr,socfpga-s10-ocram-ecc",
	"altr,socfpga-a10-ocram-ecc";
	reg = <0xff8cc000 0x100>;
	altr,ecc-parent = <&ocram>;
	interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
	};

	usb0-ecc@ff8c4000 {
	compatible = "altr,socfpga-s10-usb-ecc",
	"altr,socfpga-usb-ecc";
	reg = <0xff8c4000 0x100>;
	altr,ecc-parent = <&usb0>;
	interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
	};

	emac0-rx-ecc@ff8c0000 {
	compatible = "altr,socfpga-s10-eth-mac-ecc",
	"altr,socfpga-eth-mac-ecc";
	reg = <0xff8c0000 0x100>;
	altr,ecc-parent = <&gmac0>;
	interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
	};

	emac0-tx-ecc@ff8c0400 {
	compatible = "altr,socfpga-s10-eth-mac-ecc",
	"altr,socfpga-eth-mac-ecc";
	reg = <0xff8c0400 0x100>;
	altr,ecc-parent = <&gmac0>;
	interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
	};

	sdmmca-ecc@ff8c8c00 {
	compatible = "altr,socfpga-s10-sdmmc-ecc",
	"altr,socfpga-sdmmc-ecc";
	reg = <0xff8c8c00 0x100>;
	altr,ecc-parent = <&mmc>;
	interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
	<15 IRQ_TYPE_LEVEL_HIGH>;
	};
	};

	qspi: spi@ff8d2000 {
	compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xff8d2000 0x100>,
	<0xff900000 0x100000>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	cdns,fifo-depth = <128>;
	cdns,fifo-width = <4>;
	cdns,trigger-address = <0x00000000>;
	clocks = <&qspi_clk>;

	status = "disabled";
	};

	firmware {
	svc {
	compatible = "intel,agilex-svc";
	method = "smc";
	memory-region = <&service_reserved>;

	fpga_mgr: fpga-mgr {
	compatible = "intel,agilex-soc-fpga-mgr";
	};
	};
	};
	};
	};