| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * (C) 2018 MediaTek Inc. |
| * Copyright (C) 2022 BayLibre SAS |
| * Fabien Parent <fparent@baylibre.com> |
| * Bernhard Rosenkränzer <bero@baylibre.com> |
| */ |
| #include <dt-bindings/clock/mediatek,mt8365-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/phy/phy.h> |
| |
| / { |
| compatible = "mediatek,mt8365"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x2>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2>; |
| }; |
| |
| l2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <0x80000>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| }; |
| }; |
| |
| clk26m: oscillator { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x10000>, /* GICD */ |
| <0 0x0c080000 0 0x80000>, /* GICR */ |
| <0 0x0c400000 0 0x2000>, /* GICC */ |
| <0 0x0c410000 0 0x1000>, /* GICH */ |
| <0 0x0c420000 0 0x2000>; /* GICV */ |
| |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt8365-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: syscon@10001000 { |
| compatible = "mediatek,mt8365-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pericfg: syscon@10003000 { |
| compatible = "mediatek,mt8365-pericfg", "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| syscfg_pctl: syscfg-pctl@10005000 { |
| compatible = "mediatek,mt8365-syscfg", "syscon"; |
| reg = <0 0x10005000 0 0x1000>; |
| }; |
| |
| pio: pinctrl@1000b000 { |
| compatible = "mediatek,mt8365-pinctrl"; |
| reg = <0 0x1000b000 0 0x1000>; |
| mediatek,pctl-regmap = <&syscfg_pctl>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| apmixedsys: syscon@1000c000 { |
| compatible = "mediatek,mt8365-apmixedsys", "syscon"; |
| reg = <0 0x1000c000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pwrap: pwrap@1000d000 { |
| compatible = "mediatek,mt8365-pwrap"; |
| reg = <0 0x1000d000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CLK_IFR_PWRAP_SPI>, |
| <&infracfg CLK_IFR_PMIC_AP>, |
| <&infracfg CLK_IFR_PWRAP_SYS>, |
| <&infracfg CLK_IFR_PWRAP_TMR>; |
| clock-names = "spi", "wrap", "sys", "tmr"; |
| }; |
| |
| keypad: keypad@10010000 { |
| compatible = "mediatek,mt6779-keypad"; |
| reg = <0 0x10010000 0 0x1000>; |
| wakeup-source; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; |
| clocks = <&clk26m>; |
| clock-names = "kpd"; |
| status = "disabled"; |
| }; |
| |
| mcucfg: syscon@10200000 { |
| compatible = "mediatek,mt8365-mcucfg", "syscon"; |
| reg = <0 0x10200000 0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| |
| sysirq: interrupt-controller@10200a80 { |
| compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10200a80 0 0x20>; |
| }; |
| |
| infracfg_nao: infracfg@1020e000 { |
| compatible = "mediatek,mt8365-infracfg", "syscon"; |
| reg = <0 0x1020e000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| rng: rng@1020f000 { |
| compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; |
| reg = <0 0x1020f000 0 0x100>; |
| clocks = <&infracfg CLK_IFR_TRNG>; |
| clock-names = "rng"; |
| }; |
| |
| apdma: dma-controller@11000280 { |
| compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; |
| reg = <0 0x11000280 0 0x80>, |
| <0 0x11000300 0 0x80>, |
| <0 0x11000380 0 0x80>, |
| <0 0x11000400 0 0x80>, |
| <0 0x11000580 0 0x80>, |
| <0 0x11000600 0 0x80>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; |
| dma-requests = <6>; |
| clocks = <&infracfg CLK_IFR_AP_DMA>; |
| clock-names = "apdma"; |
| #dma-cells = <1>; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x1000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 0>, <&apdma 1>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x1000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 2>, <&apdma 3>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x1000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 4>, <&apdma 5>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| pwm: pwm@11006000 { |
| compatible = "mediatek,mt8365-pwm"; |
| reg = <0 0x11006000 0 0x1000>; |
| #pwm-cells = <2>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_IFR_PWM_HCLK>, |
| <&infracfg CLK_IFR_PWM>, |
| <&infracfg CLK_IFR_PWM1>, |
| <&infracfg CLK_IFR_PWM2>, |
| <&infracfg CLK_IFR_PWM3>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; |
| reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <1>; |
| clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11008000 { |
| compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; |
| reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <1>; |
| clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11009000 { |
| compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; |
| reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <1>; |
| clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi: spi@1100a000 { |
| compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; |
| reg = <0 0x1100a000 0 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_IFR_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@1100f000 { |
| compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; |
| reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <1>; |
| clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| ssusb: usb@11201000 { |
| compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; |
| reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; |
| phys = <&u2port0 PHY_TYPE_USB2>, |
| <&u2port1 PHY_TYPE_USB2>; |
| clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, |
| <&infracfg CLK_IFR_SSUSB_REF>, |
| <&infracfg CLK_IFR_SSUSB_SYS>, |
| <&infracfg CLK_IFR_ICUSB>; |
| clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| usb_host: usb@11200000 { |
| compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; |
| reg = <0 0x11200000 0 0x1000>; |
| reg-names = "mac"; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, |
| <&infracfg CLK_IFR_SSUSB_REF>, |
| <&infracfg CLK_IFR_SSUSB_SYS>, |
| <&infracfg CLK_IFR_ICUSB>, |
| <&infracfg CLK_IFR_SSUSB_XHCI>; |
| clock-names = "sys_ck", "ref_ck", "mcu_ck", |
| "dma_ck", "xhci_ck"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11230000 0 0x1000>, |
| <0 0x11cd0000 0 0x1000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, |
| <&infracfg CLK_IFR_MSDC0_HCLK>, |
| <&infracfg CLK_IFR_MSDC0_SRC>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11240000 { |
| compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11240000 0 0x1000>, |
| <0 0x11c90000 0 0x1000>; |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, |
| <&infracfg CLK_IFR_MSDC1_HCLK>, |
| <&infracfg CLK_IFR_MSDC1_SRC>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc2: mmc@11250000 { |
| compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; |
| reg = <0 0x11250000 0 0x1000>, |
| <0 0x11c60000 0 0x1000>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, |
| <&infracfg CLK_IFR_MSDC2_HCLK>, |
| <&infracfg CLK_IFR_MSDC2_SRC>, |
| <&infracfg CLK_IFR_MSDC2_BK>, |
| <&infracfg CLK_IFR_AP_MSDC0>; |
| clock-names = "source", "hclk", "source_cg", |
| "bus_clk", "sys_cg"; |
| status = "disabled"; |
| }; |
| |
| ethernet: ethernet@112a0000 { |
| compatible = "mediatek,mt8365-eth"; |
| reg = <0 0x112a0000 0 0x1000>; |
| mediatek,pericfg = <&infracfg>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_ETH_SEL>, |
| <&infracfg CLK_IFR_NIC_AXI>, |
| <&infracfg CLK_IFR_NIC_SLV_AXI>; |
| clock-names = "core", "reg", "trans"; |
| status = "disabled"; |
| }; |
| |
| u3phy: t-phy@11cc0000 { |
| compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x11cc0000 0x9000>; |
| |
| u2port0: usb-phy@0 { |
| reg = <0x0 0x400>; |
| clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, |
| <&topckgen CLK_TOP_USB20_48M_EN>; |
| clock-names = "ref", "da_ref"; |
| #phy-cells = <1>; |
| }; |
| |
| u2port1: usb-phy@1000 { |
| reg = <0x1000 0x400>; |
| clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, |
| <&topckgen CLK_TOP_USB20_48M_EN>; |
| clock-names = "ref", "da_ref"; |
| #phy-cells = <1>; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| system_clk: dummy13m { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| systimer: timer@10017000 { |
| compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; |
| reg = <0 0x10017000 0 0x100>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&system_clk>; |
| clock-names = "clk13m"; |
| }; |
| }; |
