// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023, Linaro Limited
 */

#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		xo_board_clk: xo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_2>;
			L2_2: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_3>;
			L2_3: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@10000 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_4>;
			L2_4: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_1>;
				L3_1: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};

			};
		};

		CPU5: cpu@10100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_5>;
			L2_5: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_1>;
			};
		};

		CPU6: cpu@10200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10200>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_1>;
			};
		};

		CPU7: cpu@10300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10300>;
			enable-method = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_7>;
			L2_7: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-sa8775p", "qcom,scm";
		};
	};

	aggre1_noc: interconnect-aggre1-noc {
		compatible = "qcom,sa8775p-aggre1-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre2_noc: interconnect-aggre2-noc {
		compatible = "qcom,sa8775p-aggre2-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	clk_virt: interconnect-clk-virt {
		compatible = "qcom,sa8775p-clk-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	config_noc: interconnect-config-noc {
		compatible = "qcom,sa8775p-config-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	dc_noc: interconnect-dc-noc {
		compatible = "qcom,sa8775p-dc-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	gem_noc: interconnect-gem-noc {
		compatible = "qcom,sa8775p-gem-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	gpdsp_anoc: interconnect-gpdsp-anoc {
		compatible = "qcom,sa8775p-gpdsp-anoc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	lpass_ag_noc: interconnect-lpass-ag-noc {
		compatible = "qcom,sa8775p-lpass-ag-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect-mc-virt {
		compatible = "qcom,sa8775p-mc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mmss_noc: interconnect-mmss-noc {
		compatible = "qcom,sa8775p-mmss-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	nspa_noc: interconnect-nspa-noc {
		compatible = "qcom,sa8775p-nspa-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	nspb_noc: interconnect-nspb-noc {
		compatible = "qcom,sa8775p-nspb-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	pcie_anoc: interconnect-pcie-anoc {
		compatible = "qcom,sa8775p-pcie-anoc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect-system-noc {
		compatible = "qcom,sa8775p-system-noc";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	/* Will be updated by the bootloader. */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	qup_opp_table_100mhz: opp-table-qup100mhz {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs_l1>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		sail_ss_mem: sail-ss@80000000 {
			reg = <0x0 0x80000000 0x0 0x10000000>;
			no-map;
		};

		hyp_mem: hyp@90000000 {
			reg = <0x0 0x90000000 0x0 0x600000>;
			no-map;
		};

		xbl_boot_mem: xbl-boot@90600000 {
			reg = <0x0 0x90600000 0x0 0x200000>;
			no-map;
		};

		aop_image_mem: aop-image@90800000 {
			reg = <0x0 0x90800000 0x0 0x60000>;
			no-map;
		};

		aop_cmd_db_mem: aop-cmd-db@90860000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x90860000 0x0 0x20000>;
			no-map;
		};

		uefi_log: uefi-log@908b0000 {
			reg = <0x0 0x908b0000 0x0 0x10000>;
			no-map;
		};

		reserved_mem: reserved@908f0000 {
			reg = <0x0 0x908f0000 0x0 0xf000>;
			no-map;
		};

		secdata_apss_mem: secdata-apss@908ff000 {
			reg = <0x0 0x908ff000 0x0 0x1000>;
			no-map;
		};

		smem_mem: smem@90900000 {
			compatible = "qcom,smem";
			reg = <0x0 0x90900000 0x0 0x200000>;
			no-map;
			hwlocks = <&tcsr_mutex 3>;
		};

		cpucp_fw_mem: cpucp-fw@90b00000 {
			reg = <0x0 0x90b00000 0x0 0x100000>;
			no-map;
		};

		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
			reg = <0x0 0x93b00000 0x0 0xf00000>;
			no-map;
		};

		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
			reg = <0x0 0x94a00000 0x0 0x800000>;
			no-map;
		};

		pil_camera_mem: pil-camera@95200000 {
			reg = <0x0 0x95200000 0x0 0x500000>;
			no-map;
		};

		pil_adsp_mem: pil-adsp@95c00000 {
			reg = <0x0 0x95c00000 0x0 0x1e00000>;
			no-map;
		};

		pil_gdsp0_mem: pil-gdsp0@97b00000 {
			reg = <0x0 0x97b00000 0x0 0x1e00000>;
			no-map;
		};

		pil_gdsp1_mem: pil-gdsp1@99900000 {
			reg = <0x0 0x99900000 0x0 0x1e00000>;
			no-map;
		};

		pil_cdsp0_mem: pil-cdsp0@9b800000 {
			reg = <0x0 0x9b800000 0x0 0x1e00000>;
			no-map;
		};

		pil_gpu_mem: pil-gpu@9d600000 {
			reg = <0x0 0x9d600000 0x0 0x2000>;
			no-map;
		};

		pil_cdsp1_mem: pil-cdsp1@9d700000 {
			reg = <0x0 0x9d700000 0x0 0x1e00000>;
			no-map;
		};

		pil_cvp_mem: pil-cvp@9f500000 {
			reg = <0x0 0x9f500000 0x0 0x700000>;
			no-map;
		};

		pil_video_mem: pil-video@9fc00000 {
			reg = <0x0 0x9fc00000 0x0 0x700000>;
			no-map;
		};

		hyptz_reserved_mem: hyptz-reserved@beb00000 {
			reg = <0x0 0xbeb00000 0x0 0x11500000>;
			no-map;
		};

		tz_stat_mem: tz-stat@d0000000 {
			reg = <0x0 0xd0000000 0x0 0x100000>;
			no-map;
		};

		tags_mem: tags@d0100000 {
			reg = <0x0 0xd0100000 0x0 0x1200000>;
			no-map;
		};

		qtee_mem: qtee@d1300000 {
			reg = <0x0 0xd1300000 0x0 0x500000>;
			no-map;
		};

		trusted_apps_mem: trusted-apps@d1800000 {
			reg = <0x0 0xd1800000 0x0 0x3900000>;
			no-map;
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;

		gcc: clock-controller@100000 {
			compatible = "qcom,sa8775p-gcc";
			reg = <0x0 0x00100000 0x0 0xc7018>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&sleep_clk>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>;
			power-domains = <&rpmhpd SA8775P_CX>;
		};

		ipcc: mailbox@408000 {
			compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
			reg = <0x0 0x00408000 0x0 0x1000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#mbox-cells = <2>;
		};

		qupv3_id_2: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x008c0000 0x0 0x6000>;
			ranges;
			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
			clock-names = "m-ahb", "s-ahb";
			iommus = <&apps_smmu 0x5a3 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			spi16: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00888000 0x0 0x4000>;
				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
				clock-names = "se";
				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd SA8775P_CX>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart17: serial@88c000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0x0088c000 0x0 0x4000>;
				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
				clock-names = "se";
				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core", "qup-config";
				power-domains = <&rpmhpd SA8775P_CX>;
				status = "disabled";
			};

			i2c18: i2c@890000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00890000 0x0 0x4000>;
				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
				clock-names = "se";
				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd SA8775P_CX>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x00ac0000 0x0 0x6000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			iommus = <&apps_smmu 0x443 0x0>;
			status = "disabled";

			uart10: serial@a8c000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0x00a8c000 0x0 0x4000>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				interconnect-names = "qup-core", "qup-config";
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0
						 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_APPSS_PROC 0
						 &config_noc SLAVE_QUP_1 0>;
				power-domains = <&rpmhpd SA8775P_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;
				status = "disabled";
			};

			uart12: serial@a94000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0x00a94000 0x0 0x4000>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				clock-names = "se";
				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core", "qup-config";
				power-domains = <&rpmhpd SA8775P_CX>;
				status = "disabled";
			};
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x20000>;
			#hwlock-cells = <1>;
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
			reg = <0x0 0x0b220000 0x0 0x30000>,
			      <0x0 0x17c000f0 0x0 0x64>;
			qcom,pdc-ranges = <0 480 40>,
					  <40 140 14>,
					  <54 263 1>,
					  <55 306 4>,
					  <59 312 3>,
					  <62 374 2>,
					  <64 434 2>,
					  <66 438 2>,
					  <70 520 1>,
					  <73 523 1>,
					  <118 568 6>,
					  <124 609 3>,
					  <159 638 1>,
					  <160 720 3>,
					  <169 728 30>,
					  <199 416 2>,
					  <201 449 1>,
					  <202 89 1>,
					  <203 451 1>,
					  <204 462 1>,
					  <205 264 1>,
					  <206 579 1>,
					  <207 653 1>,
					  <208 656 1>,
					  <209 659 1>,
					  <210 122 1>,
					  <211 699 1>,
					  <212 705 1>,
					  <213 450 1>,
					  <214 643 2>,
					  <216 646 5>,
					  <221 390 5>,
					  <226 700 2>,
					  <228 440 1>,
					  <229 663 1>,
					  <230 524 2>,
					  <232 612 3>,
					  <235 723 5>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0 0x0c440000 0x0 0x1100>,
			      <0x0 0x0c600000 0x0 0x2000000>,
			      <0x0 0x0e600000 0x0 0x100000>,
			      <0x0 0x0e700000 0x0 0xa0000>,
			      <0x0 0x0c40a000 0x0 0x26000>;
			reg-names = "core",
				    "chnls",
				    "obsrvr",
				    "intr",
				    "cnfg";
			qcom,channel = <0>;
			qcom,ee = <0>;
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "periph_irq";
			interrupt-controller;
			#interrupt-cells = <4>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		tlmm: pinctrl@f000000 {
			compatible = "qcom,sa8775p-tlmm";
			reg = <0x0 0x0f000000 0x0 0x1000000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 149>;
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
			reg = <0x0 0x15000000 0x0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <2>;

			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
		};

		memtimer: timer@17c20000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x17c20000 0x0 0x1000>;
			ranges = <0x0 0x0 0x0 0x20000000>;
			#address-cells = <1>;
			#size-cells = <1>;

			frame@17c21000 {
				reg = <0x17c21000 0x1000>,
				      <0x17c22000 0x1000>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <0>;
			};

			frame@17c23000 {
				reg = <0x17c23000 0x1000>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <1>;
				status = "disabled";
			};

			frame@17c25000 {
				reg = <0x17c25000 0x1000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <2>;
				status = "disabled";
			};

			frame@17c27000 {
				reg = <0x17c27000 0x1000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <3>;
				status = "disabled";
			};

			frame@17c29000 {
				reg = <0x17c29000 0x1000>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <4>;
				status = "disabled";
			};

			frame@17c2b000 {
				reg = <0x17c2b000 0x1000>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <5>;
				status = "disabled";
			};

			frame@17c2d000 {
				reg = <0x17c2d000 0x1000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				frame-number = <6>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@18200000 {
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x18200000 0x0 0x10000>,
			      <0x0 0x18210000 0x0 0x10000>,
			      <0x0 0x18220000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS 2>,
					  <SLEEP_TCS 3>,
					  <WAKE_TCS 3>,
					  <CONTROL_TCS 0>;
			label = "apps_rsc";

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,sa8775p-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board_clk>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sa8775p-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp-0 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp-1 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp-4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp-5 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp-6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp-7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp-8 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp-9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		cpufreq_hw: cpufreq@18591000 {
			compatible = "qcom,sa8775p-cpufreq-epss",
				     "qcom,cpufreq-epss";
			reg = <0x0 0x18591000 0x0 0x1000>,
			      <0x0 0x18593000 0x0 0x1000>;
			reg-names = "freq-domain0", "freq-domain1";

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
			clock-names = "xo", "alternate";

			#freq-domain-cells = <1>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};