Device-Tree bindings for Samsung SoC display controller (FIMD)

FIMD (Fully Interactive Mobile Display) is the Display Controller for the
Samsung series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.

Required properties:
- compatible: value should be one of the following
		"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
		"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
		"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
		"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
		"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */

- reg: physical base address and length of the FIMD registers set.

- interrupt-parent: should be the phandle of the fimd controller's
		parent interrupt controller.

- interrupts: should contain a list of all FIMD IP block interrupts in the
		 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
		 format depends on the interrupt controller used.

- interrupt-names: should contain the interrupt names: "fifo", "vsync",
	"lcd_sys", in the same order as they were listed in the interrupts
        property.

- pinctrl-0: pin control group to be used for this controller.

- pinctrl-names: must contain a "default" entry.

- clocks: must include clock specifiers corresponding to entries in the
         clock-names property.

- clock-names: list of clock names sorted in the same order as the clocks
               property. Must contain "sclk_fimd" and "fimd".

Optional Properties:
- samsung,power-domain: a phandle to FIMD power domain node.
- samsung,invert-vden: video enable signal is inverted
- samsung,invert-vclk: video clock signal is inverted
- display-timings: timing settings for FIMD, as described in document [1].
		Can be used in case timings cannot be provided otherwise
		or to override timings provided by the panel.
- samsung,sysreg: handle to syscon used to control the system registers
- i80-if-timings: timing configuration for lcd i80 interface support.
  - cs-setup: clock cycles for the active period of address signal is enabled
              until chip select is enabled.
              If not specified, the default value(0) will be used.
  - wr-setup: clock cycles for the active period of CS signal is enabled until
              write signal is enabled.
              If not specified, the default value(0) will be used.
  - wr-active: clock cycles for the active period of CS is enabled.
               If not specified, the default value(1) will be used.
  - wr-hold: clock cycles for the active period of CS is disabled until write
             signal is disabled.
             If not specified, the default value(0) will be used.

  The parameters are defined as:

    VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??
                      :            :            :            :            :
    Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
                      | cs-setup+1 |            :            :            :
                      |<---------->|            :            :            :
    Chip Select     ???????????????|____________:____________:____________|??
                                   | wr-setup+1 |            | wr-hold+1  |
                                   |<---------->|            |<---------->|
    Write Enable    ????????????????????????????|____________|???????????????
                                                | wr-active+1|
                                                |<---------->|
    Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--

The device node can contain 'port' child nodes according to the bindings defined
in [2]. The following are properties specific to those nodes:
- reg: (required) port index, can be:
		0 - for CAMIF0 input,
		1 - for CAMIF1 input,
		2 - for CAMIF2 input,
		3 - for parallel output,
		4 - for write-back interface

[1]: Documentation/devicetree/bindings/video/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:

SoC specific DT entry:

	fimd@11c00000 {
		compatible = "samsung,exynos4210-fimd";
		interrupt-parent = <&combiner>;
		reg = <0x11c00000 0x20000>;
		interrupt-names = "fifo", "vsync", "lcd_sys";
		interrupts = <11 0>, <11 1>, <11 2>;
		clocks = <&clock 140>, <&clock 283>;
		clock-names = "sclk_fimd", "fimd";
		samsung,power-domain = <&pd_lcd0>;
		status = "disabled";
	};

Board specific DT entry:

	fimd@11c00000 {
		pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
		pinctrl-names = "default";
		status = "okay";
	};