tree aeee912e0f9fd054bd8bf4bf436426ba07ef2077
parent 865c8064a2fb07100525097983966b8e789bde1a
author San Mehat <san@google.com> 1258395450 -0800
committer Daniel Walker <dwalker@codeaurora.org> 1268943347 -0700

mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays

As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*

    Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.

Signed-off-by: San Mehat <san@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>