| /* |
| * Copyright (C) 2021 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #ifndef _dpcs_2_0_3_OFFSET_HEADER |
| #define _dpcs_2_0_3_OFFSET_HEADER |
| // addressBlock: dpcssysa_dpcs0_dpcstx0_dispdec |
| // base address: 0x0 |
| #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 |
| #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 |
| #define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 |
| #define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 |
| #define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a |
| #define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 |
| #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b |
| #define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 |
| #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c |
| #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 |
| #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d |
| #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dpcssysa_dpcs0_rdpcstx0_dispdec |
| // base address: 0x0 |
| #define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 |
| #define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 |
| #define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 |
| #define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 |
| #define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 |
| #define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 |
| #define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939 |
| #define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e |
| #define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
| |
| |
| // addressBlock: dpcssysa_dpcs0_dpcstx1_dispdec |
| // base address: 0x360 |
| #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 |
| #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 |
| #define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 |
| #define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 |
| #define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 |
| #define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 |
| #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 |
| #define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 |
| #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 |
| #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 |
| #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 |
| #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 |
| |
| |
| // addressBlock: dpcssysa_dpcs0_rdpcstx1_dispdec |
| // base address: 0x360 |
| #define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 |
| #define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 |
| #define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a |
| #define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b |
| #define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c |
| #define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d |
| #define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a11 |
| #define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 |
| #define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
| |
| #endif |
