| commit | 8bdb65dc8575978214785462870852a56b6a21ac | [log] [tgz] |
|---|---|---|
| author | Zhi Mao <zhi.mao@mediatek.com> | Fri Jun 30 14:05:20 2017 +0800 |
| committer | Thierry Reding <thierry.reding@gmail.com> | Mon Aug 21 10:39:11 2017 +0200 |
| tree | fb421e982b77d6e0afae2e3fc8f7217e4af4093c | |
| parent | 62843a6152e7c19f28c368bb51cac1bbfcdf4249 [diff] |
pwm: mediatek: Disable clock on PWM configuration failure Make sure to disable the PWM clock if the PWM cannot be configured due to the clock divider exceeding the maximum value. While at it, replace the hardcoded maximum clock divider with a defined constant to improve code readability. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>