tree 1d3c0176ccd7fccf07bc5bfb24dffa43af7fc6c7
parent 0fcfb00b28c0b7884635dacf38e46d60bf3d4eb1
author Samuel Holland <samuel@sholland.org> 1637205521 -0600
committer Chanwoo Choi <cw00.choi@samsung.com> 1639119367 +0900

PM / devfreq: Add a driver for the sun8i/sun50i MBUS

This driver works by adjusting the divider on the DRAM controller's
module clock. Thus there is no fixed set of OPPs, only "full speed" down
to "quarter speed" (or whatever the maximum divider is on that variant).

It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which
takes care of updating registers during the critical section while DRAM
is inaccessible.

This driver should support several sunxi SoCs, starting with the A33,
which have a DesignWare DDR3 controller with merged PHY register space
and the matching MBUS register layout (so not A63 or later). However,
the driver has only been tested on the A64/H5, so those are the only
compatibles enabled for now.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>