// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 BayLibre, SAS.
 * Author: Jerome Brunet <jbrunet@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-g12b-a311d.dtsi"
#include "meson-libretech-cottonwood.dtsi"

/ {
	compatible = "libretech,aml-a311d-cc", "amlogic,a311d", "amlogic,g12b";
	model = "Libre Computer AML-A311D-CC Alta";

	vddcpu_a: regulator-vddcpu-a {
		compatible = "pwm-regulator";
		regulator-name = "VDDCPU_A";
		regulator-min-microvolt = <730000>;
		regulator-max-microvolt = <1011000>;
		regulator-boot-on;
		regulator-always-on;
		pwm-supply = <&dc_in>;
		pwms = <&pwm_ab 0 1250 0>;
		pwm-dutycycle-range = <100 0>;
	};

	sound {
		model = "LC-ALTA";
		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
				"TDMOUT_A IN 1", "FRDDR_B OUT 0",
				"TDMOUT_A IN 2", "FRDDR_C OUT 0",
				"TDM_A Playback", "TDMOUT_A OUT",
				"TDMOUT_B IN 0", "FRDDR_A OUT 1",
				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
				"TDM_B Playback", "TDMOUT_B OUT",
				"TDMOUT_C IN 0", "FRDDR_A OUT 2",
				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
				"TDM_C Playback", "TDMOUT_C OUT",
				"TDMIN_A IN 0", "TDM_A Capture",
				"TDMIN_B IN 0", "TDM_A Capture",
				"TDMIN_C IN 0", "TDM_A Capture",
				"TDMIN_A IN 3", "TDM_A Loopback",
				"TDMIN_B IN 3", "TDM_A Loopback",
				"TDMIN_C IN 3", "TDM_A Loopback",
				"TDMIN_A IN 1", "TDM_B Capture",
				"TDMIN_B IN 1", "TDM_B Capture",
				"TDMIN_C IN 1", "TDM_B Capture",
				"TDMIN_A IN 4", "TDM_B Loopback",
				"TDMIN_B IN 4", "TDM_B Loopback",
				"TDMIN_C IN 4", "TDM_B Loopback",
				"TDMIN_A IN 2", "TDM_C Capture",
				"TDMIN_B IN 2", "TDM_C Capture",
				"TDMIN_C IN 2", "TDM_C Capture",
				"TDMIN_A IN 5", "TDM_C Loopback",
				"TDMIN_B IN 5", "TDM_C Loopback",
				"TDMIN_C IN 5", "TDM_C Loopback",
				"TODDR_A IN 0", "TDMIN_A OUT",
				"TODDR_B IN 0", "TDMIN_A OUT",
				"TODDR_C IN 0", "TDMIN_A OUT",
				"TODDR_A IN 1", "TDMIN_B OUT",
				"TODDR_B IN 1", "TDMIN_B OUT",
				"TODDR_C IN 1", "TDMIN_B OUT",
				"TODDR_A IN 2", "TDMIN_C OUT",
				"TODDR_B IN 2", "TDMIN_C OUT",
				"TODDR_C IN 2", "TDMIN_C OUT",
				"Lineout", "ACODEC LOLP",
				"Lineout", "ACODEC LORP";
	};
};

&cpu0 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
};

&cpu1 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table_0>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
};

&cpu100 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
};

&cpu101 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
};

&cpu102 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
};

&cpu103 {
	cpu-supply = <&vddcpu_a>;
	operating-points-v2 = <&cpub_opp_table_1>;
	clocks = <&clkc CLKID_CPUB_CLK>;
	clock-latency = <50000>;
};

&pwm_ab {
	pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x7_pins>;
	clocks = <&xtal>, <&xtal>;
	clock-names = "clkin0", "clkin1";
};