| commit | 8d11f21a73e662fa11f39447de629cd8caa485c9 | [log] [tgz] |
|---|---|---|
| author | Guo Ren <guoren@linux.alibaba.com> | Sun Dec 20 03:39:27 2020 +0000 |
| committer | Guo Ren <guoren@linux.alibaba.com> | Tue Jan 12 09:52:40 2021 +0800 |
| tree | 5aa937f17bd6579d02cb046c34f812b1e41e5a18 | |
| parent | f92ddfb7b5415536e4fe4c7a4868737954159374 [diff] |
csky: Fixup barrier design Remove shareable bit for ordering barrier, just keep ordering in current hart is enough for SMP. Using three continuous sync.is as PTW barrier to prevent speculative PTW in 860 microarchitecture. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>