// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	chosen {
		stdout-path = &uart2;
	};

	aliases {
		can0 = &can1;
		can1 = &can2;
		ethernet0 = &fec;
		ethernet1 = &lan1;
		ethernet2 = &lan2;
		mdio-gpio0 = &mdio;
		nand = &gpmi;
		rtc0 = &i2c_rtc;
		rtc1 = &snvs;
		switch0 = &switch;
		usb0 = &usbh1;
		usb1 = &usbotg;
	};

	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&adc 0>, /* 24V */
		              <&adc 1>; /* temperature */
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "D1";
			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
			function = LED_FUNCTION_STATUS;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			label = "D2";
			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-2 {
			label = "D3";
			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	mdio: mdio {
		compatible = "microchip,mdio-smi0";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mdio>;
		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
			<&gpio1 22 GPIO_ACTIVE_HIGH>;

		switch: switch@0 {
			compatible = "microchip,ksz8873";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_switch>;
			interrupt-parent = <&gpio3>;
			interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
			reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
			reg = <0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				lan1: ports@0 {
					reg = <0>;
					phy-mode = "internal";
					label = "lan1";
				};

				lan2: ports@1 {
					reg = <1>;
					phy-mode = "internal";
					label = "lan2";
				};

				ports@2 {
					reg = <2>;
					label = "cpu";
					ethernet = <&fec>;
					phy-mode = "rmii";

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};
			};
		};

	};

	clk50m_phy: phy-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "enet_ref_pad";
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		vin-supply = <&reg_5v0>;
		regulator-name = "3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_24v0: regulator-24v0 {
		compatible = "regulator-fixed";
		regulator-name = "24v0";
		regulator-min-microvolt = <24000000>;
		regulator-max-microvolt = <24000000>;
	};

	reg_can1_stby: regulator-can1-stby {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can1_stby>;
		regulator-name = "can1-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can2_stby>;
		regulator-name = "can2-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
	};

	reg_tft_vcom: regulator-tft-vcom {
		compatible = "pwm-regulator";
		pwms = <&pwm3 0 20000 0>;
		regulator-name = "tft_vcom";
		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;
		regulator-always-on;
		voltage-table = <3600000 26>;
	};

	reg_vcc_mmc: regulator-vcc-mmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_vcc_mmc>;
		vin-supply = <&reg_3v3>;
		regulator-name = "mmc_vcc_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
	};

	reg_vcc_mmc_io: regulator-vcc-mmc-io {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_vcc_mmc_io>;
		vin-supply = <&reg_5v0>;
		regulator-name = "mmc_io_supply";
		regulator-type = "voltage";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		states = <1800000 0x1>, <3300000 0x0>;
		startup-delay-us = <100>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_can1_stby>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can2>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <54000000>;
		reg = <0>;
	};
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
	status = "okay";

	adc: adc@0 {
		compatible = "microchip,mcp3002";
		reg = <0>;
		vref-supply = <&reg_3v3>;
		spi-max-frequency = <1000000>;
		#io-channel-cells = <1>;
	};
};

&clks {
	clocks = <&clk50m_phy>;
	clock-names = "enet_ref_pad";
	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
	assigned-clock-parents = <&clk50m_phy>;
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rmii";
	phy-supply = <&reg_3v3>;
	status = "okay";

	fixed-link {
		speed = <100>;
		full-duplex;
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <400000>;
	status = "okay";

	i2c_rtc: rtc@51 {
		compatible = "nxp,pcf85063";
		reg = <0x51>;
		quartz-load-femtofarads = <12500>;
	};
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	#pwm-cells = <2>;
	status = "okay";
};

&pwm3 {
	/* used for LCD contrast control */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_5v0>;
	disable-over-current;
	status = "okay";
};

/* no usbh2 */
&usbphynop1 {
	status = "disabled";
};

/* no usbh3 */
&usbphynop2 {
	status = "disabled";
};

&usbotg {
	vbus-supply = <&reg_5v0>;
	disable-over-current;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
	cap-power-off-card;
	full-pwr-cycle;
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-ddr50;
	mmc-ddr-1_8v;
	vmmc-supply = <&reg_vcc_mmc>;
	vqmmc-supply = <&reg_vcc_mmc_io>;
	status = "okay";
};

&iomuxc {
	pinctrl_can1: can1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX			0x3008
			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX			0x1b000
		>;
	};

	pinctrl_can1_stby: can1stbygrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D31__GPIO3_IO31			0x13008
		>;
	};

	pinctrl_can2: can2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX		0x3008
			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX		0x1b000
		>;
	};

	pinctrl_can2_stby: can2stbygrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11			0x13008
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D17__ECSPI1_MISO			0x100b1
			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI			0xb1
			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK			0xb1
			/* *no* external pull up */
			MX6QDL_PAD_EIM_D24__GPIO3_IO24			0x58
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_OE__ECSPI2_MISO			0x100b1
			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI			0xb1
			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK			0xb1
			/* external pull up */
			MX6QDL_PAD_EIM_RW__GPIO2_IO26			0x58
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			/* RMII 50 MHz */
			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x100f5
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x100f5
			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x100c0
			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x100c0
			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x100f5
			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x100f5
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0
			MX6QDL_PAD_GPIO_5__GPIO1_IO05			0x58
			/* GPIO for "link active" */
			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24		0x3038
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6QDL_PAD_NANDF_CLE__NAND_CLE			0xb0b1
			MX6QDL_PAD_NANDF_ALE__NAND_ALE			0xb0b1
			MX6QDL_PAD_NANDF_RB0__NAND_READY_B		0xb000
			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B		0xb0b1
			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B		0xb0b1
			MX6QDL_PAD_SD4_CMD__NAND_RE_B			0xb0b1
			MX6QDL_PAD_SD4_CLK__NAND_WE_B			0xb0b1
			MX6QDL_PAD_NANDF_D0__NAND_DATA00		0xb0b1
			MX6QDL_PAD_NANDF_D1__NAND_DATA01		0xb0b1
			MX6QDL_PAD_NANDF_D2__NAND_DATA02		0xb0b1
			MX6QDL_PAD_NANDF_D3__NAND_DATA03		0xb0b1
			MX6QDL_PAD_NANDF_D4__NAND_DATA04		0xb0b1
			MX6QDL_PAD_NANDF_D5__NAND_DATA05		0xb0b1
			MX6QDL_PAD_NANDF_D6__NAND_DATA06		0xb0b1
			MX6QDL_PAD_NANDF_D7__NAND_DATA07		0xb0b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			/* external 10 k pull up */
			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x40010878
			/* external 10 k pull up */
			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x40010878
		>;
	};

	pinctrl_mdio: mdiogrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__GPIO1_IO22		0x100b1
			MX6QDL_PAD_ENET_MDC__GPIO1_IO31			0xb1
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_1__PWM2_OUT			0x58
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_DAT1__PWM3_OUT			0x58
		>;
	};

	pinctrl_switch: switchgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D30__GPIO3_IO30			0xb0
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D26__UART2_TX_DATA		0x1b0b1
			MX6QDL_PAD_EIM_D27__UART2_RX_DATA		0x1b0b1
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			/* SoC internal pull up required */
			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17059
			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10059
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17059
			/* SoC internal pull up required */
			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01			0x1b040
			/* SoC internal pull up required */
			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00			0x1b040
		>;
	};

	pinctrl_vcc_mmc: vccmmcgrp {
		fsl,pins = <
			MX6QDL_PAD_SD3_RST__GPIO7_IO08			0x58
		>;
	};

	pinctrl_vcc_mmc_io: vccmmciogrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_18__GPIO7_IO13			0x58
		>;
	};
};