// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2162A Clearfog
//
// Copyright 2023 Josua Mayer <josua@solid-run.com>

/dts-v1/;

#include "fsl-lx2160a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"

/ {
	model = "SolidRun LX2162A Clearfog";
	compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";

	aliases {
		crypto = &crypto;
		i2c0 = &i2c0;
		i2c1 = &i2c2;
		i2c2 = &i2c4;
		i2c3 = &sfp_i2c0;
		i2c4 = &sfp_i2c1;
		i2c5 = &sfp_i2c2;
		i2c6 = &sfp_i2c3;
		i2c7 = &mpcie1_i2c;
		i2c8 = &mpcie0_i2c;
		i2c9 = &pcieclk_i2c;
		mmc0 = &esdhc0;
		mmc1 = &esdhc1;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led_sfp_at: led-sfp-at {
			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
			default-state = "off";
		};

		led_sfp_ab: led-sfp-ab {
			gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
			default-state = "off";
		};

		led_sfp_bt: led-sfp-bt {
			gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
			default-state = "off";
		};

		led_sfp_bb: led-sfp-bb {
			gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
			default-state = "off";
		};
	};

	sfp_at: sfp-at {
		compatible = "sff,sfp";
		i2c-bus = <&sfp_i2c0>;
		mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
		maximum-power-milliwatt = <2000>;
	};

	sfp_ab: sfp-ab {
		compatible = "sff,sfp";
		i2c-bus = <&sfp_i2c1>;
		mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
		maximum-power-milliwatt = <2000>;
	};

	sfp_bt: sfp-bt {
		compatible = "sff,sfp";
		i2c-bus = <&sfp_i2c2>;
		mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
		maximum-power-milliwatt = <2000>;
	};

	sfp_bb: sfp-bb {
		compatible = "sff,sfp";
		i2c-bus = <&sfp_i2c3>;
		mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
		maximum-power-milliwatt = <2000>;
	};
};

&dpmac3 {
	sfp = <&sfp_at>;
	managed = "in-band-status";
	phys = <&serdes_1 7>;
};

&dpmac4 {
	sfp = <&sfp_ab>;
	managed = "in-band-status";
	phys = <&serdes_1 6>;
};

&dpmac5 {
	sfp = <&sfp_bt>;
	managed = "in-band-status";
	phys = <&serdes_1 5>;
};

&dpmac6 {
	sfp = <&sfp_bb>;
	managed = "in-band-status";
	phys = <&serdes_1 4>;
};

&dpmac11 {
	phys = <&serdes_2 0>;
	phy-handle = <&ethernet_phy3>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac12 {
	phys = <&serdes_2 1>;
	phy-handle = <&ethernet_phy1>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac13 {
	phys = <&serdes_2 6>;
	phy-handle = <&ethernet_phy6>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac14 {
	phys = <&serdes_2 7>;
	phy-handle = <&ethernet_phy8>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac15 {
	phys = <&serdes_2 4>;
	phy-handle = <&ethernet_phy4>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac16 {
	phys = <&serdes_2 5>;
	phy-handle = <&ethernet_phy2>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac17 {
	/* override connection to on-SoM phy */
	/delete-property/ phy-handle;
	/delete-property/ phy-connection-type;

	phys = <&serdes_2 2>;
	phy-handle = <&ethernet_phy5>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&dpmac18 {
	phys = <&serdes_2 3>;
	phy-handle = <&ethernet_phy7>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&emdio1 {
	ethernet_phy1: ethernet-phy@8 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <8>;
		max-speed = <1000>;
	};

	ethernet_phy2: ethernet-phy@9 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <9>;
		max-speed = <1000>;
	};

	ethernet_phy3: ethernet-phy@10 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <10>;
		max-speed = <1000>;
	};

	ethernet_phy4: ethernet-phy@11 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <11>;
		max-speed = <1000>;
	};

	ethernet_phy5: ethernet-phy@12 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <12>;
		max-speed = <1000>;
	};

	ethernet_phy6: ethernet-phy@13 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <13>;
		max-speed = <1000>;
	};

	ethernet_phy7: ethernet-phy@14 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <14>;
		max-speed = <1000>;
	};

	ethernet_phy8: ethernet-phy@15 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <15>;
		max-speed = <1000>;
	};
};

&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&ethernet_phy0 {
	/*
	 * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
	 * It competes for WRIOP MAC17, and no connector has been wired.
	 */
	status = "disabled";
};

&i2c2 {
	status = "okay";

	/* retimer@18 */

	i2c-mux@70 {
		compatible = "nxp,pca9546";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;

		sfp_i2c0: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		sfp_i2c1: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		sfp_i2c2: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		sfp_i2c3: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
	};

	i2c-mux@71 {
		compatible = "nxp,pca9546";
		reg = <0x71>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;

		mpcie1_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		mpcie0_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		pcieclk_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			/* clock-controller@6b */
		};
	};
};

&pcie3 {
	status = "disabled";
};

&pcie4 {
	status = "disabled";
};

&pcs_mdio3 {
	status = "okay";
};

&pcs_mdio4 {
	status = "okay";
};

&pcs_mdio5 {
	status = "okay";
};

&pcs_mdio6 {
	status = "okay";
};

&pcs_mdio11 {
	status = "okay";
};

&pcs_mdio12 {
	status = "okay";
};

&pcs_mdio13 {
	status = "okay";
};

&pcs_mdio14 {
	status = "okay";
};

&pcs_mdio15 {
	status = "okay";
};

&pcs_mdio16 {
	status = "okay";
};

&pcs_mdio17 {
	status = "okay";
};

&pcs_mdio18 {
	status = "okay";
};

&serdes_1 {
	status = "okay";
};

&serdes_2 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb0 {
	status = "okay";
};